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Microelectronic Package With Three Dimensional (3 D) Monolithic Memory Die

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
10 December 2020
Publication Number
50/2021
Publication Type
INA
Invention Field
ELECTRICAL
Status
Email
ipo@iphorizons.com
Parent Application

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California 95054, USA

Inventors

1. WILFRED GOMES
3393 NW 125 Place Portland, OR 97229 USA
2. MAURO J. KOBRINSKY
14197 NW Stonebridge Drive Portland, OR 97229 USA
3. DOUG B. INGERLY
5485 NW Tamarron Place Portland, OR 97229 USA
4. TAHIR GHANI
14191 NW Stonebridge Drive Portland, OR 97229 USA

Specification

Claims:1. A microelectronic package comprising:
a package substrate;
an active die; and
a memory die communicatively coupled with the package substrate and the active die, wherein the memory die includes:
a first memory cell at a first layer of the memory die;
a second memory cell at a second layer of the memory die; and
a via in the memory die that communicatively couples the active die with the package substrate.
, Description:Background
[0002] Mobile devices such as smart phones may include significant amounts of memory. For example, some mobile devices may have between approximately 4 and approximately 16 gigabytes (GB) of package-on-package (POP) memory.

Brief Description of the Drawings
[0003] Figure 1 depicts an example microelectronic package with a three-dimensional (3D) monolithic memory die, in accordance with various embodiments.
[0004] Figure 2 depicts an example of a memory cell of a 3D monolithic memory die, in accordance with various embodiments.
[0005] Figure 3 depicts an example circuit architecture of a 3D monolithic memory die, in accordance with various embodiments.
[0006] Figure 4 is a top view of a wafer and dies that may be or include a 3D monolithic memory die, in accordance with various embodiments.
[0007] Figure 5 is a side, cross-sectional view of an integrated circuit (IC) device assembly that may include a microelectronic package with a 3D monolithic memory die, in accordance with various embodiments.
[0008] Figure 6 is a block diagram of an example electrical device that may include a microelectronic package with a 3D monolithic memory die, in accordance with various embodiments.
Detailed Description
[0009] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
[0010] For the purposes of the present disclosure, the phrase “A or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0011] The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
[0012] The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
[0013] The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or elements are in direct contact.

Documents

Application Documents

# Name Date
1 202044053670-FORM 1 [10-12-2020(online)].pdf 2020-12-10
2 202044053670-DRAWINGS [10-12-2020(online)].pdf 2020-12-10
3 202044053670-DECLARATION OF INVENTORSHIP (FORM 5) [10-12-2020(online)].pdf 2020-12-10
4 202044053670-COMPLETE SPECIFICATION [10-12-2020(online)].pdf 2020-12-10
5 202044053670-FORM-26 [27-02-2021(online)].pdf 2021-02-27
6 202044053670-FORM 3 [08-06-2021(online)].pdf 2021-06-08
7 202044053670-FORM 3 [10-12-2021(online)].pdf 2021-12-10
8 202044053670-FORM 18 [15-05-2024(online)].pdf 2024-05-15