CLIAMS:1. A 3D chip comprising:
level-1 comprising one or more group III – Nitride based high electron mobility transistors and diodes disposed over any or a combination of Si, SiC, and Al2O3substrate;
level-2 comprising molybdenum disulphide (MoS2) based mixed signal IC;
level-3 comprising super inductors fabricated using metallic Carbon Nanotubes;
level-4 comprising super capacitors, wherein the super capacitors are fabricated using graphene sheets;
one or more intermediate levels comprising lateral heat transporters and vertical EMI shields; and
one or more vertical heat transporters and lateral EMI shields.
2. The 3D chip of claim 1, further comprising interconnects and vias, wherein said interconnects and vias are fabricated using metallic carbon nanotubes, and wherein said levels are stacked on top of each other and encapsulated inside a single package along with the vertical heat transporters, the lateral EMI shields, the interconnects, and the vias.
3. The 3D chip of claim 1, wherein one or more of the levels are used in different combinations and orders.
4. The 3D chip of claim 1, wherein one or more of the levels have local electrical interconnection and are globally electrically isolated from each other by one or more interlayer dielectric interlayers.
5. The 3D chip of claim 1, wherein the lateral heat transporters and the vertical EMI shields are made of any or a combination of a metal, graphene, and stack of a metal and graphene.
6. The 3D chip of claim 1, wherein the lateral heat transporters are sandwiched between dielectric interlayers, wherein the dielectric interlayers are made of thermally conducting material.
7. The 3D chip of claim 1, wherein the vertical heat transporters and the lateral EMI shields are made of any or a combination of a metal, graphene, stack of a metal and graphene, and stack of metal and CNT, and wherein the vertical heat transporters and the lateral EMI shields are disposed anywhere on the chip.
8. The 3D chip of claim 1, wherein level-2 uses2-dimentional materials elected from one or a combination of transition metal dichalcogenide, WS2, WSe2, stack of 2-dimentional materials, or Si/SiGe produced using metal induced crystallization.
9. The 3D chip of claim 1, wherein level-3 uses metallic, high conducting, and super conducting material.
10. The 3D chip of claim 1, wherein level-4 uses a material selected from a group comprising dielectric material, graphene sheet, activated graphene, quantum nanocluster of metal oxides, graphite oxide, and SWNT composite electrodes.
11. The 3D chip of claim 1, wherein the interconnects and the vias are fabricated using a high/super conducting material selected from a group comprising through-Silicon-Via (TSV), metallic Carbon Nanotubes, and graphene.
12. The 3D chip of claim 1, wherein the level-2, the level-3, and the level-4 are integrated in a single level.
13. The 3D chip of claim 1, wherein the level-2 is distributed over more than one IC.
14. The 3D chip of claim 1, wherein the level-3 comprises at least one of a super conductor and a transformer.
15. The 3D chip of claim 1, wherein the chip is any or a combination of a high power density power convertor, a high power density power inverter, a high power RF trans-receiver, and a RF power amplifier.
,TagSPECI:TECHNICAL FIELD
[0001] The present disclosure generally relates to the field of power electronics. In particular it pertains to a 3D power system on a chip that incorporates power devices with µ-Nano device technology.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Innovations in power MOSFET structures, technology, and circuit topologies during last few decades of last century steadily improved the power management efficiency and reduced cost contributing to pace of growing need for electrical power in our daily lives. Application space of power electronic devices and technology has grown tremendously with penetration of consumer electronic devices. FIG. 1 illustrates an exemplary application of power electronics in a typical modern mobile phone indicating extent of application of power electronics in consumer electronic products. However, application of power electronic devices is not limited to consumer electronic devices and penetrates every conceivable field such as automobile, space, communication networks, defense, railways, machine tool industry to name a few. It is evident all these fields have benefitted from advances in the field of power electronics.
[0004] In the new millennium, however, the rate of improvement in the field of power electronics has slowed down as the silicon power MOSFET asymptotically approached its theoretical bounds. It would not be an exaggeration to say that very soon users and therefore power electronics industry will look for further miniaturization of power electronic systems in order to reduce size, weight, and cost and increase power density. In fact keeping in mind that a good percentage weight and cost in many products is dominated by power management modules, miniaturization of these modules is already a desperate requirement.
[0005] Typical power electronic circuits incorporate monolithic ICs, hybrid, surface mount and wire-bond technology. A close examination of the power electronic applications indicates that the power semiconductor modules have shrunk the power switching part of the converter, but the bulk of the subsystem volume still comprises the associated control, sensing, electromagnetic power passives (inductors, transformers, capacitors) and interconnects, which limit the scaling. Concurrently, next generation and emerging applications are demanding substantial leaps in power conversion performance.
[0006] Moving from MOSFET to High-electron-mobility transistor (HEMT) [also known as heterostructure FET (HFET) or modulation-doped FET (MODFET)] technology has a potential to reduce switching time; however its potential is limited due to system parasitic elements. Orders of magnitude increase in switching speed, which is possible with new device technologies, requires substantial reduction in structural capacitances and inductances associated with these devices/systems as also introduction of super-passives and novel packaging techniques.
[0007] To meet the new requirements, new materials and transistor structures are needed to fill the gap. Keeping a proactive view on such a need, gallium nitride (GaN) based power device technology was invented, which promises to deliver better performance than the existing silicon devices. The GaN technology is expected to enable dramatic reductions in energy consumption in the end-application coupled with reduction in size, weight, and cost and increase in power density. However, this can’t be achieved using the existing technologies or methods that follow following approaches:
Board level integration: comprises power switching devices, the associated control, sensing, electromagnetic power passives (inductors, transformers, capacitors) and interconnects over a multi-layer board.
PSiP: comprises separate chips (switches drivers, controller) within the same package with external inductor/passives
PwrSoC: comprises a single Si chip (containing switches, drivers and controller) with integrated inductor/passives
Power IC: comprises a single Si chip (containing switches, drivers and controller) with external inductor/passives
[0008] These limitations of the conventional technology can be overcome either by introducing new materials and better device architectures for power device technology or by 3D/vertical integration of micro – and nano – technology. There is therefore a need in the art to provide method of integrating a power electronic system inside a 3D IC that allows controller, processors, power switches/transistors, inductive and capacitive passive devices within the same chip with thermal and EMI shield. Such a device can significantly increase power density without sacrificing the performance targets and can significantly reduce cost, size and weight.
[0009] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
[0010] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0011] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0012] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0013] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
[0014] An object of the present disclosure is to overcome limitations of the conventional technology in the field of power electronics.
[0015] An object of the present disclosure is to provide a method of integrating a power electronic system inside a 3D IC.
[0016] An object of the present disclosure is to provide a power electronic device that incorporates controller, processors, power switches/transistors, inductive and capacitive passive devices within the same chip with thermal and EMI shield.
[0017] An object of the present disclosure is to provide a power electronic device with significantly increased power density, without sacrificing the performance targets.
[0018] An object of the present disclosure is to provide a power electronic device with significantly reduced cost, size and weight.
[0019] An object of the present disclosure is to provide a power electronic device that integrates HEMT on Si with MoS2 based controller chip and super inductors/capacitors.
[0020] An object of the present disclosure is to provide a power electronic device that uses MoS2 grown over HEMT-on-Si die
[0021] An object of the present disclosure is to provide a power electronic device that uses Graphene sheet based super capacitor and CNT based super inductors.
[0022] An object of the present disclosure is to provide a power electronic device that uses newly proposed heat transporters and EMI shields.
[0023] An object of the present disclosure is to provide a method for integrating above proposed devices within a 3D chip.
[0024] An object of the present disclosure is to provide a method for manufacturing the proposed 3D power IC in a single process line.

SUMMARY
[0025] Aspects of present disclosure relate to a 3 D power system on a chip that incorporates power devices with µ-Nano device technology. In an aspect such a device can incorporate controller, processors, power switches/transistors, inductive and capacitive passive devices within the same chip with thermal and EMI shield. Further it can significantly increase power density without sacrificing the performance targets and can significantly reduce cost, size and weight.
[0026] In an embodiment, the disclosure provides an AlGaN/GaN HEMT based power device over a Si die with additional Si circuitry on the same Si die. In an aspect the disclosed architecture can significantly improve the switching speed or power amplification capability without adding to cost and weight. In another aspect, the size of inductive and capacitive passives can reduce dramatically on account of increase in the switching speed. GaN devices can also be integrated within a Si chip,
[0027] In an embodiment, the disclosed 3 D chip can incorporate a controller chip that is developed using monolayer Molybdenum Di-sulphide (MoS2) or similar 2D material stack, which can offer low power solution without any weight increase and thermal constraints. This is an advantageous solution when Si CMOS and HEMT can’t be integrated over the same die. As MoS2 offers good mobility, has a band gap and can be grown over an appropriate dielectric, MoS2 based controller chip can be realized over the GaN-on-Si die – passivated by an appropriate dielectric.
[0028] In an embodiment, the disclosed 3 D chip can incorporate metallic carbon nanotubes (CNTs) based super inductors/transformers and graphene/CNT (e.g. graphene sheet, activated graphene, quantum Nano cluster of metal oxides, graphite oxide, SWNT composite electrodes, etc) based super capacitors that can be integrated within the 3D chip. In an aspect CNT based inductors can result in low eddy current, low proximity effect loss, and low AC resistance, which is good for high switching circuits. Further, it has 50× greater performances than copper, offers higher inductance, Q-factor, and sustains a larger amount of heat than conventional inductors without breaking down. In another aspect, graphene/CNT based super capacitors have significantly higher storage (per volume) capability, that can allow integration of big capacitors within a smaller volume on a 3D chip. Introduction of CNTs based super inductors/transformers and graphene/CNT based super capacitors can result in significant improvement in system performance and reduction in size, weight and cost beyond the significant reduction in their sizes on account of high switching power devices.
[0029] In an embodiment, the individual sub-components i.e. HEMT, controller, super capacitors and super inductors can be fabricated at different levels in the chip, electrically isolated through interlayer dielectrics, thermally isolated using a heat transporter and magnetically isolated through a EMI shield. The fabricated chip incorporating all the sub-components can be integrated inside a thermally conducting package.
[0030] In an embodiment the disclosed 3 D chip can be configured to meet different requirements such as but not limited to a high power density power converter, a high power density power inverter, a high power RF trans-receiver or a RF power amplifier.
[0031] In an embodiment, the disclosure provides a method of depositing a AlGaN/GaN stack over a Si substrate for fabricating an HEMT such that the same Si substrate can be used for integrating additional Si circuitry configured to meet other functional requirement of the device such as controller. The disclosed method provides for growing of a AlGaN/GaN stack within a deep trench configured on the Si substrate with a transition layer and side wall spacers. The disclosed method leaves balance surface of the Si substrate for configuring additional Si circuitry.
[0032] In an embodiment, the disclosure provides a method of fabricating the disclosed 3 D chip wherein the method can comprise one or more steps in different combinations, the steps being forming deep trench over an Si substrate, growing AlGaN/GaN stack within the deep trench after side wall formation; fabricating, on the AlGaN/GaN stack, one or more GaN HEMT, diode and Si device and their interconnection, encapsulation and contact pad deposition; growing large area MoS2; fabricating, over MoS2, a mixed signal IC and its interconnection, encapsulation and contact pad deposition; fabricating CNT inductors with contact pads and fabricating graphene super conductors with contact pads.
[0033] In an embodiment, the method can further comprise steps of depositing one or more Inter Layer Dielectric (ILD) layers, forming one or more trenches for CNT vias, growing CNT vias, depositing contact pads, growing one or more large area graphene for lateral heat transporters & EMI shields and bonding and packaging the chip. In an aspect these steps and their sequence can depend on requirement and layout of the specific chip.
[0034] In an embodiment, the disclosed 3 D chip can be produced following the disclosed method on a single process line. In an alternate embodiment, it can be done on more than one process line also.
[0035] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components

BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0037] FIG. 1 illustrates an exemplary block diagram indicating extent of application of power electronics in in a typical modern mobile phone.
[0038] FIG. 2 illustrates an exemplary circuit diagram of a typical power converter and a RF power amplifier as known in the art.
[0039] FIG. 3 illustrates an exemplary schematic diagram indicating proposed miniaturization of power electronics products by 3D integration of micro and nano – technology in accordance with embodiments of the present disclosure.
[0040] FIG. 4 illustrates an exemplary schematic diagram indicating AlGaN/GaN stack within a deep trench in Si substrate in accordance with embodiments of the present disclosure.
[0041] FIG. 5 illustrates an exemplary process flow diagram for method of integrating AlGaN/GaN over a Si substrate for fabricating an HEMT in accordance with embodiments of the present disclosure.
[0042] FIG. 6 illustrates an exemplary schematic diagram indicating various electronic components fabricated over the AlGaN/GaN stack and Si substrate in accordance with embodiments of the present disclosure.
[0043] FIG. 7 and FIG. 7A illustrate an exemplary process flow diagram for method of fabricating a 3 D chip integrating µ-Nano devices in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION
[0044] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0045] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0046] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0047] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0048] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0049] Embodiments of the present disclosure relate to a 3 D chip that can incorporate power devices with µ-Nano device technology. In an aspect such a chip can incorporate controller, processors, power switches/transistors, inductive and capacitive passive devices within the same chip with thermal and EMI shield. Further it can significantly increase power density without sacrificing the performance targets and can significantly reduce cost, size and weight as compared to conventional technologies.
[0050] FIG. 2 illustrates exemplary circuit diagrams 100 and 150 of a typical power converter and a RF power amplifier respectively as known in the art. It is evident from the diagram 100 that such systems consist of controller chips 202, power switch/transistors 204, diodes 206 and passives like inductor 210, capacitors 208 and loads 212. A RF power amplifier illustrated in 150 can likewise comprise of similar electronic components. A single chip that functions as a complete device should therefore offer these individual components, which can be fabricated in-line. Unfortunately, convention integration techniques like system-on-chip (SoC: chip with Si power devices, Cu inductors and BEOL capacitors) and system-in-package (SiP: die from different technologies integrated inside single package) have their own limitations and can’t be exploited beyond a point. For example, SoC is limited in terms of what can be offered in a given technology node (limited voltage limits, limited size inductors and conventional capacitors). Moreover, SiP is limited in terms of technology offering, thermal issues and package parasitic elements. Further no SoC or SiP is available or reported, which is based on HEMT technology.
[0051] To meet the requirements of futuristic light weight power applications, new materials, technology, transistor structures, super passives and 3D integration methods are required to fill this gap. The present disclosure provides a new scheme for building miniaturized power electronic products.
[0052] In an embodiment, the disclosure provides an AlGaN/GaN HEMT based power device over a Si die with additional Si circuitry on the same Si die. In an aspect the disclosed architecture can significantly improve the switching speed or power amplification capability without adding to cost and weight. In another aspect, the size of inductive and capacitive passives can reduce dramatically on account of increase in the switching speed. GaN devices can also be integrated within a Si chip,
[0053] In an embodiment, the disclosed 3 D chip can incorporate a controller chip that is developed using monolayer Molybdenum Di-sulphide (MoS2) or similar 2D material stack, which can offer low power solution without any weight increase and thermal constraints. This is an advantageous solution when Si CMOS and HEMT can’t be integrated over the same die As MoS2 offers good mobility, has a band gap and can be grown over an appropriate dielectric, MoS2 based controller chip can be realized over the GaN-on-Si die – passivated by an appropriate dielectric.
[0054] In an embodiment, the disclosed 3 D chip can incorporate metallic carbon nanotubes (CNTs) based super inductors/transformers and graphene/CNT (e.g. graphene sheet, activated graphene, quantum Nano cluster of metal oxides, graphite oxide, SWNT composite electrodes, etc) based super capacitors that can be integrated within the 3D chip. In an aspect CNT based inductors can result in low eddy current, low proximity effect loss, and low AC resistance, which is good for high switching circuits. Further, it has more than 50× greater performances than copper, offers higher inductance, Q-factor, and sustains a larger amount of heat than conventional inductors without breaking down. In another aspect, graphene/CNT based super capacitors have significantly higher storage (per volume) capability, that can allow integration of big capacitors within a smaller volume on a 3D chip. Introduction of CNTs based super inductors/transformers and graphene/CNT based super capacitors can result in significant improvement in system performance and reduction in size, weight and cost beyond the significant reduction in their sizes on account of high switching power devices.
[0055] In an embodiment, the individual sub-components i.e. HEMT, controller, super capacitors and super inductors can be fabricated at different levels in the chip, electrically isolated through interlayer dielectrics, thermally isolated using a heat transporter and magnetically isolated through a EMI shield. The fabricated chip incorporating all the sub-components can be integrated inside a thermally conducting package.
[0056] In an embodiment the disclosed 3 D chip can be configured to meet different requirements such as but not limited to a high power density power converter, a high power density power inverter, a high power RF trans-receiver or a RF power amplifier.
[0057] In an embodiment, the disclosure provides a method of depositing a AlGaN/GaN stack over a Si substrate for fabricating an HEMT such that the same Si substrate can be used for integrating additional Si circuitry configured to meet other functional requirement of the device such as controller. The disclosed method provides for growing of a AlGaN/GaN stack within a deep trench configured on the Si substrate with a transition layer and side wall spacers. The disclosed method leaves balance surface of the Si substrate for configuring additional Si circuitry.
[0058] In an embodiment, the disclosure provides a method of fabricating the disclosed 3 D chip wherein the method can comprise one or more steps in different combinations, the steps being growing a AlGaN/GaN stack on a Si substrate; fabricating, on the AlGaN/GaN stack, one or more GaN HEMT, diode and Si devices and their interconnection, encapsulation and contact pad deposition; growing large area MoS2; fabricating, over MoS2, a mixed signal IC and its interconnection, encapsulation and contact pad deposition; fabricating CNT inductors with contact pads and fabricating graphene super conductors with contact pads.
[0059] In an embodiment, the method can further comprise steps of depositing one or more Inter Layer Dielectric (ILD) layers, forming one or more trenches for CNT vias, growing CNT vias, depositing contact pads, growing one or more large area graphene for lateral heat transporters & EMI shields and bonding and packaging the chip. In an aspect these steps and their sequence can depend on requirement and layout of the specific chip.
[0060] In an embodiment, the disclosed 3 D chip can be produced following the disclosed method on a single process line. In an alternate embodiment, it can be done on more than one process line also.
[0061] FIG. 3 illustrates an exemplary schematic diagram 300 indicating proposed miniaturization of power electronics products by 3D integration of micro and nano – technology devices in accordance with embodiments of the present disclosure. In an embodiment the 3D integration of micro and nano – technology devices within a single chip can be through multiple levels wherein there can be a level referred to as level-1 302 hereinafter that can incorporate Gallium nitride (GaN) based High Electron Mobility Transistors (HEMT) and diodes disposed over Si, SiC or Al2O3 substrate. There can be another level referred to as level-2 304, incorporating Molybdenum disulfide (MoS2) based mixed signal IC that can function as controller. Yet another level referred to as level-3306 can incorporate Super Inductors and/or transformers that can be designed using metallic Carbon Nanotubes. There can be yet another level referred to as level-4308 that can incorporate Super capacitors that are designed using Graphene sheets.
[0062] In an embodiment, it is possible to incorporate devices of level-2 304 to level- 4 308 in a single common level. Further level-2 304 can be distributed within more than one integrated circuit.
[0063] In an embodiment, the level-1 302 can consist of any other Group III-Nitride based HEMT instead of GaN based HEMT and Si/SiGe/SiC transistors and diodes disposed over Si, SiC or Al2O3 substrate.
[0064] In an embodiment, the Level-2 304 can use any 2-dimentional materials such as but not limited to WS2, WSe2 wherein stack of 2-dimentional material or Si/SiGe can be produced using metal induced crystallization method.
[0065] In an embodiment, the Level-3 306 can use any conventional and non-convention metallic, high conducting and super conducting materials.
[0066] In an embodiment, the Level 4 can use any non-conventional or conventional dielectric materials and graphene sheet, activated graphene, quantum nanocluster of metal oxides, graphite oxide or SWNT composite electrodes etc. offering high storage density.
[0067] In an embodiment, the disclosed multiple levels can be stacked over each other and connectivity between different levels can be provided by means of vias310 fabricated using metallic carbon nanotubes and contact pads 312.
[0068] In an embodiment, the Interconnect vias 310 can be fabricated using Through-Silicon-Via (TSV), non-convention metallic materials like metallic Carbon Nanotubes, graphene or similar high conducting / super conducting materials
[0069] In an embodiment, each of the level can be electrically isolated from other by providing an interlayer dielectric layer (IDL) 314 that can be of a thermally conducting material.
[0070] In an embodiment, the architecture can further incorporate one or more intermediate layers 316that incorporate lateral heat transporters and vertical EMI shield. The lateral heat transporters and vertical EMI shield can consist of metal or graphene or stack of metal such as copper and graphene. The one or more intermediate layers can be sandwiched between interlayer dielectric layers which being thermally conducting can permit free flow of heat.
[0071] In an embodiment, the architecture can further incorporate vertical heat transporter and lateral EMI shield 318. The vertical heat transporter and lateral EMI shield 318 can consist of metal or graphene or CNT or stack of metal such as Cu – Graphene – metal or stack of metal such as Ni – CNT – metal. In an aspect the vertical heat transporter and lateral EMI shield 318 and can be disposed anywhere on the chip.
[0072] In an embodiment, the complete structure can be encapsulated inside a single thermal conducting package 320 to make a single chip.
[0073] In an embodiment, a 3 D chip can be configured using above described levels in any combination and order so as to configure different devices to meet different requirements such as but not limited to a high power density power converter, a high power density power inverter, a high power RF trans-receiver or a RF power amplifier.
[0074] In an embodiment, during operation of the disclosed 3D chip, operating temperature of the level 4 is less than that of the level 3, operating temperature of the level 3 is less than that of the level 2 and operating temperature of the level 2 is less than that of the level 1.
[0075] Referring now to FIG. 4 and FIG. 5 wherein method of integrating AlGaN/GaN over a Si substrate for fabricating an HEMTis disclosed. As illustrated in view 400 of FIG. 4 and flow diagram 500 of FIG. 5, the method can incorporate steps such as step 502 -forming a deep trench 402 over Si substrate 404, step 504 - depositing conformal dielectric layer 406 (intermediate layer), step 506 - anisotropic etching for sidewall spacer 408 formation, step 508 - blocking surface of Si substrate 404 except the one which is inside the trench 402, step 510 -growing AlGaN/GaN stack over the intermediate layer 406 within the trench 402, step 512 - filling the trench 402 using a dielectric, and step 514 - carrying out chemical/mechanical polishing / planarization of the surface to prepare it for fabricating HEMT. The Si substrate 404 can now be used for AlGaN/GaN HEMT based power device with additional Si circuitry on the same Si wafer to function as controller or to meet any other functional requirement of the device.
[0076] In an embodiment, the Si substrate 404 over which the AlGaN/GaN stack is grown within the trench 402 can have an orientation <111> or <110> or <100>.
[0077] FIG. 6 illustrates an exemplary schematic diagram 600 indicating various electronic components fabricated over the AlGaN/GaN stack and Si substrate in accordance with embodiments of the present disclosure. Shown therein is a HEMT 602 fabricated over the AlGaN/GaN stack 410. Additionally there can be one or more diodes 604 fabricated over the same AlGaN/GaN stack 410. These together can constitute aAlGaN/GaN HEMT based power device. The remaining surface of the Si substrate 404 can be used for fabricating additional Si circuitry constituting components such as but not limited to NMOS 606, PMOS 608, LDMOS 610.
[0078] FIG. 7 and FIG. 7A illustrate an exemplary process flow diagram for method of fabricating a 3 D chip integrating µ-Nano devices in accordance with embodiments of the present disclosure. The method of fabricating a 3 D chip integrating µ-Nano devices can comprise one or more steps in different combinations wherein step 702 can be growing a AlGaN/GaN stack over a Si substrate. The AlGaN/GaN stack can be grown following method outlined in flow diagram 500. Step 704 can be fabricating, on the AlGaN/GaN stack, one or more GaN HEMT, diode and Si device and their interconnection, encapsulation and contact pad deposition. This can form level-1 of the disclosed 3D chip. Step 706 can be growing large area MoS2. Step 708 can be fabricating, over MoS2, a mixed signal IC and its interconnection, encapsulation and contact pad deposition. This can form level-2 of the disclosed 3 D chip. Step 710 can befabricating CNT inductors with contact pads. This can form level-3 of the disclosed 3 D chip. Step 712 can be fabricating graphene super conductors with contact pads and this can form level-4 of the disclosed 3 D chip. Step 714 can be bonding and packaging the 3 D chip.
[0079] In an embodiment, the method can further comprise steps 752, 756 and 762 of depositing one or more Inter Layer Dielectric (ILD) layers step754 growing one or more large area graphene for lateral heat transporters & EMI shields, step 758 forming one or more trenches for CNT vias and step 760 growing CNT vias, depositing contact pads. In an aspect these steps and their sequence can depend on requirement and layout of the specific chip.
[0080] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0081] The present disclosure overcomes limitations of the conventional technology in the field of power electronics.
[0082] The present disclosure provides a method of integrating a power electronic system inside a 3D IC.
[0083] The present disclosure provides a power electronic device that incorporates controller, processors, power switches/transistors, inductive and capacitive passive devices within the same chip with thermal and EMI shield.
[0084] The present disclosure provides a power electronic device with significantly increased power density, without sacrificing the performance targets.
[0085] The present disclosure provides a power electronic device with significantly reduced cost, size and weight.
[0086] The present disclosure provides a power electronic device that integrates HEMT on Si with MoS2 based controller chip and super inductors/capacitors.
[0087] The present disclosure provides a power electronic device that uses HEMT grown over MoS2 onSi die
[0088] The present disclosure provides a power electronic device that uses Graphene sheet based super capacitor and CNT based super inductors.
[0089] The present disclosure provides a power electronic device that uses newly proposed heat transporters and EMI shields.
[0090] The present disclosure provides a method for integrating above proposed devices within a 3D chip.
[0091] The present disclosure provides a method for manufacturing the proposed 3D power IC in a single process line.