DESC:TECHNICAL FIELD
[0001] The present invention relates to a beamformer. The invention more particularly relates to a multi-channel beam former for the phased array radar systems.
BACKGROUND
[0002] Digital receiver is an integral part of the phased array radar system, high-resolution ADCs are used to convert the analog signal to digital signal and further digital down-conversion are carried out to convert the signal to baseband. The realization of a digital receiver is performed using the state of the art FPGA, the said FPGA has the capability of showing higher performance at higher speeds. The active phased array Radar might consist of several hundreds of receive channels.
[0003] Beamforming, a signal processing technique used for directional signal transmission or reception. This is achieved by combining elements in an antenna array in such a way that, signals at particular angles constructive interference while others experience destructive interference. Beamforming is used for directional signal transmission and reception with the versatility to change both amplitude and phase to help regulate power needs and steer the beam in the intended direction. In high-frequency millimeter wave transmission, large path loss during signal propagation limits the transmission range. To overcome the said limitation, directional antennas with beamforming abilities are used in transmission and reception. Beamforming directs the antenna beams at the transmitter and receiver so that the transmission rate is maximized with minimum loss.
[0004] In analog beamforming, the signal is fed to each antenna element in the array by passing through analog phase shifters where the signal is amplified and directed to the desired receiver. The amplitude or phase variation applied to the analog signal at transmitting end where the signals from different antennas are added before the ADC. At present, analog beamforming is the most cost-effective way to build a beamforming array but it can manage and generate only one signal beam.
[0005] Digital Beam Former, for digital beamforming, is an accurate translation of the analog signal into the digital realm. Matching receivers being a complex calibration process, with each antenna having its own transverse and data converters that generate multiple beams simultaneously form one array.
[0006] US20170262398 titled “Power Efficient Distributed Beam Forming Architecture Using Interconnected Processing Nodes” discloses a digital beam forming apparatus for use in a radar system. The digital beam forming apparatus comprises i) a plurality of multichip modules, each of the multichip modules comprising a plurality of application-specific integrated circuit (ASIC) devices; ii) at least a first serial bus configured to couple a first multichip module to an antenna element; and iii) at least a second serial bus configured to couple the first multichip module to a second multichip module, wherein a first ASIC device on the first multichip module is coupled to a second ASIC device on the first multichip module by means of a first parallel bus. The first and second ASIC devices perform beamforming operations.
[0007] US6701141 B1 titled “Mixed-signal true-time delay digital beamformer” discloses an apparatus for implementing true time delay digital beamformers for forming transmit and/or receive beams in array antennas. The apparatus includes a mixed-signal application-specific integrated circuit (ASIC), which is comprised of an analog-to-digital converter (A/D) as an input circuit, an internal digital delay circuit, and a digital-to-analog converter (D/A) as an output circuit. The internal digital delay circuit provides true-time delays that are selectable based on digital control, whereas the A/D and D/A circuits provide the interface circuits for the analog input and output signals.
[0008] A compact FPGA BEAM Former Architecture (PP463-466) describes digital beamforming based on non-uniform sampling and focusing simultaneously and hence can possess efficient frontend architecture called Pipelined Sampled-Delay Focussing (PSDE). This requires non-uniform sampling using different sampling clocks at each element.
[0009] There are many challenges in realising the hardware for digital beam former application. One of the challenges in the realisation of the hardware for digital beam former is handling of data when electronic systems require increased resolution and higher sampling rate for increased bandwidth.
[0010] The data rate of the ADC affects the digital interface and processing power requirement and the question becomes how to handle the data when electronic systems require increased resolution and higher sampling rate for increased bandwidth.
[0011] Another problem is related to the requirement of a waveform generator at each element. The processors require immense power. Because of the limitation in data bandwidth, there is a practical limit of the number of elements in the array which requires waveform generators at each element.
[0012] Another problem is related to data reliability. The module size increases with an increase in the number of array elements. With more number of array elements and increased hardware complexity, it becomes difficult to integrate data from multiple receiver channels and hence problem of data reliability becomes a question.
[0013] Hence, there is a need for a system and method to overcome the aforesaid limitations.
SUMMARY
[0014] This summary is provided to describe a multi-channel receive beam former system and method thereof. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[0015] For example, various embodiments herein may include one or more systems and methods for the multi-channel receive beam former system with integrated mono-pulse apparatus. In one embodiment, the multi-channel receive beam former comprises a plurality of radio frequency (RF) connectors configured to receive a reflected intermediate frequency (IF) signals from a target which is centred across the said IF. The multi-channel receive beam former is a 128 channel digital receiver and beam former. The system further includes a plurality of analog-to-digital converters (ADC) configured to digitize the received IF signals. The received signals are later digitized using the high-speed ADCs. The system further includes a field-programmable gate array (FPGA) configured to perform the digital down-conversion and beam forming operations on the received ADC digitized signal. A memory unit is interfaced to the FPGA. The memory unit is configured to store volatile weight coefficients for digital beam forming application and digital simulation coefficients for built-in self-test (BIST). The memory unit having a static random access memory (SRAM) module and a board flash module which are used to store the volatile weight coefficients data and the digital simulation coefficients data.
[0016] The system disclosed in the present invention further includes a plurality of multi-gigabit transceiver (MGT) channels configured to transfer the beam-formed data towards a signal processor module, wherein the beam formed data is transferred through a VPX connector.
[0017] In another embodiment, a method comprising receiving reflected intermediate frequency signals from a target by a plurality of a radio frequency (RF) connectors. The method further includes digitizing, by an analog-to-digital converters ADC, the received IF signals. The method further includes performing the digital down-conversion and beam forming operations, by an FPGA, on the received ADC digitized signal. The method further includes transferring, by multi-gigabit transceiver channels, beam-formed data towards a signal processor module through a VPX connector. The method further includes storing, by a memory unit, the volatile weight coefficients, and digital simulation coefficients data. Further, a metal housing encloses the multi-channel receive beam former system.
BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0018] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.
[0019] Fig.1 illustrates a schematic diagram depicting a target and a multi-channel receives beam former system, according to an exemplary embodiment of the present invention.
[0020] Fig.2 illustrates a schematic diagram depicting a block-diagram of multi-channel receive beam former module, according to an embodiment of the present invention.
[0021] Fig.3 illustrates a schematic diagram depicting a functional block diagram of the multi-channel receive beam former modules present in the system, according to an embodiment of the present invention.
[0022] Figs.4A-4B illustrates flow charts relating to the technical implementation of multi-channel receive beam former, according to an exemplary implementation of the present invention.

DETAILED DESCRIPTION
[0023] In the following description, for the purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into several systems.
[0024] The various embodiments of the present invention describe a multi-channel receive beam former system.
[0025] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0026] References in the present invention to “one embodiment” or “an embodiment” mean that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0027] In an embodiment, the present invention discloses a multi-channel receive beam former system. The said system comprises a plurality of radio frequency (RF) connectors, a 128 channel ADCs, a single FPGA processor, a 10/100/1000 Mbs-Ethernet connected to the said FPGA, a memory unit to store volatile weight coefficients for digital beam forming application and digital simulation coefficients for built in self test, a plurality of multi-gigabit transceiver (MGT) channels, and a VPX connector.
[0028] The said RF connectors configured to receive reflected signals from a target which is centred across an intermediate frequency. All the reflected signals as input are received over the said RF connectors and further these received signals are transferred through the 128 channels ADC. The said 128 channel ADC is connected with the said FPGA. The data received from the entire 128 channel ADC is synchronized in the FPGA. Based on controls from radar computer, digital down-conversion and beamforming algorithms are implemented in the FPGA. Further, the plurality of MGT channels transfers the beam formed data from the said FPGA towards a signal processor module through the said VPX connector. The said memory unit interfaced to the FPGA is having an SRAM module and a board flash module.
[0029] In an exemplary embodiment, the present invention discloses the hardware FPGA. The reflected signals i.e. 128 channels data, from multiple antennas, are sent towards the 128 channel ADCs. The said ADCs convert the received 128 analog signals into digital signals. The said ADCs are configured for digital data simulation that generates different known test patterns to make serial to parallel word-formation certain in the FPGA, ensuring the interpretation of even high data rates consistently. Further, these digitized signals are sent to the FPGA. Inside the FPGA, multiple operations are performed by elements present in the said FPGA. The digitized signals when sending to the said FPGA, the 128 channel signals first enter to digital down-conversion (DDC). Further, the digitized signals are transferred to FIR for filtering. The said internal filtering eliminates the undesired spurious at the input but also reduces the resources utilized in the FPGA. Further, the said signals are sent to a digital beam former. Further, the multiple channel data or the processed data are sent to the signal processor in the form of I (In-phase) & Q (Quadrant-Phase) through the VPX connector.
[0030] In another embodiment, the present invention discloses the multi-channel receive beam former system interfacing with other sub-system in a radar. The multi-channel receive beam former system are connected with four exciter receiver i.e. exciter receiver 1, exciter receiver 2, exciter receiver 3, and exciter receiver 4. The system is also connected to a power supply, timing signals, and a radar computer. The output from the multi-channel receive beam former system is sent towards the signal processor unit through the VPX connector of the system.
[0031] In an exemplary embodiment of the present invention, multi-wire serial ADC to address higher data is discussed. Applications with higher sampling frequencies demand higher data rates between the FPGA and the ADCs. To address the higher data rates and also limitations of a number of input/output ports in the FPGA, the said multi-wire serial ADC with LVDS logic is used.
[0032] In another embodiment, the plurality of radio frequency (RF) connectors configured to receive the reflected intermediate frequency (IF) signals from the target. The said RF connectors are placed on the module which acts as a critical factor in achieving reduced form-factor of the said system. Channel to channel isolation of greater than 100 dBc is ensured within the said connector. Routing from the said connectors to the said ADC input is length matched which ensures minimal phase difference across all the channels in the system.
[0033] In another embodiment, the present invention discloses a metal housing. The metal casing used in the present invention is to ensure the module's compliance for EMI/EMC, better thermal performance and physical stability for the system. Further, the metal casing used in the present invention is externally maintained at a constant temperature, casing projected on to high power dissipating ICs to regulate the heat. As the thermal management is a critical parameter with a multitude of components in this compact module, metal-core PCB (printed circuit board) with multiple ground layers of higher copper thickness are used in said fabrication. Edge milling is done across the periphery of the PCB which exposes the metal-core to the mechanical housing and helps in transferring the heat from the module. The metal casing is projected on to the high power dissipating ICs to regulate the heat. The system enclosed in the housing is externally maintained at a temperature of less than 25 degrees through conduction which counters all the thermal related issues arising due to the high-power radiating antenna elements placed adjacent to the system.
[0034] In an exemplary implementation, the claimed subject matter of the present invention describes the compact scalable hardware architecture of a multi-channel receive beam former with integrated mono-pulse architecture to perform digital beam forming for active phased array radar application. In the digital beam forming, the said phased array antenna is not required to rotate. Instead of rotating the phased array antenna, the beam itself is rotated by different elements of the multichannel-receive beam former system to find out the exact location of the target.
[0035] In an exemplary implementation, the present invention discloses a method to find the exact location of the target using the multi-channel receive beam former system. The multichannel receive beam former system receives the 128 channels data (IF signals) from the antennas. The said received IF signals which are reflected from the target are converted to the baseband signals. Further, the digital beam forming is performed on the said baseband signals which are later sent to the signal processor module for further processing. A plurality of giga-bit transceiver lanes is used to send the beam formed data to the signal processor and to support high-speed data rates. A quadrant approach is implemented in the system enables the feature of mono-pulse extraction in the radar. The quadrant approach implemented in the system provides received beams which partially overlap with each other quadrants to define the mono-pulse areas and processes input signals produced in each of the mono-pulse areas to obtain the angular direction of each target correctly.
[0036] The method includes receiving, by the plurality of radio frequency connectors, the reflected intermediate frequency signals from the said target. All the inputs are received into the system over a plurality of the RF connectors. Further, the method includes digitizing, by the analog-to-digital converters ADC, the received IF signals. Serial data in the ADC is converted to DDR form with reference to the input clock in the said ADC. The digitized data of the samples are serialized in the ADCs. The serial DDR data from the ADC is sent to the FPGA on the LVDS interface. The received signal is decoded back to the ADC sample data in the FPGA. Further, the method includes performing digital down-conversion and beam forming operations, by the field-programmable gate arrays FPGA, on the received ADC digitized signal. The down-converted signal is passed through an FIR filter. The said FIR filter output is fed to both the digital beam former logic as well as the mono-pulse logic. Further, dynamically configurable parameters are received through the Ethernet interface from the radar computer. The method further includes transferring, by the multi-gigabit transceiver channels, beam-formed data towards the signal processor module through the said VPX connector. Multiple hardware is stacked up on to a custom VPX backplane and the number of channels is multiplied. The method further includes storing, by the memory unit, the volatile weight coefficients, and the digital simulation coefficients data. The memory unit comprises the SRAM module and the board flash module. The said SRAM module is configured to store the volatile weight coefficient data and the board flash module is configured to store the digital simulation coefficients data and also to debug radar signal processing algorithms.
[0037] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0038] However, the systems and method are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[0039] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0040] Fig.1 illustrates a schematic diagram (100) depicting a target (102) and a multi-channel receive beam former system (106), according to an exemplary embodiment of the present invention. The block diagram (100) includes the target (102), an exciter receiver (104), a multi-channel receive beam former (106), a mono pulse apparatus (108), a VPX motherboard (110), and a signal processor module (112).
[0041] The input to the said system is the received signals from the said target (102) centred across an intermediate frequency. The exciter receiver (104) receives the signals from multiple antenna elements and down converts to IF signals. The said IF signals are further transferred to the multi-channel receive beam former (106). The processed output signals from the multi-channel receive beam former (106) are transferred through the VPX (110) to the signal processor module (112). The diagram (100) also includes the mono pulse apparatus (108) interfaced with the said multichannel receive beam former (106). The said mono-pulse apparatus (108) is configured to perform a mono-pulse extraction process. Mono-pulse extraction by the said mono-pulse apparatus (108) is a process capable of discriminating between azimuth angles of two or more targets moving side by side close to each other. The quadrant approach implemented in the system provides received beams which partially overlap with each other quadrants to define the mono-pulse areas and processes input signals produced in each of the mono-pulse areas to obtain the angular direction of each target correctly.
[0042] Fig.2 illustrates a schematic diagram depicting a block-diagram (200) of the multi-channel receive beam former module of the present system, according to an embodiment of the present invention.
[0043] The block diagram (200) includes a plurality of RF connector (202), 128 channels ADCs (204), an FPGA (206), 10/100/100 Mb-s tri mode-Ethernet (208), a memory unit (210), 16 pairs-MGT (212), and the VPX connector (110). The plurality of RF connectors (202) is configured for the reception of the IF signals that are coming from the waveform generator/exciter receiver (104). Channel to channel isolation of greater than 100 dBc is ensured within the said connector (202). Routing from the connectors (202) to the ADC (204) input is length matched which ensures minimal phase difference across all the channels in the system. The said multi-channel receive beam former system is split into a plurality of quadrants, with each quadrant receiving the IF signals, through the plurality of the RF connectors (202).
[0044] The tri-mode Ethernet (208) in the present invention is interfaced with the FPGA (206) to dynamically configure parameters, based on radar computer instructions. To achieve dynamic configurability of the parameters in the system, the FPGA (206) module receives packets on-the-fly from the radar computer through the Ethernet link (208) operating at 1000/100/10 Mbps. The packet encapsulates the control commands to be played in next CPI. Health status of various channels is sent as an acknowledgment to the radar computer through the Ethernet (208) interface once in the CPI.
[0045] Further, the received analog signals are passed through the said 128 channels ADCs (204) (but not limited to 128 channels). The said ADCs (128) is placed in a symmetric manner to ensure that the thermal issues, length mismatch and the interferences between the channels are kept minimum. The 128 channel ADCs (204) converts the received 128 analog signals into digital signals. Further, these digitized signals are passed through the said FPGA (206). The 128 channel data or the processed data are sent to the signal processor (112) in the form of I (In-phase) & Q (Quadrant-Phase) through the VPX connector (110).
[0046] In the present invention, a VPX VITA 46 connector (110) is used for transferring the beam formed data to the signal processor (112). An innovative approach has been followed to scale the number of channels by giving a provision of 16 pairs of transceivers connections, with each operating at a speed of 5Gbps to the said VPX connector (110). This approach not only enables the use of multiple similar such modules integrated on a custom backplane but also features higher data rate communication with the said signal processor (112).
[0047] Fig.3 illustrates a schematic diagram depicting a functional block diagram (300) of the multi-channel receive beam former module in the system, according to an embodiment of the present invention. The exciter receiver (1), exciter receiver (2), exciter receiver (3), and exciter receiver (4) receives the signals from the antenna elements and down converts to IF signals correspondingly. Further, these IF signals are transferred towards multi-channel receiver beam former. The multi-channel receive beam former also receives the time signals from other sub-systems in the radar, for the processing. Further, the digital down-conversion algorithms and beam forming algorithms are implemented in FPGA (206) based on the controls from the radar computer. Power, to the multi-channel receive beam former is provided by a power supply.
[0048] Figs.4A-4B illustrates flow charts (400) relating to the technical implementation of the multi-channel receives beam former, according to an exemplary implementation of the present invention.
[0049] Referring now to Fig.4A which illustrates a flow chart (400) of a method for multi-channel beam former, according to an exemplary implementation of the present invention. The flow chart (400) of Fig.4A is explained below.
[0050] At step 402, receiving, by the plurality of a radio frequency (RF) connectors (202), reflected intermediate frequency signals from the target (102);
[0051] At step 404, receiving, by the four different RF connectors, all the reflected intermediate frequency;
[0052] At step 406, digitizing, by the analog-to-digital converters ADC (204), the received IF signals;
[0053] At step 408, digitized data of the samples are serialized in the ADC (208);
[0054] At step 410, serial DDR data from the ADC (204) is sent to the FPGA (206) on the LVDS interface ;
[0055] At step 412, the received signal is decoded back to the ADC sample data in the FPGA (206);
[0056] At step 414, performing digital down-conversion, by the field-programmable gate arrays FPGA (206), on the received ADC digitized signal;
[0057] Now refereeing to Fig. 4B, at step 416, the down-converted signal is passed through an FIR filter;
[0058] At step 418, the FIR filter output is fed to both the digital beam former (106) logic as well as the mono-pulse logic (108);
[0059] At step 420, implementing the digital beam former and mono-pulse algorithms on the received data;
[0060] At step 422, transferring, by the multi-gigabit transceiver channels (212), beam-formed data towards the signal processor module (112) through the VPX connector (110);
[0061] At step 424, transferring, by the multi-gigabit transceiver channels (212), mono-pulse data towards the signal processor module (112) through the VPX connector (110);
[0062] At step 426, storing, by the memory unit (210), the volatile weight coefficients and the digital simulation coefficients data.
[0063] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

List of Reference Numerals:
Target: 102
Exciter Receiver: 104
Multi-Channel Receive Beam Former: 106
Mono Pulse Apparatus: 108
VPX Connector: 110
Signal Processor Module: 112
RF Connector: 202
ADC: 204
FPGA: 206
Ethernet: 208
SRAM: 210-a
Flash Module: 210-b
MGT: 212
VPX Connector: 110

,CLAIMS:

1. A multi-channel receive beam former system comprising:
a plurality of radio frequency (RF ) connectors (202) configured to receive a reflected intermediate frequency (IF) signals from a target (102) ;
a plurality of analog-to-digital converters ADC (204) configured to digitize the received IF signals;
a field-programmable gate arrays FPGA (206) configured to perform digital down-conversion and beam forming operations on the received ADC digitized signal;
a plurality of multi-gigabit transceiver (MGT) channels (212) configured to transfer the beam-formed data towards a signal processor module (112), wherein the beam formed data is transferred through a VPX connector (110);
a memory unit (210) to store volatile weight coefficients for digital beam forming application and digital simulation coefficients for built in self-test (BIST); and
a metal housing to enclose the multi-channel receive beam former system;
wherein the multi-channel receive beam former system split into a plurality of quadrants, with each quadrant receiving the IF signals, through the plurality of radio frequency (RF) connectors (202).
2. The system as claimed in claim 1, wherein the multi-channel receive beam former is a 128 channel digital receiver and beam former.
3. The system as claimed in claim 1, wherein a mono-pulse apparatus (108) is integrated on the system.
4. The system as claimed in claim 3, wherein the mono-pulse apparatus (108) is configured to perform mono-pulse processing with a quadrant approach.
5. The system as claimed in claim 1, wherein the memory unit (210), interfaced to the field-programmable gate arrays FPGA (206) comprises:
an SRAM module (210-a) to store volatile weight coefficients data; and
a board flash module (210-b) to store digital simulation coefficients data.
6. The system as claimed in claim 1, wherein the metal casing configured to provide improved thermal performance and physical stability of the different hardware fitted on the said system.
7. The system as claimed in claim 1, wherein the radio frequency (RF) signals are received from an exciter receiver (104) and beam formed data is transferred to the digital signal processing.
8. The system as claimed in claim 1, wherein a tri mode-ethernet port (208) is interfaced with the field-programmable gate arrays FPGA (206) to dynamically configure parameters, based on a radar computer instruction.
9. A method comprising:
receiving, by a plurality of a radio frequency (RF) connectors (202), reflected intermediate frequency signals from a target (102);
digitizing, by an analog-to-digital converters ADC (204), the received IF signals;
performing digital down-conversion and beam forming operations, by a field-programmable gate arrays FPGA (206), on the received ADC digitized signal;
transferring, by multi-gigabit transceiver channels (212), beam-formed data towards a signal processor module (112) through a VPX connector (110);
storing, by a memory unit (210), the volatile weight coefficients and digital simulation coefficients data; and
enclosing, by a metal housing, the said system.