We claim:
1. A multi-lane transmitting apparatus (100) comprising:
a plurality of lanes (1011, 1012, ……., 101n), wherein each lane of the plurality of lanes
(1011, 1012, ……., 101n) comprises a serializer circuit (102) configured to convert parallel bits to
serial bits;
a clock signal generator (103), configured to generate a first clock signal having a
plurality of phases, wherein the first clock signal is provided to the plurality of lanes (1011,
1012, ……., 101n);
a plurality of deserializer circuits (1041, 1042, ……., 104n), wherein each of the plurality
deserializer circuits (104) is configured between two lanes of the plurality of lanes (1011, 1012,
……., 101n) to convert serial bits to parallel bits; and
a Built-In Self-Test (BIST) circuit (105) configured to test the multi-lane transmitting
apparatus, wherein the BIST circuit (100) comprises:
a plurality of signal generator circuits (2011, 2012, ……., 201n), wherein each of
the plurality of signal generator circuits (201) is configured between two lanes of the
plurality of lanes (1011, 1012, ……., 101n) to generate a signal having bits in a defined
pattern and provide the signal corresponding to each of the plurality of phases of the
first clock signal sequentially to a corresponding two lanes of the plurality of lanes;
a plurality of comparator circuits (2021, 2022, ……., 202n), wherein each of the
plurality of comparator circuits (202) is configured between two lanes of the plurality of lanes(1011, 1012, ……., 101n), to compare a pattern of bits of an output signal from
each of a corresponding two lanes with the defined pattern, for each of the plurality of
phases of the first clock signal, and an output of each of the plurality of comparator
circuits(202) indicates a matched status or an unmatched status of the pattern of bits of
the output signal;
a plurality of BIST lane circuits (2031, 2032, ……., 203n), wherein each of the
plurality of BIST lane circuits (203) is configured between two lanes of the plurality of
lanes (1011, 1012, ……., 101n), to monitor a status of each of a corresponding two lanes
(1011, 1012, ……., 101n) based on the output of a corresponding comparator circuit;
a BIST central circuit(204) configured to receive a status of the plurality of
lanes(1011, 1012, ……., 101n) from the plurality of BIST lane circuits,(2031, 2032, …….,
203n) determine one or more lanes from the plurality of lanes (1011, 1012, ……., 101n)
and a corresponding phase among the plurality of phases of the first clock signal having the unmatched status, and determine if a number of the one or more lanes is less than a
threshold value; and
a plurality of phase extrapolator circuits(2061, 2062, ……., 206n), wherein each of
the plurality of phase extrapolator circuits(206) is configured between two lanes of the
plurality of lanes(1011, 1012, ……., 101n) to adjust the phase of the first clock signal
provided to the one or more lanes when the number of the one or more lanes is less than
the threshold value, and the phase of the first clock signal provided to the one or more
lanes is adjusted according to a delay calibrated in the one or more lanes.
2. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein the BIST circuit
(105) comprises a port associated with a notification circuit, and
the output of the plurality of comparator circuits (2021, 2022, ……., 202n) is provided to the port for notifying a status of testing of the plurality of lanes (1011, 1012, ……., 101n) via the
notification circuit.
3. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein the clock signal
generator (103) generates the first clock signal having the plurality of phases ranging from 0°
to 360°.
4. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein the plurality of
deserializer circuits (1041, 1042, ……., 104n) are configured to receive inputs from one or more
combinations of lanes from the plurality of lanes (1011, 1012, ……., 101n).
5. The multi-lane transmitting apparatus (100) as claimed in claim 1, further comprises a
plurality of switching circuits (2051, 2052, ……., 205n) configured to connect each lane of the plurality of lanes (1011, 1012, ……., 101n) to a respective deserializer circuit of the plurality of
deserializer circuits.
6. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein each phase
extrapolator circuit (206) among the plurality of phase extrapolator circuits (2061, 2062, …….,
206n) is further configured to receive each phase of the first clock signal from the clock signal
generator (103) and to provide to a respective lane of the plurality of lanes (1011, 1012, …….,
101n). 7. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein the plurality of
signal generator circuits (2011, 2012, ……., 201n) provides the first clock signal having a second
phase of the plurality of phases, when the number of the one or more lanes is greater than or
equal to the threshold value for the first clock signal having a first phase of the plurality of
phases.
8. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein a result of testing
the plurality of lanes (1011, 1012, ……., 101n) indicates failure, when a number of the one or more
lanes with unmatched status is greater than or equal to the threshold value.
9. The multi-lane transmitting apparatus (100) as claimed in claim 1, wherein the multi-lane
transmitting apparatus is further configured to provide each of the plurality of phases of the
first clock signal to a driver circuit (702) in the multi-lane transmitting apparatus (100) and
measure an output of the driver circuit for each of the plurality of phases to monitor
performance of the driver circuit (702). 10. A method for testing a multi-lane transmitting apparatus (100), comprising a plurality of
lanes (1011, 1012, ……., 101n), a clock signal generator (103), and a Built-In Self-Test (BIST)
circuit (105), the method comprising:
generating, by the clock signal generator (103), a first clock signal having a plurality of
phases, wherein the first clock signal is provided to the plurality of lanes (1011, 1012, ……., 101n);
generating, by a plurality of signal generator circuits (2011, 2012, ……., 201n), a signal
having bits in a defined pattern, and providing the signal and each of the plurality of phases of
the first clock signal to the plurality of lanes (1011, 1012, ……., 101n) sequentially;
comparing, by a plurality of comparator circuits (2021, 2022, ……., 202n), a pattern of bits
of an output signal from each lane of the plurality of lanes (1011, 1012, ……., 101n) with the
defined pattern, for each of the plurality of phases of the first clock signal, wherein an output
of each of the plurality of comparator circuits (202) indicates a matched status or an unmatched status of the pattern of bits of the output signal;
monitoring, by a plurality of BIST lane circuits (2031, 2032, ……., 203n), the status of each
of two lanes of the plurality of lanes (1011, 1012, ……., 101n) based on the output of the plurality
of comparator circuits (2021, 2022, ……., 202n), wherein each of the plurality of BIST lane
circuits (203) is configured between two lanes of the plurality of lanes (1011, 1012, ……., 101n); receiving, by a BIST central circuit(204), a status of the plurality of lanes(1011, 1012,
……., 101n) from the plurality of BIST lane circuits,(2031, 2032, ……., 203n) determining one or
more lanes from the plurality of lanes (1011, 1012, ……., 101n) having the unmatched status and
a corresponding phase among the plurality of phases of the first clock signal, and determining
if a number of the one or more lanes is less than a threshold value; and
calibrating, by a respective phase extrapolator circuit among a plurality of phase
extrapolator circuits (2061, 2062, ……., 206n), a delay in the one or more lanes, to adjust a phase
of the first clock signal provided to the one or more lanes when the number of one or more
lanes is less than the threshold value, wherein the phase of the first clock signal provided to the
one or more lanes is adjusted.
11. The method as claimed in claim 10, wherein the output of the plurality of comparator
circuits (2021, 2022, ……., 202n) is provided to a port associated with a notification circuit in the
BIST circuit (105), for notifying via the notification circuit. 12. The method as claimed in claim 10, wherein the plurality of phases range from 0° to 360°.
13. The method as claimed in claim 10, wherein a plurality of deserializer circuits (1041, 1042,
… 104n) receives inputs from one or more combinations of lanes from the plurality of lanes
(1011, 1012, ……., 101n).
14. The method as claimed in claim 10, wherein each lane of the plurality of lanes (1011, 1012,
……., 101n) is connected to a respective deserializer circuit via a plurality of switching circuits
(2051, 2052, ……., 205n).
15. The method as claimed in claim 10, wherein each of the plurality of phases of the first clock
signal is provided to each of the plurality of lanes (1011, 1012, ……., 101n) by a corresponding
phase extrapolator circuit (206) among the plurality of phase extrapolator circuits (2061, 2062,
……., 206n). 16. The method as claimed in claim 10, wherein the first clock signal having a second phase
of the plurality of phases is provided, when the number of the one or more lanes is greater than
or equal to the threshold value for the first clock signal having a first phase of the plurality of
phases. 17. The method as claimed in claim 10, wherein a result of testing the multi-lane transmitting
apparatus (100) indicates failure, when the number of the one or more lanes with unmatched
status is greater than or equal to the threshold value.
18. The method as claimed in claim 10 further comprises:
providing each of the plurality of phases of the first clock signal to a driver circuit in the multilane transmitting apparatus; and
measuring an output of the driver circuit for each of the plurality of phases to monitor
performance of the driver circuit. 19. A method for testing a multi-lane transmitting apparatus (100) comprising a plurality of
lanes (1011, 1012, ……., 101n) and a Built-In Self-Test (BIST) circuit (105) including a plurality
of BIST lane circuits (2031, 2032, ……., 203n), wherein each of the plurality of BIST lane circuits
(203) is connected between two of the plurality of lanes (1011, 1012, ……., 101n), the method
comprising:
selecting a first phase of a plurality of phases of a first clock signal, and providing the
first phase to the plurality of lanes (1011, 1012, ……., 101n);
performing align detection to determine if each of the plurality of lanes (1011, 1012, …….,
101n) has a matched status or an unmatched status, and receiving a status of the plurality of
lanes (1011, 1012, ……., 101n) from the plurality of BIST lane circuits (2031, 2032, ……., 203n);
determining if a number of the plurality of lanes (1011, 1012, ……., 101n) having the
unmatched status is less than a threshold value, wherein each of the plurality of lanes (1011,
1012, ……., 101n) having the unmatched status is a fail lane;
performing delay calibration for the fail lanes if a number of the fail lanes is less than
the threshold value;
performing a BIST if the delay calibration for the fail lanes passes; and
selecting a next phase of the plurality of phases, providing the next phase to the plurality
of lanes (1011, 1012, ……., 101n), and performing the align detection, the delay calibration if the
number of the fail lanes is less than the threshold value, and the BIST if the delay calibration
passes. 20. The method of claim 19, wherein the align detection, the delay calibration, and the BIST
are performed until all of the plurality of phases are selected or the BIST is passed for all of
the plurality of lanes (1011, 1012, ……., 101n).