TITLE OF THE INVENTION Multilayer Substrate
BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION
The present invention relates to improvement of a multilayer substrate in which high current patterns are disposed in a high current control ECU making e.g., motor control of, for example, a four-wheel automobile EPS (electric power steering) or a transmission.
2. DESCRIPTION OF THE RELATED ART
Conventionally, many structures of a multilayer substrate intended to reduce noise produced by a high-frequency current or to reduce an electromagnetic induction have been proposed (refer to the Japanese Patent Publication (unexamined) No. 307203/2000 and the Japanese Patent Publication (unexamined) No. 53449/2001. In a high current control ECU making the motor control of, for example, a four-wheel automobile EPS or a transmission, however, practical use of a multilayer substrate with a large capacity of electronic parts (transistors and the like) comes to be desired.
That is, this type of printed circuit board is required to address s the needs of 30 to 60 A current and not less than 30 V of voltage. However, the thickness of a conductive layer
is typically 35 µm or 70 µm in thickness in respect of etching of a copper foil thereof, and the width of a conductive layer is eventually limited owing to restrictions to an effective area and a heat capacity of substrates, resulting in restrictions to a current carrying capacity of electronic parts to be mounted

on the substrate.
Accordingly, the following technique is proposed (refer to the Japanese Patent Publication (examined) No. 54874/1995 and the Japanese Patent Publication (unexamined) No. 251063/2001). In this technique, conductive layers of a standard thickness on which predetermined patterns are formed are laminated on both sides of an insulating layer therethrough, and the above-mentioned conductive layers are connected in parallel via through holes to provide connection with a high current control element, whereby a printed circuit board of a large current carrying capacity is obtained.
This printed board, however, is constructed such that the conductive layers of the same circuit pattern are laminated via an insulating layer, and thus these patterns are seen to overlap in one pattern when the substrate is viewed in one direction (for example, viewed from the surface) . Due to the same shapes in a vertical direction, an advantage is recognized in that the radiation of noise in the case where current is carried is suppressed, and the thickness of an insulating layer of these patterns can be smaller. Nevertheless, since various electronic parts are mounted on the surface layer, a pattern shape of this surface conductive layer is still restricted. In contrast, although an internal layer is originally free of such restrictions, and patterns therein can be designed comparatively without restraint, the pattern shape of the internal layer has to be the same as that of the surface layer. Consequently, there is no flexibility in design of a current carrying capacity of a substrate, and restrictions still remain to achieve a larger current carrying capacity.
That is, due to that there is resided an internal layer

of the same pattern as of a surface conductive layer, a larger capacity is obtained to a certain level. However, when higher current electronic parts are mounted on the surface, to avoid destruction of parts or burning of a substrate owing to heat generation from the parts, it will be designed such that high current patterns or high current parts are disposed on metal substrates having higher heat dissipation characteristics, or extra heat sink of a large capacity is located- Thus, as a matter of fact, downsizing of substrates has not yet been achieved. In addition, it is necessary to mount a control signal circuit on a standard electronic control substrate made of e.g., glass epoxy material in addition to a metal substrate on which the above-mentioned high current parts are mounted.
According to such techniques, however, heat dissipation parts such as metal substrates and heat sinks require costs, and additionally a further problem exists in complicated and large-sized electronic housing structure.
SUMMARY OF THE INVENTION
The present invention has been made to solve problems as described above, and, in a multilayer substrate including high current patterns and high current parts, has an object to carry out more improved surface mount technology of high current electronic parts, and thus to achieve downsizing of substrates and cost reduction.
The present invention, in a multilayer substrate in which an internal conductive layer and a surface conductive layer are laminated with each other via an insulating layer, is characterized in that at least one internal conductive layer and surface conductive layer are disposed in parallel to from

a high current pattern; and that there are formed a via hole providing connection between mentioned internal conducive layer and surface conductive layer before and after (in the vicinity of)places where mentioned surface conductive layer is narrow on the way of mentioned high current pattern.
Due to that high current patterns of a plurality of conductive layers inclusive of internal layers are disposed in parallel, the cross section of high current path is ensured. In addition, even in the case where a pattern layout space cannot be obtained with surface mount parts, and thus patterns on the surface layer come narrower, a tolerated capacity of patterns is ensured through via holes. As a result, minimization of the area of a high current circuit that is downsizing of a substrate is achieved.
Furthermore, it comes to be possible that the above-mentioned high current patterns are disposed on a standard electronic control substrate made of e.g., glass epoxy material, thus enabling to reduce costs of substrates.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view of a multilayer substrate
according to a first preferred embodiment of the present
invention.
Fig. 2 is a cross sectional view taken along a line II-
II in Fig. 1.
Fig. 3 is a schematic plan view of a multilayer substrate

according to a second embodiment of the invention.
Fig. 4 is an explanatory view showing an example of a motor drive circuit to be a target of the invention.
Fig. 5 shows a multilayer substrate example according to a third embodiment of the invention.
Fig. 6 shows a multilayer substrate example according to a fourth embodiment of the invention.
Fig. 7 shows a multilayer substrate example according to a fifth embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1.
Hereinafter, a preferred embodiment according to the present invention is described referring to the drawings. Fig. 1 is a schematic plan view of a multilayer substrate according to a first embodiment of the invention. Fig. 2 is a cross
sectional view taken along a line II - II .
Although Fig. 1 shows only a part of a substrate 1, on the surface thereof, there are disposed high current parts such as transistors 3 and 4 and control circuit parts such as capacitors 5 and 6; and there are provided a surface conductive layer 7 forming a high current pattern through spaces therebetween. As can be seen from Fig. 2, the substrate 1 is in a multilayer substrate construction including an internal conductive layer 8 via insulating layers 9. The above-mentioned conductive layer 8, as illustrated with dotted lines in Fig.l, is formed in a shape different from that of the above-mentioned surface conductive layer 7.
The above-mentioned surface conductive layer and internal conductive layer 8 are constructed to connect in parallel via

a connector pin 10 with a connector acting as a part for introducing external signals. Furthermore, a plurality of via holes 11 is made in places of the above-mentioned multilayer substrate, and for example, the electrical connection with the transistor 4 is made through via holes lla.
Moreover, in the high current pattern in the vicinity of the transistor 3 and the capacitors 5 and 6 on the above-mentioned surface conductive layer 7, space for ensuring a width thereof cannot be obtained, and thus there is remained an extremely narrow pattern. The internal conductive layer 8, however, at this portion is shaped to be wide on the contrary. In addition, there are formed via holes lib and lid in these narrow parts, and via holes 11c before and after these narrow parts, whereby more shunt is achieved.In such a manner, a high current flows mainly in the internal conductive layer 8 based on the distribution of resistances, so that the maximum high current can be easily ensured.
Embodiment 2.
Fig. 3 is a schematic plan view of a multilayer substrate according to a second embodiment of this invention, and like reference numerals refer to identical and corresponding parts to those in Fig. 1 in the drawings. In the multilayer substrate according to the second embodiment as shown in Fig. 3, the above-mentioned surface conductive layer 7 and internal conductive layer 8 are disposed in a completely offset manner other than the connector 2 part, the connection part of the transistor 4, and the connection parts 11b, 11c and 11d between the surface layer and the internal layer in the vicinity of the transistor and the capacitors 5 and 6. Whereby, since the overlap

of high current patterns comes to be the minimum, heat dissipation at upper and lower insulating layers of the patterns can be improved.
Accordingly, as shown in the drawing, an advantage exits in that a control signal circuit pattern 20 can be formed on the same substrate as the substrate where high current patterns are located in a way adjacent thereto.
Embodiment 3.
Figs. 4 are explanatory diagrams showing an example of a motor drive circuit to be applied to preferred embodiments described in Embodiments 3 to 5 according to this invention. In the drawings, Fig. 4 (a) is a diagram showing a motor drive circuit example using an H bridge circuit; Fig. 4 (b) is a diagram showing a specific construction example of a transistor FET, being a high current part; and Fig. 4(c) shows an example of the waveform of current flowing through a motor M in the case of using it for transmission control.
In the H bridge circuit arranged like this, a high current path A via motor the M is formed by FETl and FET4 being brought in conduction; on the contrary, a high current path B via the motor M is made by FET2 and FET3 being brought in conduction, whereby a motor current, for example, as shown in Fig. 4(c) flows. In the transmission control, a conducting time period through the motor M is several hundreds ms In the case of EPS control, a time width is approximately several seconds
Figs. 5 shows an example of a multilayer substrate according to a third embodiment of the invention, and shows a part of a pattern example of the circuit of Fig. 4 (a). Fig. 5 (a) shows a schematic plan view thereof, and Fig. 5(b) shows a cross

sectional view thereof taken along a line A-A. In the drawings, FET1 (or FET4) and FET2 (or FET3) form the high current path A and the high current path B in Fig. 4 (a) , and are transistors conducting in time zones different from each other.
In the drawings, Yl and Y2 are high current patterns through the above-mentioned transistor FET2 (or FET3) Yl indicated by solid lines is a surface conductive layer, and Y2 indicated with dotted lines is an internal conductive layer. As shown in Fig. 5(b), the above-mentioned Yl and Y2 are disposed in an offset manner with each other. On the other hand, XI and X2 are high current patterns through the above-mentioned transistor FET1 (or FET4). XI indicated by solid lines is a surface conductive layer, and X2 indicated by dotted lines is an internal conductive layer. Moreover, the above-mentioned XI and X2 are disposed in an offset manner with each other, as well as the above-mentioned XI and Y2 are disposed in a superposed manner in a vertical direction.
In the multilayer substrate according to this third embodiment arranged in such a manner, since the high current patterns XI and X2 forming the same high current path A and the high current patterns Yl and Y2 forming the same high current path B are not superimposed in a vertical direction with each other, heat dissipation characteristics are improved. In addition, since only the high current patterns XI and Y2 through which no current flows spontaneously are constructed to superimpose in a vertical direction, a higher density of pattern arrangement can be achieved without affecting heat dissipation characteristics .
Embodiment 4 .

Figs. 6 show a multilayer substrate example according to a fourth embodiment of the invention, and shows a part of another pattern example of the circuit shown in Fig. 4(a). Fig. 6(a) shows a schematic plan view, and Fig. 6(b) shows a cross sectional view taken along a line A-A. In the drawings, FETl (or FET4) and FET2 (or FET3) are the same as in the third embodiment, being the transistors, which form a high current path A and a high current path B in Fig. 4(a), and which are conducting in time zones different from each other. In the drawings, Yl and Y2 are high current patterns through the above-mentioned transistor FET2 (or FET3). Yl indicated by solid lines is a surface conductive layer, and Y2 indicated by dotted lines is an internal conductive layer.
As shown in Fig. 6(b), the above-mentioned Yl and Y2 are disposed in an offset manner with each other. On the other hand, XI and X2 are high current patterns through the above-mentioned transistor FETl (or FET4). XI indicated by solid lines is a surface conductive layer, and X2 indicated by dotted lines is an internal conductive layer. Moreover, the above-mentioned XI and X2 are disposed in an offset manner with each other, as well as the above-mentioned XI and Y2, and Yl and X2 are disposed in a superposed manner in a vertical direction.
In the multilayer substrate according to this fourth embodiment arranged in such a manner, since the high current patterns XI and X2 forming the same high current path A and the high current patterns Yl and Y2 forming the same high current path B are not superimposed in a vertical direction with each other, heat dissipation characteristics are improved. In addition, since the high current patterns XI and Y2, and Yl and X2 through which no current flows spontaneously are constructed

to superimpose in a vertical direction, a higher density of pattern arrangement can be achieved without affecting heat dissipation characteristics.
Embodiment 5 .
Figs. 7 show a multilayer substrate example according to a fifth embodiment of the invention, and shows a part of another pattern example in which the circuit shown in Fig. 4(a) is constructed with a four-layer substrate. Fig. 7(a) shows a schematic plan view thereof, and Fig. 7(b) shows a cross sectional view thereof taken along a line A-A. In the drawings, FET1 (or FET4) and FET2 (or FET3) are the same as in the third and fourth embodiments, being the transistors, which form a high current path A and a high current path B in Fig. 4 (a) , and which are conducting in time zones different from each other.
In the drawings, Yl and Y2 are high current patterns through the above-mentioned transistor FET2 (or FET3). Yl indicated by solid lines is a surface conductive layer, and Y2 indicted by dotted lines is an internal conductive layer. As shown in Fig. 7 (b), the above-mentioned Yl and Y2 are disposed in an offset manner with each other. On the other hand, XI and X2 are high current patterns through the above-mentioned transistor FET1 (or FET4) XI indicated by solid lines is an internal conductive layer (a third layer) , and X2 indicated by dotted lines is an internal conductive layer (a fourth layer). Moreover, the above-mentioned XI and X2 are also disposed in an offset manner with each other, as well as the above-mentioned XI and Yl, and Y2 and X2 are disposed in a superposed manner in a vertical direction respectively. Furthermore, numerals 9a, 9b, and 9c designate insulating layers.

In the multilayer substrate according to this fifth embodiment arranged as described above, since the high current patterns XI and X2 forming the same high current path A are disposed at the third and fourth layers, and the high current patterns Yl and Y2 forming the high current path B are disposed at the first and second layers, as well as are not superimposed in a vertical direction with each other, heat dissipation characteristics are improved. In addition, since the high current patterns XI and Yl, and Y2 and X2 through which no current flows spontaneously are constructed to superimpose in a vertical direction, heat dissipation characteristics are further improved, as well as a higher density of pattern arrangement
can be achieved.
While the presently preferred embodiments of the present invention have been shown and described. It is to be understood that these disclosures are for the purpose of illustration and that various changes and modifications may be made without departing from the scope of the invention as set forth in the appended claims.

What is claimed is:
1. A multilayer substrate in which an internal conductive
layer and a surface conductive layer are laminated with each
other via an insulating layer: wherein at least one internal
conductive layer and surface conductive layer are connected in
parallel to each other to form a high current pattern; and wherein
there are formed a via hole providing connection between said
internal conducive layer and surface conductive layer before
and after places where said surface conductive layer of said
high current pattern is narrow.
2. The multilayer substrate according to claim 1, wherein
said internal conductive layer and surface conductive layer are
disposed so as not to be overlapped in a vertical direction with
each other except for places where respective layers are
connected through a via hole.
3. The multilayer substrate according to claim 1, wherein
there are provided at least two high, current paths conducting
at time points different from each other; each high current path
is formed of an internal conductive layer and a surface
conductive layer; and the surface conductive layer of either
one of said high current paths is overlapped each other in a
vertical direction with the internal conductive layer of the
other high current path.
4. The multilayer substrate according to claim 1, wherein
there are provided at least two high current paths conducting
at time points different from each other; each high current path
is formed of an internal conductive layer and a surface
conductive layer; and the surface conductive layer of one of
said high current paths is overlapped each other in a vertical
direction with the internal conductive layer of the other high

current path.
5. The multilayer substrate according to claim 4, wherein
internal conductive layers and surface conductive layers
forming said two high current paths are located at respective
different layers.
6. The multilayer substrate according to any one of claims
1 to 5, wherein there are provided on the same substrate a high
current pattern and a control pattern.
Dated this 5 day of December 2006