Claims:CLAIMS
We Claim:
1. A multiple-input multiple-output (MIMO) radio unit (200) comprising:
a plurality of components in a radio frequency (RF) circuit distributed among two types of printed circuit boards (PCBs) (204, 206) to handle a heat issue generated by at least one power amplifier (PA) (268);
a PA section (206) divided into a plurality of PCBs with each PCB comprising a plurality of PAs (268); and
two single pole double throw (SPDT) switches (214) arranged to feedback forward and reflected powers from all transceiver chains to a field programmable gate array (FPGA) (202), wherein the FPGA (202) and at least one memory device perform functions related to the MIMO radio unit (RU) (200), wherein the functions correspond to digital signal processing on a digital board (204).

2. The MIMO radio unit (200) as claimed in claim 1, wherein the PA section (206) is divided into two PCBs (206a and 206b) with each PCB comprising four PAs (268).

3. The MIMO radio unit (200) as claimed in claim 1, wherein the PA section (206) is divided into four PCBs (206a-206d) with each PCB comprising two PAs (268).

4. The MIMO radio unit (200) as claimed in claim 1, wherein the PA section (206) is divided into eight PCBs (206a-206h) with each PCB comprising a single PA (268).

5. The MIMO radio unit (200) as claimed in claim 1, wherein at least one component from the plurality of components having a low power consumption and a low operating temperature is shifted onto the digital board (204) from the PA section (206).

6. The MIMO radio unit (200) as claimed in claim 1, wherein the size of the PA section (206) is reduced by around 7 percent.

7. The MIMO radio unit (200) as claimed in claim 1, wherein the MIMO radio unit (200) comprises a power supply board (208), the digital board (204), and the PA section (206).

8. The MIMO radio unit (200) as claimed in claim 7, wherein at least one of the power supply board (208) and the PA section (206) comprises a protection section that receives a telecom standard -48V supply as a main power source.

9. The MIMO radio unit (200) as claimed in claim 7, wherein three sections are arranged to achieve compact size along with providing high noise isolation and thermal management.

10. The MIMO radio unit (200) as claimed in claim 1, wherein:
the PA section (206) comprising the PCBs are placed parallel to each other on the same axis to form a 1x8 transmitter/receiver port configuration so as to optimize space occupancy; or
the PA section (206) comprising the PCBs are stacked one by one in the vertical direction to form a 2x4 transmitter/receiver port configuration so as to optimize space occupancy.

11. The MIMO radio unit (200) as claimed in claim 1, wherein a first Low Noise Amplifier (LNA) (262) in a receive path (LNA1) in the PA section (206) to keep the losses from the first LNA (262) to a cavity filter (212) in a transmit-receive chain as low as possible as the first LNA (262) governs the noise figure of the MIMO radio unit (200), wherein other two LNAs (256) in the receive path are not included in the PA section (206) that saves the PA section's raising the temperature and prevents performance degradation due to placement of multiple components in a small space.

12. A method for designing radio frequency front end (RFFE) architecture of a multiple-input multiple-output (MIMO) radio unit (200) comprising:
arranging a plurality of switches (214) to feedback forward and reflected powers from all transceiver chains to a field programmable gate array (FPGA) (202), wherein each switch captures signals to achieve a total time spent on a transceiver chain less than one-fourth of the total time of a transmit-receive cycle, so that all the transceiver chains are read during the transmit-receive cycle.

13. The method as claimed in claim 12, wherein the forward and reflected powers from the transceiver chain are multiplexed in time by the plurality of switches (214) such a way that the time required to read the forward and reflected powers on respective ports is a fraction of the total time required by the transmit-receive cycle.

14. The method as claimed in claim 12, wherein other two LNAs (Low Noise Amplifiers) (256) in a receive path are not included in a PA (Power Amplifier) section (206) as many components in a small space raise the PA section’s temperature and degrade the performance of the MIMO radio unit (200).
, Description:TECHNICAL FIELD
[0001] The present disclosure relates to radio units, and more specifically relates to a radio frequency front end (RFFE) section of multiple-input multiple-output (MIMO) radio unit and a method for designing the radio frequency front end (RFFE) section of the MIMO radio unit.

BACKGROUND
[0002] Power amplifiers (PAs) in a transmit chain are main generators of Radio Frequency (RF) power in a radio unit. In the existing radio unit architecture, the PAs generate a lot of heat on a printed circuit board (PCB), thereby raising the temperature of the PCB. As the temperature of the PCB rises, temperature of other RF components in the transmit chain and a receive chain increases that results in degrading the performance of the RF components. Some of the prior art references, related to radio unit, are given below:
[0003] US10771123B2 discloses systems and methods for distributed phased array multiple input multiple output (DPA-MIMO) communications. The system may comprise, a baseband processing unit; a plurality of beamforming (BF) modules each of which comprises at least a beamforming antenna and a transceiver circuit comprising at least a downconverter that down converts a beamformed antenna radio frequency signal to an intermediate frequency signal, and an upconverter that upconverts an intermediate frequency signal to radio frequency and sends to said beamforming antenna for transmission. A plurality of intermediate frequency (IF) radios, each of which comprises a receive chain circuit that includes at least a downconverter that down converts an intermediate frequency signal sent from said BF module to a based band signal conveyed to said baseband processing unit. A transmit chain circuit includes at least an upconverter that upconverts a baseband signal received from said baseband processing unit to an intermediate frequency signal which is conveyed to said beamforming module. A plurality of cables or any type of physical signal transmission medium, each of which connects one of said beamforming modules with one of said intermediate frequency radios.
[0004] WO2018111267A1 discloses a base station that includes a central transceiver unit (CTU) having a plurality of transceiver cores and a substrate. A printed circuit board (PCB) supports the substrate and at least one antenna unit is coupled to the PCB with at least one of a cable and a waveguide. The at least one antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.
[0005] JP6793256B2 relates to a MIMO (Multiple Input Multiple Output) antenna. More specifically, the present invention relates to a lightweight stacked MIMO antenna assembly and calibration with a MIMO antenna operating in a TDD (Time Division Duplex) system. A main object of the present invention is to provide a MIMO antenna having a laminated structure that is compact but lightweight. An assembly method capable of minimizing the cumulative amount of assembly tolerances generated when assembling a plurality of filters and a fastening force required for ensuring the electrical characteristics of the filters. According to the present invention, in a MIMO antenna operating in a TDD (Time Division Duplex) system, TX / RX calibration is executed with one calibration hardware configuration, and calibration is executed in real time during operation. There is another purpose in providing the method.
[0006] US9172145B2 discloses a mixed-signal, multilayer printed wiring board fabricated in a single lamination step. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes several unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits is disposed on an external surface of the PWB, and a heat sink can be disposed over the flip chip components.
[0007] US20210266076A1 relates to wireless communication systems, and more particularly, to a time-period-based antenna adaptation for wireless communication.
[0008] CN213426496U discloses a method for producing a semiconductor device. The utility model relates to the field of communication technology, to cell board is pulled far to radio frequency of 5G basic station. In particular to cell board is pulled far away to radio frequency of 5G basic station, CPRI interface, wide frequency receiving ware are connected respectively in signal processor, dual-channel transmission TX passageway, dual-channel reception RX passageway are connected respectively in wide frequency receiving ware, the external 5G baseband cell module of CPRI interface connection, dual-channel transmission TX passageway, dual-channel reception RX passageway connection external antenna, the PCB board still includes GPS module and ethernet interface, GPS module and ethernet interface are connected respectively in signal processor.
[0009] A non-patent literature entitled “first Commercial Hybrid Massive MIMO System for Sub-6Hz Bands” discloses a massive MIMO referring to the use of many antennas typically at the base station (BS) to serve multiple user equipment (UE) simultaneously to deliver reliable and high data throughput. Two basic architectures have been considered in the literature. First is a fully digital massive MIMO where all the beamforming and precoding is performed digitally in baseband and a radio frequency (RF) chain is required for every antenna element. In the second architecture referred to as hybrid massive MIMO, beamforming and precoding are done in two stages, digital precoding over fewer digital ports followed by analog beamforming across large number of antenna elements. In this paper, we provide a comparison of implementation challenges for each approach. We introduce the High-Definition Active Antenna System (HDAAS), a novel scalable architecture to implement a hybrid Massive MIMO system. This design philosophy is used to build BeamCraft500, which we believe is a first commercial hybrid 3D beamforming system operating at 2 GHz. We also present results from one of the field trials in a live LTE network that validate the stability and performance of the system under real world conditions.
[0010] While the prior arts cover various approaches for reducing the heat generation in the transmit chain and the receive chain, however, there is still scope of improvement. To address the issue of heat generated by the PAs that affects the performance of RF components on the PCB, the PCB is physically segregated into two different sections i.e., HPA (High Power Amplifier) section and SSG (Small Signal Gain) board. However, the boards used for PAs are made of expensive Roger's material and due to the large size of the PCB, the cost of the PCB increases. Hence, the existing approaches are limited by efficiency, cost and heat dissipation. Therefore, there is a need to overcome the above stated disadvantages.

OBJECT OF THE DISCLOSURE
[0011] A principal object of the present disclosure is to provide a radio frequency front end (RFFE) section of multiple-input multiple-output (MIMO) radio unit and a method for designing the radio frequency front end (RFFE) section of the MIMO radio unit.
[0012] Another object of the present disclosure is to arrange a plurality of PCBs (Printed Circuit Boards) to achieve compact size along with providing high noise isolation and thermal management in the MIMO radio unit.
[0013] Another object of the present disclosure is to reduce the total cost of the MIMO radio unit by reducing the size of expensive PCBs of the MIMO radio unit using different materials.
[0014] Another object of the present disclosure is to introduce modularity in a High-Power Amplifier (HPA) section to achieve multiple configurations and easy replacement of the components.

SUMMARY
[0015] Accordingly, the present disclosure provides a MIMO radio unit. The MIMO radio unit comprises a plurality of components in a radio frequency (RF) circuit distributed among two types of printed circuit boards (PCBs) to handle a heat issue generated by at least one power amplifier (PA). The MIMO radio unit further comprises a PA section divided into two PCBs with four PAs each, wherein four PAs are arranged on a first PCB and four PAs are arranged on a second PCB. Alternatively, the PA section is divided into four PCBs with each PCB comprising two PAs. Alternatively, the PA section is divided into eight PCBs with each PCB comprising a single PA.
[0016] Two single pole double throw (SPDT) switches are arranged on the digital board (i.e., SSG Board) to feedback forward and reflected powers from all transceiver chains to a field programmable gate array (FPGA), wherein the FPGA and at least one memory device perform functions related to the MIMO radio unit (RU), wherein the functions correspond to digital signal processing on the digital board.
[0017] In the MIMO radio unit, at least one component from the plurality of components having a low power consumption and a low operating temperature is shifted onto the digital board (i.e., SSG board) from the PA section, wherein the size of the PA section is reduced by around 7 percent. The MIMO radio unit also comprises a power supply board, wherein at least one of the power supply board and the PA section comprises a protection section that receives a telecom standard -48V supply as the main power source. The three sections are arranged to achieve compact size along with providing high noise isolation and thermal management.
[0018] The PA section comprising the two PCBs are placed parallel to each other on the same axis to form a 1x8 transmitter/receiver port configuration to optimize space occupancy; or the PA section comprising the two PCBs are stacked one by one in the vertical direction to form a 2x4 transmitter/receiver port configuration so as to optimize space occupancy. A first Low Noise Amplifier (LNA) in a receive path (LNA1) is kept in the PA section to keep the losses from the first LNA to a cavity filter in a transmit-receive chain as low as possible as the first LNA governs the noise figure of the MIMO radio unit, wherein other two LNAs in the receive path are not included in the PA section that saves the PA section’s’ raising temperature and prevents performance degradation due to placement of multiple components in a small space.
[0019] Accordingly, the present disclosure provides a method for designing the RFFE Architecture of a multiple-input multiple-output (MIMO) radio unit. The method includes arranging a plurality of switches to feedback forward and reflected powers from all transceiver chains to a field programmable gate array (FPGA), wherein each switch captures signals to achieve a total time spent on a transceiver chain less than one-fourth of the total time of a transmit-receive cycle, so that all the transceiver chains are read during the transmit-receive cycle.
[0020] The forward and reflected powers from the transceiver chain are multiplexed in time by the plurality of switches such a way that the time required to read the forward and reflected powers on respective ports is a fraction of the total time required by the transmit-receive cycle.
[0021] These and other aspects herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention herein without departing from the spirit thereof.

BRIEF DESCRIPTION OF FIGURES
[0022] The invention is illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the drawings. The invention herein will be better understood from the following description with reference to the drawings, in which:
[0023] FIG. 1 illustrates a general MIMO system.
[0024] FIG. 2a to FIG. 2d illustrate an RFFE architecture of a MIMO radio unit of the present disclosure.
[0025] FIG. 3a to FIG. 3c illustrate a side view of an HPA (or PA) section according to various embodiments of the present disclosure.
[0026] FIG. 3d illustrates a top view of the HPA (or PA) section.
[0027] FIG. 3e to FIG. 3g illustrate a side view of the HPA section according to various embodiments of the present disclosure.
[0028] FIG. 3h illustrates a top view of another configuration of the HPA section.
[0029] FIG. 4 illustrates a transceiver chain from the RFFE architecture of the MIMO radio unit.
[0030] FIG. 5a illustrates a part of the PA section of the MIMO radio unit including switches for multiplexing feedback signals, as per one of the embodiments of the present disclosure.
[0031] FIG. 5b illustrates a part of the PA section of the MIMO radio unit including switches for multiplexing feedback signals, as per another embodiment of the present disclosure.
[0032] FIG. 5c illustrates a part of the PA section of the MIMO radio unit including switches for multiplexing feedback signals, as per yet another embodiment of the present disclosure.
[0033] FIG. 6 illustrates a timing diagram corresponding to the operation of the switches for multiplexing feedback signals.
[0034] FIG. 7 is a flow chart illustrating a method for designing the RFFE architecture of the MIMO radio unit.

DETAILED DESCRIPTION
[0035] In the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be obvious to a person skilled in the art that the invention may be practiced with or without these specific details. In other instances, well known methods, procedures and components have not been described in detail so as not to unnecessarily obscure aspects of the invention.
[0036] Furthermore, it will be clear that the invention is not limited to these alternatives only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without parting from the scope of the invention.
[0037] The accompanying drawings are used to help easily understand various technical features and it should be understood that the alternatives presented herein are not limited by the accompanying drawings. As such, the present disclosure should be construed to extend to any alterations, equivalents and substitutes in addition to those which are particularly set out in the accompanying drawings. Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally only used to distinguish one element from another.
[0038] FIG. 1 illustrates a general MIMO system (100). The MIMO system (100) includes a transmitter (102) and a receiver (104). The MIMO system (100) multiplies the capacity of a radio link using multiple transmissions and receiving antennas to exploit multipath propagation. In a wireless system, the term "MIMO" referred to the use of multiple antennas at the transmitter (102) and the receiver (104). In modern usage, the "MIMO" specifically refers to a practical technique for sending and receiving more than one data signal simultaneously over the same radio channel by exploiting multipath propagation. The MIMO system (100) has the following diversity mode:
a) Time diversity mode: Using time diversity, a message may be transmitted at different times, e.g., using different timeslots and channel coding.
b) Frequency diversity mode: This form of diversity uses different frequencies. It may be in the form of using different channels or technologies such as spread spectrum/ orthogonal frequency-division multiplexing (OFDM).
c) Space diversity mode: Space diversity used in the broadest sense of the definition is used as the basis for the MIMO. It uses antennas located in different positions to take advantage of the different radio paths that exist in a typical terrestrial environment.
[0039] The MIMO system (100) uses multiple antennas at the transmitter (102) and the receiver (104) to enable a variety of signal paths to carry the data, choosing separate paths for each antenna to enable multiple signal paths to be used. By enabling spatial channelization and diversity, the MIMO system (100) expands the bandwidth available within a given spectral bandwidth and space. There are three MIMO transmission techniques, and each offers an opportunity to optimize the space and bandwidth already selectively and adaptively in use. In the MIMO system (100), Radio frequency (RF) chain circuits play a major role in digital receiver architectures. But, in the current digital receiver architectures, power amplifiers (PAs) in a transmit chain are the main generators of RF power. As disclosed in the background section, the PAs generate a lot of heat on a PCB (Printed Circuit Board), which raises the temperature of the PCB. As the temperature rises on the PCB, the performance of other RF components in the transmit chain and a receive chain degrades. Accordingly, the proposed RFFE Architecture of the MIMO radio unit (200) (explained in FIG. 2a to FIG. 7) improves the performance of the MIMO system (100).
[0040] FIG. 2a to FIG. 2d illustrate an RFFE architecture of the MIMO radio unit (200) of the present disclosure. The MIMO radio unit (200) is preferably an 8 transmitter-8 receiver (8T8R) MIMO base station unit. The MIMO radio unit (200) includes 8 transmission and 8 reception lines. The MIMO radio unit (200) may also be referred to as a radio unit. The MIMO radio unit (200) includes a Field Programmable Gate Array (FPGA) (202), a digital board (204) (i.e., Small Signal Gain (SSG) board), a Power Amplifier (PA) section (206) (i.e., High Power Amplifier (HPA) board), a power supply board (208), a digital side (210) and a plurality of cavity filters (212).
[0041] The digital side (210) of the digital board (204) includes, but is not limited to, a 3X Double Data Rate (DDR) (216), 1X DDR4 (218), small form-factor pluggables (SFPs) (220), a Remote Electrical Tilt (RET) connector (222), an Embedded MultiMediaCard (eMMC) (224), a NOR (226), status LEDs (Light Emitting Diodes) (228), a reset button (230), a reset-in (232), an LMP JTAG (Link Management Protocol Joint Test Action Group) (236), a global position system (GPS) module (238) and a debug connector (234). The 3X DDR (216) and the 1X DDR4 (218) are memory devices operating at a low operating voltage (1.2V) and providing a higher transfer rate. The SFPs (220) are a compact, hot-pluggable network interface module used for telecommunication and data communications applications. The RET connector (222) is configured to allow a tilt angle of an antenna to be controlled remotely. The eMMC (224) is an embedded non-volatile memory system having a flash memory and a flash memory controller to facilitate application interface design. The NOR (226) is a NOR logic gate that produces a high output only if all its inputs are false and low output otherwise. The status LEDs (228) indicate the operation status of the MIMO radio unit (200). The reset-in (232) and the reset button (230) reset the operations of the MIMO radio unit (200) and the debug connector (234) is used for debugging the MIMO radio unit (200). The LMP JTAG (236) facilitates verifying designs and testing printed circuit boards after manufacture. The GPS module (238) may include one or more processors and one or more antennas that receive data sent by satellites through dedicated RF frequencies. The digital side (210) is coupled with the FPGA (202).
[0042] The FPGA (202) includes a plurality of digital-to-analog converter (DAC) ports (DAC_0 to DAC_7) (240) that convert a digital signal into an analog signal and a plurality of analog-to-digital converter (ADC) ports (ADC_0 to ADC_9) (242) that converts an analog signal to a digital signal as shown in FIG. 2a to FIG. 2d. The FPGA (202) is an integrated circuit often sold off-the-shelf and is referred to as ‘field programmable’ as it provides customers the ability to reconfigure the hardware to meet specific use case requirements after the manufacturing process. This allows for feature upgrades and bug fixes to be performed in situ, which is especially useful for remote deployments. The FPGA (202) contains configurable logic blocks (CLBs) and a set of programmable interconnects that allow a designer to connect blocks and configure them to perform everything from simple logic gates to complex functions. All the functions related to the MIMO radio unit (200) such as digital signal processing are performed by the FPGA (202) and memory devices (i.e., eMMC, DDR4 and EEPROM) on the digital board (204), where the FPGA (202) is coupled with the digital board (204).
[0043] The digital board (204) includes a plurality of baluns (244), a plurality of low pass filters (LPFs) (246), a plurality of gain blocks (248), a plurality of digital step attenuators (DSAs) (250), a plurality of band pass filters (BPFs) (252), a pre-driver PA (254), a plurality of BypassLNAs (Low Noise Amplifiers) (BypassLNA1 and BypassLNA2) (256) and a plurality of Single Pole Double Throw (SPDT) RF switches (214) (aka “SPDT switch”). The plurality of baluns (244) allows balanced and unbalanced lines to be interfaced without disturbing the impedance arrangement of either line. The plurality of LPFs (246) passes signals with a frequency lower than a selected cutoff frequency. The plurality of gain blocks (248) amplifies the output signal received from the plurality of LPFs (246). The plurality of DSAs (250) receives the amplified output signal and passes to the respective pre-driver PA. The pre-driver PA (Power Amplifier) (254) increases the magnitude of the power of a given input signal. The plurality of BypassLNAs (BypassLNA1 and BypassLNA2) (256) amplifies a low-power signal without significantly degrading its signal-to-noise ratio. The plurality of band pass filters (BPFs) (252) passes frequencies within a certain range and rejects frequencies outside that range.
[0044] The PA section (206) comprises a plurality of driver power amplifiers (258), a plurality of power amplifiers (PAs) (268), a plurality of first LNAs (Low Noise Amplifiers) (262), circulators, RF connectors, a plurality of forward directional couplers (270) and a plurality of reverse directional couplers (272). The plurality of forward directional couplers (270) and the plurality of reverse directional couplers (272) propagate energy/power in a transmission line in each PA section (206). A cavity where the antenna will be connected is interfaced with the PA section (206). The PA section (206) is divided into two PCBs (206a, 206b) with each PCB comprising four PAs (268), where the four PAs (268) are arranged on a first PCB (206a) and four PAs (268) are arranged on a second PCB (206b). Alternatively, the PA section is divided into four PCBs (206a-206d) with each PCB comprising two PAs (268). Alternatively, the PA section is divided into eight PCBs (206a-206h) with each PCB comprising a single PA (208). As shown in FIG. 3a to FIG. 3d, the PA section (206) comprising two PCBs (206a, 206b) or four PCBs (206a-206d) or eight PCBs (206a-206h) are placed parallel to each other on the same axis to form a 1x8 transmitter/receiver port configuration so as to optimize space occupancy. Alternatively, as shown in FIG. 3e to FIG. 3h, the PA section (206) comprising the two PCBs (206a, 206b) or four PCBs (206a-206d) or eight PCBs (206a-206h) are stacked in the vertical direction to form a 2x4 transmitter/receiver port configuration so as to optimize space occupancy. These two configurations can be used for a four transmitter four receiver (4T4R) system by discarding one of the PCBs with four transmit/receive ports making the solution more agile and bringing modularity in the MIMO radio unit (200).
[0045] The aforesaid components in a radio frequency (RF) circuit are distributed among two types of printed circuit boards (PCBs) (i.e., digital board (204) and PA section (206)) to handle a heat issue, as mentioned earlier, generated by the power amplifiers (PAs) (HPA (268)). The components having a low power consumption and a low operating temperature are shifted onto the PCB of the digital board (204) from the PA section (206). Further, the PA section (206) and/or the power supply board (208) comprise a protection section that receives a telecom standard -48V supply as the main power source. The protection section includes necessary power supply filtering and protection circuits. The power supply filtering and protection circuits protect the MIMO radio unit (200) from the sudden transient voltage at its input.
[0046] Due to aforesaid arrangements, the size of the PA section (206) is reduced by around 7 percent. The three sections (digital board (204), PA section (206), and power supply board (208)) are arranged to achieve compact size (by around 10%) along with providing high noise isolation (around 0.4dB) and thermal management (Temperature reduction by 4-5 degrees) in the MIMO radio unit (200).
[0047] FIG. 4 illustrates a transceiver chain from the MIMO radio unit (200). Referring to FIG.4, a first LNA (Low Noise Amplifier) (262) in a receive path (LNA1) is kept in the PA section (206) to keep the losses from the first LNA (262) to the cavity filter (212) in the transmit-receive chain as low as possible as it governs the noise figure of the MIMO radio unit (200). The other two LNAs (BypassLNA1 and BypassLNA2) (256) in the receive path are not included in the PA section (206) because having so many components in a small space will raise the board's temperature and degrade their performance.
[0048] FIG. 5a illustrates the RFFE architecture of the MIMO radio unit (200) including switches for multiplexing feedback signals. As shown in FIG 2a to FIG. 2d, in the FPGA (202), there are a total of ten ADC ports available, eight of which are being used for receiving eight reception signals in the 8T8R configuration. So, only two ADC ports are available for sending the feedback signals back to the FPGA (202). As per the 8T8R configuration, there are a total of eight transmit signals and corresponding eight feedback signals are to be sent back to the FPGA (202). In order to address this issue, the feedback signals are multiplexed in the time domain such that the first four of them can be sent to one ADC port and the other four to the second ADC port, as explained below:
[0049] The unique arrangement of the plurality of Single Pole Double Throw (SPDT) switches (214) and an SP4T switch (264) are used to feedback the forward and reflected powers from all the transceiver chain to the FPGA (202), where an SPDT switch (214) has a single output and can connect to and switch between two inputs. This means it has two input terminals and one output terminal. The SPDT switch (214) can be in both positions, switching on a separate device in each case. It is often called a changeover switch. For example, the SPDT switch (214) can be used to switch on a red lamp in one position and a green lamp in the other position. The SPDT switch (214) receives two input signals i.e., forward power and reflected power from one transceiver chain as input and produces a feedback signal which acts as one of the four inputs to the SP4T switch (264). The isolation is maintained between the forward power and reflected power by the SPDT switch (214) and the corresponding fixed value attenuators (266). The SP4T switch (264) receives four feedback signals each of which is the multiplexed version of forward power and reflected power, corresponding to four transceiver chains.
[0050] As there are a total of eight transceiver chains per 8T8R configuration, two SP4T switches are used to produce signals to be input to the two available ADC ports. The digital board (i.e., SSG board) (204) comprises of the two SP4T switches (264), one switch at a place and the other at another place, each of which multiplexes four feedback signals, corresponding to four transceiver chains, thus conforming to 4T4R configuration.
[0051] The forward and reflected powers from the transceiver chain are multiplexed in time by the plurality of SPDT switches (214) in such a way that the time required to read the forward and reflected powers on respective ports is a fraction of the total time required by the transmit-receive cycle. This is achieved in a way that the first unit of time is spent reading forward power from the first port of the SPDT switch (214) and the reflected power is read in the second unit of time on the second port as these two signals are multiplexed in time to be given as an input feedback signal to one of the four input ports of the SP4T switch (264). The total time spent on this procedure should be less than one-fourth of the total time of the transmit-receive cycle, so that all the transceiver chains can be read during the transmit-receive cycle.
[0052] At any given time, only one of these four feedback signals from the SPDT switches (214) will be sent through the SP4T switch (264). During this time, all the other three SPDT switches are in the off state and the Voltage Standing Wave Ratio (VSWR) and Digital Pre-Distortion (DPD) correction are performed at the FPGA (202) for the transceiver chain associated with that SPDT switch (214). A similar process is followed for other SPDT switches as well to optimize the transceiver chain associated with other SPDT switches on the digital board (i.e., SSG board) (204).
[0053] FIG. 5b illustrates an alternative part of the PA section (206) of the MIMO radio unit (200) including the switches (214 and 264) for multiplexing feedback signals. FIG. 5c illustrates an alternative part of the PA section of the MIMO radio unit (200) including the switches (214 and 264) for multiplexing feedback signals. The operations and functions of the switches (214 and 264) for multiplexing feedback signals are explained in connection with FIG. 5a.
[0054] FIG. 6 illustrates a timing diagram (600) corresponding to the operation of the switches for multiplexing feedback signals as explained in conjunction with FIG. 5a to FIG.5c.
[0055] FIG. 7 is a flow chart (700) illustrating a method for designing the RFFE architecture of the MIMO radio unit (200). At 702, the method includes arranging a plurality of switches (e.g., SPDT switches (214) and SP4T switch (264)) to feedback forward and reflected powers from all transceiver chains to the FPGA (202). Each switch captures signals to achieve the total time spent on a transceiver chain less than one-fourth of the total time of a transmit-receive cycle, so that all the transceiver chains are read during the transmit-receive cycle.
[0056] The various actions, acts, blocks, steps, or the like in the flow chart (700) may be performed in the order presented, in a different order or simultaneously. Further, in some implementations, some of the actions, acts, blocks, steps, or the like may be omitted, added, modified, skipped, or the like without departing from the scope of the invention.
[0057] The embodiments disclosed herein can be implemented using at least one software program running on at least one hardware device and performing network management functions to control the elements.
[0058] It will be apparent to those skilled in the art that other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope of the invention. It is intended that the specification and examples be considered as exemplary, with the true scope of the invention being indicated by the claims.
[0059] The methods and processes described herein may have fewer or additional steps or states and the steps or states may be performed in a different order. Not all steps or states need to be reached. The methods and processes described herein may be embodied in, and fully or partially automated via, software code modules executed by one or more general purpose computers. The code modules may be stored in any type of computer-readable medium or other computer storage device. Some or all of the methods may alternatively be embodied in whole or in part in specialized computer hardware.
[0060] The results of the disclosed methods may be stored in any type of computer data repository, such as relational databases and flat file systems that use volatile and/or non-volatile memory (e.g., magnetic disk storage, optical storage, EEPROM and/or solid state RAM).
[0061] The various illustrative logical blocks, modules, routines, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality can be implemented in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure.
[0062] Moreover, the various illustrative logical blocks and modules described in connection with the embodiments disclosed herein can be implemented or performed by a machine, such as a general purpose processor device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general-purpose processor device can be a microprocessor, but in the alternative, the processor device can be a controller, microcontroller, or state machine, combinations of the same, or the like. A processor device can include electrical circuitry configured to process computer-executable instructions. In another embodiment, a processor device includes an FPGA or other programmable device that performs logic operations without processing computer-executable instructions. A processor device can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, a processor device may also include primarily analog components. A computing environment can include any type of computer system, including, but not limited to, a computer system based on a microprocessor, a mainframe computer, a digital signal processor, a portable computing device, a device controller, or a computational engine within an appliance, to name a few.
[0063] The elements of a method, process, routine, or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor device, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of a non-transitory computer-readable storage medium. An exemplary storage medium can be coupled to the processor device such that the processor device can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor device. The processor device and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In the alternative, the processor device and the storage medium can reside as discrete components in a user terminal.
[0064] Conditional language used herein, such as, among others, "can," "may," "might," "may," “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain alternatives include, while other alternatives do not include, certain features, elements and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more alternatives or that one or more alternatives necessarily include logic for deciding, with or without other input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular alternative. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list.
[0065] Disjunctive language such as the phrase “at least one of X, Y, Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain alternatives require at least one of X, at least one of Y, or at least one of Z to each be present.
[0066] While the detailed description has shown, described, and pointed out novel features as applied to various alternatives, it can be understood that various omissions, substitutions, and changes in the form and details of the devices or algorithms illustrated can be made without departing from the scope of the disclosure. As can be recognized, certain alternatives described herein can be embodied within a form that does not provide all of the features and benefits set forth herein, as some features can be used or practiced separately from others.