Description:
F O R M 2

THE PATENTS ACT, 1970
(39 of 1970)

COMPLETE SPECIFICATION
(See section 10 and rule 13)

TITLE
MULTIPLE-VALUE LOGIC CIRCUIT USING CARBON NANO TUBE FIELD EFFECT TRANSISTORS

INVENTORS
HATTI, Kaveri- Indian Citizen
#6-71,6-72, Kodla
Kalaburagi, Karnataka 585222, India

CHINNUSAMY, Paramasivam– Indian Citizen
44, Sathirakkattu Valasu
Arachalur (Via) Kasthuriba Gramam (Po)
Kongudaiyampalayam, Erode, Tamil Nadu 638101, India

SELVAM, Mullai Venthan– Indian Citizen
1/116, New Colony, Nallampalli, Nallampalli Post
Dharmapuri, Tamil Nadu 636807, India

APPLICANTS
Amrita Vishwa Vidyapeetham
Bengaluru Campus, Kasavanahalli, Carmelaram P.O.,
Bangalore – 560035, India

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED:

MULTIPLE-VALUE LOGIC CIRCUIT USING CARBON NANO TUBE FIELD EFFECT TRANSISTORS
CROSS-REFERENCES TO RELATED APPLICATION
None.
FIELD OF THE INVENTION
The disclosure generally relates to electronic device security, and in particular to physical unclonable function (PUF) architecturefor generating security keys.
DESCRIPTION OF THE RELATED ART
Enabling data security against unwanted access is a significant task for electronic devices. The majority of traditional cryptography methods store their "keys" in non-volatile memory, causing them to be vulnerable to faults, side-channel assaults, physical attacks, and other types of external attacks. Physical unclonable functions (PUFs) are a promising solution to these problems because they are hard to replicate and do not keep keys indefinitely. Physical Unclonable Functions (PUFs) use unique and unpredictable physical properties to identify, authenticate, and generate secret keys.
The primary purpose of employing a Physical Unclonable Function (PUF) is to generate unique, inherently random, and difficult-to-replicate identifiers or keys based on the physical characteristics of the underlying hardware. PUFs influence the integral variations found in physical structures or properties of hardware components, like transistors or memory cells, to create these unique identifiers or keys. These identifiers are used for various security applications, including device authentication, secure key generation, anti-counterfeiting measures, and cryptographic protocols. PUFs offer a robust security mechanism due to their integral uniqueness, making them valuable in safeguarding sensitive data, securing hardware, and verifying the authenticity of devices or components.
The first Ring Oscillator(RO) PUF was created for secret key generation and authentication in cryptography. It includes two N-to-1 MUX connected to N-ring oscillators. The outputs of the multiplexers are connected to two counters whose valuesare compared by a comparator. Each RO was built with one NAND gate and several inverter gates. Multiplexers select specific ring oscillators, initiate oscillation, and track counter values. After a set time, the comparator checks the counters; if the upper counter is greater, it produces logic "1" output, and if the lower counter is greater, it produces logic "0".
In Configurable Ring Oscillator PUF (CRO-PUF) the core logic stage of the RO, typically a single inverter gate, is upgraded to a flexible logic stage capable of handling multiple delay variations. This modification enhances the PUF's Reliability while reducing hardware resources. In CRO-PUF, the RO unit is designed by introducing MUX units between the NOT gates, thereby altering the RO's structure. While this approach consumes significant hardware resources, it can generate more CRPs than the NOT-based RO PUF.
In the Reconfigurable Ring Oscillator PUF (RRO-PUF) architecture, the programmable nodes {S0, S1, ..., Sn-1} of the MUX are employed to specify the conduction path for generating a Ring Oscillator. Discrepancies arise due to changes in the manufacturing of the wires connected to the multiplexers. The RRO PUF design utilizes less hardware resources as compared to CRO PUF.
Carbon Nanotube Field-Effect Transistors (CNTFETs) are often utilized in Physical Unclonable Function (PUF) architectures due to their unique properties that make them suitable for generating unpredictable and unique identifiers. CNTFETs exhibit inherent variability in their electrical characteristics due to imperfections and irregularities in the carbon nanotube structure. This variability can be exploited to create unique identifiers for each CNTFET. CNTFETs offer the potential for low power consumption, making them suitable for energy-efficient implementations of PUFs in resource-constrained devices such as IoT devices or embedded systems.There are three primary categories of CNTFETs based on the connection between the source/drain regions and CNT channels as well as the type of source/drain regions. Schottky Barrier CNTFETs (SB-CNTFETs) are the first kind with their metallic source and drain regions. The Schottky barrier junctions in this kind of CNTFET reduce the trans conductance in the ON state and raise the reverse currents in the OFF state, resulting in a relatively low ION/IOFF ratio. Applications requiring medium to high performance should use SB-CNTFETs. The band-to-band tunnelling CNTFET (T-CNTFET), which has CNT source and drain regions with opposing doping types, is the second type of CNTFET. T-CNTFETs have low ON current and super cut-off characteristics. T-CNTFETs are not suitable for high-performance applications but are suitable for low-standing power applications. The third type is MOSFET-like CNTFET, in which the source and drain are similar to MOSFET. For nCNTFETs, the source and drain are doped with n+, and pCNTFETs, the source and drain are doped with p+. Due to its extremely high ION/IOFF ratio, MOSFET-like CNTFETs are well suited for high-performance and energy-efficient applications.
Chinese patent 106850227A discloses a Three-Value Physically Unclonable Function (PUF) circuits implemented using Carbon Nanotube Field-Effect Transistors (CNFETs). The PUF units described in the invention utilize CNFETs as their basic building blocks. The PUF units consist of multiple CNFET pipes (individual CNFETs) arranged in a specific configuration. Another Chinese patent 109167664B presents a reconfigurable ring oscillator PUF circuit based on exclusive-OR gate. This consists of a PUF delay module and a tail end control module. The PUF delay module comprises n series delay units, while the tail end control module incorporates a similar delay unit and a feedback control unit, achieving simplicity, high reliability, and increased excitation response pairs with less resource consumption. In ‘Multi-valued logic arbiter PUF designs based on CNTFETs’ Hossein Momeni et. al. proposes a multi-valued logic Arbiter Physical Unclonable Functions (APUFs) employing Carbon Nanotube Field Effect Transistors (CNTFETs), aiming to enhance security by increasing challenge-response pairs.
However, the circuit design of PUF architecture can still be enhanced by focusing on simplicity while leveraging the capabilities of CNTFETs for gate design. Employing multi-valued logic gates, such as ternary and quaternary logic gates, in a PUF improves reliability and security, leading to a significant increase in challenge-response pair size. In the case of Multi-Value logic (MVL) ternary and quaternary-based configurable exclusive OR-based reconfigurable ring oscillator PUF (CXRRO-PUF), its flexibility in placing delay chains stems from the inherent randomness present in the fluctuations of ring oscillator frequencies. This property is crucial for better protection against modelling attacks, as the re-configurability of the PUF makes it challenging to predict responses, thereby reducing the prediction rate.
SUMMARY OF THE INVENTION
The invention in various embodiments discloses a Multi Value Logic (MVL) based Physical Unclonable Function (PUF) circuit employing a Configurable Exclusive OR-based Reconfigurable Ring Oscillator (CXRRO). The components present in the PUF utilize Carbon Nano Tube Field Effect Transistors (CNTFET) based transmission gates. The circuit comprises an upper delay chain group, a lower delay chain group and p number of D-latches.
The upper delay chain group and the lower delay chain group concurrently receive n-bit challenges and generates p-bit responses through the p number of D-latches. Each of the upper delay chain group and the lower delay chain group comprises p number of delay chains. The pth upper delay chain output is connected to the D-input of the pth D-latch, and the pth lower delay chain output is connected to the clock-input of the pth D-latch.
Each delay chain comprises a plurality of delay units connected serially to one of the inputs of an AND gate to form a Ring Oscillator (RO). Each delay unit comprises a multi value logic multiplexer (MUX) and an XOR gate, wherein the output of the MUX is connected to an input of the XOR gate and the output of XOR gate forms an input to the next delay unit.
Thex-bit input challenges are partitioned into two x/2-bit segments, wherein the least significant x/2- bits (LSB) of the input challenges are sequentially connected to select line of each multi value logic MUX and the most significant x/2-bits (MSB) of the input challenges are sequentially connected to an input of the XOR gate. The AND gate controls the oscillation of the delay chain with the help of an enable input.
In various embodiments, the value of n ranges in the power of 2 from 23 to 29 and the value of prange in the power of 2 from 20 to 26. A 2x bit challenge generates 2x-3 bit responses. Each delay chain comprises 4 delay units.
In certain embodiments, the PUF circuit is characterized as a ternary logic CXRRO PUF.The multi value logic MUX used for the design of ternary CXRRO-PUF is a ternary input MUX utilizing six CNTFET based transmission gates.
In certain embodiments, the PUF circuit is characterized as a quaternary logic CXRRO PUF.The multi value logic MUX used for the design of quaternary CXRRO-PUF is a quaternary input MUX utilizing eight CNTFET based transmission gates.
In various embodiments, the XOR gates, AND gates and D-latches are implemented utilizing CNTFET based transmission gates.
In various embodiments, the multi logic MUX, configured as ternary MUX, comprises three inputs representing zero, half and full of primary power voltage. The multi logic MUX, configured as quaternary MUX, comprises four inputs representing zero, half, two-third and full of primary power voltage.
In various embodiments, the XOR gate is configured as NOT gate or Buffer by setting one of the inputs to logic "1" or logic "0", respectively. The MSB of the challenge input configures the XOR gate as either a NOT gate or a Buffer.
This and other aspects are described herein.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention has other advantages and features, which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:
FIG. 1A shows the circuit diagram of Multi Value Logic configurable exclusive OR-based reconfigurable ring oscillator Physical Unclonable Function (CXRRO-PUF).
FIG. 1B shows a single delay chain in the CXRRO-PUF design.
FIG. 2A shows the circuit diagram of Ternary configurable exclusive OR-based reconfigurable ring oscillator Physical Unclonable Function (TCXRRO-PUF).
FIG. 2B shows Ternary MUX block used in the design of Ternary CXRROPUF.
FIG. 2C shows Ternary MUX designed using Transmission gates.
FIG. 2D shows optimized CNTFET based XOR gate.
FIG. 2E shows D-latch designed using transmission gates.
FIG. 2F showsCNTFET based AND gate.
FIG. 3A shows the circuit diagram of Quaternaryconfigurable exclusive OR-based reconfigurable ring oscillator Physical Unclonable Function (QCXRRO-PUF).
FIG. 3B shows Quaternary MUX block used in the design of Quaternary CXRRO-PUF.
FIG. 3C shows Quaternary MUX designed using Transmission gates.
FIG. 4illustratesCRP Size for three different logic levels of PUF, namely Classical Ring Oscillator PUF, Ternary CXRRO-PUF and Quaternary CXRRO-PUF.
FIG. 5Aillustrates the Uniqueness of CXRRO responses under 27oC with inter Hamming Distance (HD) for Ternary CXRRO-PUF.
FIG. 5Billustrates the Uniqueness of CXRRO responses under 27oC with inter Hamming Distance (HD) for Quaternary CXRRO-PUF.
FIG. 6Aillustrates Monte Carlo results for 100 CXRRO PUF responses under 27oC for Ternary CXRRO-PUF.
FIG. 6Billustrates Monte Carlo results for 100 CXRRO-PUF responses under 27oC for Quaternary CXRRO-PUF.
FIG. 7Aillustrates reliability (intra Hamming Distance) of Ternary CXRRO-PUF and quaternary CXRRO-PUF with varying temperature from 0oC to 100oC.
FIG. 7Billustrates reliability (intra Hamming Distance) of Ternary CXRRO-PUF and quaternary CXRRO-PUF with varying voltage from 0.8V to 1V.
DETAILED DESCRIPTION OF THE EMBODIMENTS
While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.
Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on.” Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.
The present subject matterin various embodiments describesMulti-Value Logic based Ring Oscillator PUF circuit designs. These circuit designs feature a ring oscillator structure based on configurable exclusive OR based reconfigurable ring oscillator (CXRRO)100. The various components present in the PUF architecture, such as MUX, XOR, AND D-latch, are constructed using CNTFET-based transmission gates. A Ternary Multi-Value Logic PUF is realized through three-input MUXs202 and a Quaternary Multi-Value logic PUF is realized through four-input MUXs302. The design offers improved resilience against modeling attacks due to the re-configurability property of the CXRRO-PUF, which complicates response prediction.Performance parameters of the ternary and quaternary CXRRO PUFs, such as uniqueness, are approximately 48% and 49%, respectively, which are close to the ideal value of 50%.
In various embodiments shown in FIG. 1A, a Multi-Value Logic configurable exclusive OR-based reconfigurable ring oscillator Physical Unclonable Function (CXRRO-PUF) circuit100. The circuit comprises an upper delay chain group 130, a lower delay chain group140, and p number of D-latches150. The upper delay chain group130 and the lower delay chain group 140 concurrently receive n-bit challenges and generates p-bit responses through the p number of D-latches150. Each of the upper delay chain group and the lower delay chain group comprises p number of delay chains 120. The pth upper delay chain output is connected to the D-input of the pth D-latch, and the pth lower delay chain output is connected to the clock-input of the pth D-latch.
In various embodiments, as shown in FIG 1B, a single delay chain120 comprisesa plurality of delay units 110 connected serially to one of the inputs of an AND gate106 to form a Ring Oscillator (RO). In various embodiments a single delay chain comprises 4 delay units. A single delay unit110 is a combination of a multi value logicMUX102 and XOR gate104. The output of the MUX forms one of the input of the XOR gate. The output of the XOR gate forms the input to the next delay unit. Four such delay units are connected back to back, and the output of the fourth delay unit is connected to one of the inputs of an AND gate106. The other input of the AND gate is given to enable the (en) pin.The output of the AND gate is connected back to the first delay unit, where it forms the Ring Oscillator. Such a combination of 4 single delay units and the AND gate forms the single delay chain. Such delay chains are instantiated depending on the length of response bits.
In various embodiments, the delay chains 120 are grouped into upper 130 and lower140 delay chain groups. There are p numbers of delay chains in each group. To generate a single-bit response, the output of thepth upper delay chain is connected to the D input of a D latch150 and thepth lower delay chain output is connected to the input of the D-latch clock(CLK), as shown in Fig 1A. One D-latch is needed to generate the single-bit response. The number of response bits (R0, R1,---Rp-1) is equal to the number of D latches.The D-latch generates a single-bit response based on the delay between upper and lower delay chains.
In various embodiments, n-bit challenges are given as input for the CXRRO-PUF. The n-bit challenges are concurrently received by both the upper delay chain group130 and the lower delay chain group140. In each delay chain group, the n-bit input challenges are partitioned into two n/2-bit segments, wherein the least significant n/2- bits (LSB) of the input challenges are sequentially connected to select line of each multi value logic MUXs 102in the delay units. The most significant n/2-bits (MSB) of the input challenges are sequentially connected to an input of the XOR gate104. The AND gate106 controls the oscillation of the delay chain with the help of an enable input.
In various embodiments, the MUXs102, the XOR gates104, AND gates 106 and D-latches 150 are implemented utilizing CNTFET based transmission gates.A Carbon nanotube (CNT) is a graphene sheet that is wrapped up along a wrapping vector, which can be single-wall (SWCNT) or multi-wall (MWCNT). A single coaxial nanotube makes up a single-wall CNT, whereas two or more coaxial nanotubes make up a multi-wall CNT. The graphene sheet is predicted to roll up into a tube based on a vector known as the chiral vector(n1, n2). According to (n1, n2), SWCNT turns into a conductor if n1- n2=3k, k is an integer; otherwise, it turns into a semiconductor. Semiconducting CNTs are used as transistor channels, and conductive CNTs are employed as on-chip interconnects.
The nanotube diameter of a CNTFET can be easily adjusted to adjust its threshold voltage. It is a very useful device for building MVL circuits. There are three primary categories of CNTFETs based on the connection between the source/drain regions and CNT channels as well as the type of source/drain regions. Schottky Barrier CNTFETs (SB-CNTFETs) are the first kind with their metallic source and drain regions. The Schottky barrier junctions in this kind of CNTFET reduce the transconductance in the ON state and raise the reverse currents in the OFF state, resulting in a relatively low ION/IOFF ratio. Applications requiring medium to high performance should use SB-CNTFETs. The band-to-band tunnelling CNTFET (T-CNTFET), which has CNT source and drain regions with opposing doping types, is the second type of CNTFET. T-CNTFETs have low ON current and super cut-off characteristics. T-CNTFETs are not suitable for high-performance applications but are suitable for low-standing power applications. The third type is MOSFET-like CNTFET, in which the source and drain are similar to MOSFET. For nCNTFETs, the source and drain are doped with n+, and pCNTFETs, the source and drain are doped with p+. Due to its extremely high ION/IOFF ratio, MOSFET-like CNTFETs are well suited for high-performance and energy-efficient applications. In various embodiments, the CXRRO-PUF circuits are designed using MOSFET-like CNTFET.
In certain embodiments, the PUF circuit is characterized as a ternary logic CXRRO PUF200, as shown in FIG. 2A.The multi value logic MUX used for the design of ternary CXRRO-PUF is a ternary logic MUX 202utilizing six CNTFET based transmission gates.Multi-significant logic levels are included in multiple-valued logic. The ternary logic comprises three levels represented by the symbols '0', '1', and '2'; these symbols correspond to the voltage levels of '0', '1/2VDD', and 'VDD', respectively. Table 1 presents the truth table of a ternary NOT gate. Standard ternary inverter (STI), positive ternary inverter (PTI), and negative ternary inverter (NTI) are the three types of ternary inverters. The output of inverters is defined by the inputs given to it.

Table 1: Ternary Inverter Gate Truth Table
Input NTI STI PTI
2 2 0 0
1 0 1 0
0 0 2 2
In various embodiments, the CNTFETs' nanotube diameter values are the same for every transistor, which is1.48 nmand thus the design provides balanced circuit characteristics. The block diagram of ternary MUX 202 is shown in FIG 2B.It is designed using CNTFET-based six transmission gates illustrated in FIG. 2C. It has three inputs: I0, I1, and I2, corresponding to 0, 1/2VDD, VDD, the select line input S and out Y.
In various embodiments, the ternary CXRRO PUF(TCXRRO PUF)200,shown in FIG. 2A, comprises an upper delay chain group230, a lower delay chain group 240 and 8 D-latches250. The TCXRRO PUF consists of eight delay chains 220 in the upper delay chain group, and eight delay chains in the lower delay chain group, as shown in FIG. 2A. A single delay chain220 is created by connecting four single delay units210 serially, and the output of such chain is connected to one of the two inputs of the ANDgate106 to form the Ring Oscillator(RO). The single delay unit is designed by connecting the output of ternary MUX202 to one of the inputs of the optimized XOR gate104.The CNTFET-based AND gate106 shown in FIG. 2F is used to control the oscillation of the delay chain with the help of enable (en) input.
The upper delay chain groups230 and lower delay chain groups240 receive the same 64-bit challenge at a time and generate an 8-bit response through D-latches250. The 64-bit input challenges are split into two 32-bits. The LSB 32-bit input challenges (C0C1C3…..C31) are given to the ternary MUX 202 select line, which decides the output from the three multiplexer input signals. The MSB 32-bit input challenges (S0S1S3…..S31) are given to the XOR gate104. These challenges inputs configure the XOR gate as either NOT gate or Buffer. The optimized XOR gate is designed using CNTFET, shown in FIG 2D.The XOR gate is configured as NOT gate or Buffer by setting one of the inputs to logic "1" or logic "0", respectively.
The upper delay chain output is connected to the D input of the D-latch, and the lower delay chainoutput is connected to the clock input of the D-latch. Further, based on the delay difference between the upper and lower delay chain, the D-latch decides the random single-bit response.The D-latch is implemented using CNTFET based transmission gates, as shown in FIG. 2E. The truth table of D-latch is given in Table 2 and the truth table of ternary MUX is given in Table 3.
Table 2: Truth Table of D-latch
Clock(C) Out(Q)
0 Previous state
1 D
2 D
Table 3: Truth Table of Ternary MUX
Select(S) Out(Y)
0 I0
1 I1
2 I2
The sample size of the outputs is increased due to the potential production of38 different combinations of outputsby each delay chain. The D latch output is used to generate the single-bit response through the connection of the outputs of two individual delay chains, one from the upper and the other from the lower delay chains that are connected to the D and clock(C) inputs as shown in FIG 2A. Thus, a single sample of the 64-bit challenge input is used to generate each of the eight-bit responses, R0, R1,..., R8.
In certain embodiments, the PUF circuit is characterized as a quaternary logic CXRRO PUF300, as shown in FIG. 3A. The multi value logic MUX used for the design of quaternary CXRRO-PUF is a quaternary logic MUX302 utilizing eight CNTFET based transmission gates.The block diagram of quaternary MUX302 is shown in FIG. 3B.It is designed using 8 CNTFET-based transmission gates, illustrated in FIG. 3C.It has four inputs: I0, I1, I2 and I3, corresponding to 0, 1/2VDD, 2/3VDD and VDD, a select line input S and out Y. Table 4shows the inputs and outputs of a four-input (quaternary) NOT gate. Standard quaternary inverter (SQI), negative quaternary inverter (NQI), Positive quaternary inversion (PQI), and intermediate quaternary inverter (IQI) are the four types of inversion in quaternary logic. The input quit specifies which of the four quaternary inverters is operational.
Table 4: Quaternary Inverter Gates Truth Table
Input SQI NQI PQI IQI
0 3 3 3 3
1 2 0 3 3
2 1 0 3 0
3 0 0 0 0
In various embodiments, the quaternary CXRRO PUF, shown in FIG. 3A comprises an upper delay chain group330, a lower delay chain group340 and a plurality of D-latches350. The Quaternary CXRRO (QCXRRO) PUF 300 consists of eight delay chains in the upper delay chain group and eight delay chains in the lower delay chain group. Each delay chain320 consists of 4 single delay units connected serially to one of the two inputs of the AND gate106 to form a Ring Oscillator (RO). The single delay unit310 is designed by connecting the output of quaternary MUX302 to one of the inputs of the optimized XOR gate104.
The upper delay chain group 330 and lower delay chain group 340 receive the same 64-bit challenge at a time and generate an 8-bit response through D-latches350. The 64-bit input challenge is split into two 32-bits. The LSB 32-bit input challenges (C0C1C3…..C31) are given to the select line of the quaternary MUX302, which decides the output from the four multiplexer input signals. The MSB 32-bit input challenges (S0S1S3…..S31) are given to the XOR gate104. These challenges inputs configure the XOR gate as either NOT gate or Buffer. The upper delay chain output is connected to the D input of the D-latch, and the lower delay chain output is connected to the clock input of the D-latch. Based on the delay difference between the upper and lower delay chain, the D latch350 decides the random single-bit response. The truth table of D-latch is given in Table 5 and truth table of quaternary MUX is shown in Table 6.
Table 5: Truth Table of D-latch
Clock (C) Out (Q)
0 Previous state
1 Previous state
2 D
3 D
Table 6: Truth Table of Quaternary MUX
Select (S) Out (Y)
0 I0
1 I1
2 I2
3 I3
The sample size of the outputs is increased due to the potential production of48 different combinations of outputs by each delay chain. The D-latch output is used to generate the single-bit response through the connection of the outputs of two individual delay chains, one from the upper and the other from the lower delay chains that are connected to the D and clock(C) inputs. Thus, a single sample of the 64-bit challenge input is used to generate each of the eight-bit responses, R0, R1,..., R8. This architecture facilitates the generation of extensive Challenge- Response pairs CRPs for a single sample at a time.
The ternary and quaternary CXRRO-PUF necessitates a minimum configuration of a pair of single delay chains from lower and upper delay chain groups with one D-latch to generate a 1-bit response. The maximum numbers of 512 bit challenges are utilized to yield the corresponding 64-bit response in the TCXRRO PUF to enhance the unpredictability rate. Table 7 represents the minimum and maximum challenge-response bits with details of a number of D latches and a number of delay chains.
Table 7: Details of Minimum and Maximum Challenge Response Bits
Challenge(bits) Response(bits) Pair of the single delay chain D latches
8 1 1 1
16 2 2 2
32 4 4 4
64 8 8 8
128 16 16 16
256 32 32 32
512 64 64 64
The invention has multiple advantages as further set forth herein. The ternary and quaternary logic-based CXRRO PUF generates an average of 66.45% increment in CRP size as compared to binary logic. Further, quaternary logic-based CXRRO PUF generates a 56% increment in CRP size as compared to ternary logic-based CXRRO PUF. This expansion exponentially increases the difficulty to access CRP pairs, thus improving security. TCXRRO and QCXRRO PUFs exhibit notably higher uniqueness values compared to other existing PUF architectures. This signifies a greater degree of distinguishability between individual instances of these PUFs, enhancing their effectiveness in authentication and cryptographic tasks. Both TCXRRO and QCXRRO PUFs showcase nearly optimal uniformity in their response distributions which ensures a balanced representation of each state within the response bits, promoting reliability and consistency in their performance. The multi valued CXRRO PUFs show case higher level of entropy values which enhances security against various attacks. Both the ternary and quaternary CXRRO PUFs maintain high levels of performance integrity, making them most suitable for real-world applications.
While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material the teachings of the invention without departing from its scope, which should be as delineated in the claims appended herewith.
EXAMPLES
Example 1: Simulation and comparative study of Ternary and Quaternary CXRRO PUF architecture with classical Ring Oscillator PUF architecture.
Cadence Virtuoso is utilized to simulate each of the CXRRO PUF designs with standard 32nm CNTFET technology. The 8-bit response result is obtained from the 64-bit input challenge. To obtain a 64-bit response, MSB bits assigned to XOR input varied 8 times in order to form a ring oscillator to produce a 64-bit PUF response.. The simulation is computed with operating parameters of temperature = 27°C and reference voltage VDD = 0.9V.
CRP size: The challenge and response (CRP) pairs for classical RO PUFs are 0,1, for which the CRP size is 2C states. Meanwhile, CRP for ternary CXRRO PUF values are 0,1,2, for which the CRP size is 3C states. Likewise, the challenge and response values for a quaternary PUF are 0,1,2,3, although the CRP size has 4C states. From the standpoint of PUF security, an adversary faces greater difficulty in gaining access to the CRP pairs as the number of states increases. The CRP size exponentially increases in proportion to the quantity of challenge bits, shown in FIG. 4.
When 64 inputs are utilized as a challenge in a ternary CXRROPUF, the CRP size grows by over 1.81*1011 when compared to a binary ROPUF. Likewise, when comparing ternary and quaternary CXRROPUFs, the CRP size in the quaternary ROPUF grows by almost 9.91*107.
Uniqueness: Uniqueness is estimated that different CXRRO PUFs will produce distinct output responses when they are presented with the same challenge set sequence.
The uniqueness value of ternary CXRRO PUF and quaternary CXRRO PUF is 48% and 49%, respectively as shown in Fig.8. The obtained uniqueness value of ternary CXRRO PUF and quaternary CXRRO PUF is 2% and 4% respectively higher than binary existing RO PUFs. The following equation is used to compute the uniqueness:
U=2/(K(K-1)) ?_(i=1)^(K-1)¦?_(j=i+1)^K¦(HD(R_i,R_j))/n×100%
HD represents the hamming distance is calculated between the two responses generated from two distinct PUFs for the same challenges, Ri is the response generated from ithPUF, Rj is the response generated from jthPUF, and uniqueness is represented as U, response size is n, and the number of evaluated PUFs represented as k.
FIG. 5A and FIG. 5B illustrate the inter-chip HD for the designs, which are the result of a ternary CXRRO PUF and a quaternary CXRRO PUF, respectively.
Uniformity: Uniformity of existing binary RO PUF is defined as the equal distribution of the number of "0" s and the number of "1" s in a given response bits. The optimal uniformity value of the binary ROPUF design is 50%. Similarly, in a ternary CXRRO PUF, the uniformity is defined as equal distribution of the number of "0" s, the number of "1" s and the number of "2" s in a given response bits. The optimal uniformity value of the TCXRRO PUF design is 33.33%. Similarly, in a quaternary CXRRO PUF, the uniformity is defined as an equal distribution of the number of "0" s, the number of "1" s, the number of "2" s and the number of "3" s in a given response bits. The optimal uniformity value of the QCXRRO PUF design is 25%. The Monte-Carlo analysis is used to find the uniformity of the proposed TCXRRO PUF and QCXRRO PUF. The results of the TCXRRO PUF and QCXRRO PUF design under nominal operating conditions are shown in FIG. 6A and FIG. 6B, respectively. In the ternary CXRRO PUF, the response values of 0's, 1's, and 2's, are randomly distributed and its values are 32%, 33% and 32.1%, respectively. In the QCXRRO PUF, the response values of 0's, 1's, 2's, and 3's are randomly distributed and its values are 23%,24%,23.9 and 23%, respectively. Therefore the TCXRRO and QCXRRO PUFs uniformity value is near to optimal.
Entropy: Entropy is a performance parameter used to evaluate the unpredictability rate of the proposed CXRRO PUF designs. The below equation is used to compute entropy:
H(X)= -?_(i=0)^n¦?P(x_i)? ?log?_2 (P(x_i))
Here, H(X) represents the entropy of a random variable X, and the number of 0’s or 1’s occurrence probability is represented as P(xi) of the corresponding outcome xi. n is a number of samples. The entropy value of the binary RO PUF is 1.00. The entropy values of the proposed TCXRRO PUF and QCXRRO PUF are 1.5846 and 1.9998, respectively. The value of the entropy in TCXRRO PUF and QCXRRO PUF is increased by 0.5846 and 0.9998, respectively, as compared to binary RO PUF.
Reliability: Reliabilityis one of the most important performance parameters to measure the similar response bits generation by the same PUF instances under different environmental conditions such as temperature and voltage.The PUF reliability is determined using the equation fromm observations by presenting the same challenge to the same PUF in different environmental conditions.
R=(100-1/m ?_(t=1)^m¦(HD(R_i,R_(i,t)))/n)×100%
Where HD(Ri, Ri,t) is the hamming distance between the nominal response (Ri) and the responses produced at varying environmental conditions (Ri,t), n is the response length. Reliability tests for the ternary and quaternary CXRRO PUFs operating at various supply voltages and temperatures are shown in FIG. 10A and FIG. 10B, respectively.
The optimal value of the reliability is 100%. The reliability value of the TCXRRO PUF and QCXRRO PUF is an average of 99% and 98%, respectively. The graph shows that the reliability of TCXRRO PUF is better compared to the QCXRRO PUF with varying temperature and voltage. The results demonstrate that the CXRRO PUF designs can produce balanced random responses even with a variation in supply voltage and temperature.

, Claims:We claim:
A Multi Value Logic (MVL) based Physical Unclonable Function (PUF) circuit (100) employing a Configurable Exclusive OR-based Reconfigurable Ring Oscillator (CXRRO) (120) utilizing Carbon Nano Tube Field Effect Transistors(CNTFET), the circuit comprising:
an upper delay chain group (130),
a lower delay chain group (140), and
p number of D-latches (150);
wherein the upper delay chain group (130) and the lower delay chain group (140) concurrently receive n-bit challenges and generates p-bit responses through the p number of D-latches (150);
wherein each of the upper delay chain group (130) and the lower delay chain (140) group comprises p number of delay chains (120);
wherein the pth upper delay chain output is connected to the D-input of the pth D-latch, and the pth lower delay chain output is connected to the clock-input of the pth D-latch (150);
wherein each delay chain (120) comprises a plurality of delay units (110) connected serially to one of the inputs of an AND gate (106) to form a Ring Oscillator (RO);
wherein each delay unit (110) comprises a multi value logic multiplexer (MUX) (102) and an XOR gate (104), the output of the MUX is connected to an input of the XOR gate and the output of XOR gate forms an input to the next delay unit;
wherein the n-bit input challenges are partitioned into two n/2-bit segments, wherein the least significant n/2- bits (LSB) of the input challenges are sequentially connected to select line of each multi value logic MUX and the most significant n/2-bits (MSB) of the input challenges are sequentially connected to an input of the XOR gates; and
wherein the AND gate (106) controls the oscillation of the delay chain (120) with the help of an enable input.

The PUF as claimed in claim 1, wherein the value of n ranges in the power of 2 from 23 to 29 and the value of p ranges in the power of 2 from 20 to 26.

The PUF as claimed in claim 1, wherein 2x bit challenges generates 2x-3 bit responses.

The PUF as claimed in claim 1, wherein each delay chain comprises 4 delay units.

The PUF circuit as claimed in claim 1, the PUF circuit is characterized as a ternary logic CXRRO PUF (200), wherein the multi value logic MUX is a ternary input MUX (202) utilizing six CNTFET based transmission gates.

The PUF circuit as claimed in claim 1, the PUF circuit is characterized as a quaternary logic CXRRO PUF (300), wherein the multi value logic MUX is a quaternary input MUX (302) utilizing eight CNTFET based transmission gates.

The PUF circuit as claimed in claim 1, wherein the XOR gates (104), AND gates (106) and D-latches (150)are implemented utilizing CNTFET based transmission gates.

The PUF circuit as claimed in claim 4, wherein the multi logic MUX, configured as ternary MUX (202), comprises three inputs representing zero, half and full of primary power voltage.

The PUF circuit as claimed in claim 5, wherein the multi logic MUX, configured as quaternary MUX (302), comprises four inputs representing zero, half, two-third and full of primary power voltage.

The PUF circuit as claimed in claim 1, wherein the XOR gate (104) is configured as NOT gate or Buffer by setting one of the inputs to logic "1" or logic "0", respectively.

The PUF circuit as claimed in claim 1, wherein the MSB of the challenge input configures the XOR gate as either a NOT gate or a Buffer.

Dated this 8 May 2024

(Dr. V. SHANKAR
IN/PA-1733)
For and on behalf of the Applicants