NAND gate based nonvolatile memory external interface architecture for general
purpose data processing devices
FIELD OF THE INVENTION
The field of this invention is digital logic design with hardware description languages.
Verilog HDL has been used to design digital interface between data processing
device and NAND gate based nonvolatile memory device.
BACKGROUND OF THE INVENTION
The extent of data processing and on board storage in real time application has
increased many folds in the recent past. Augmenting an existing data processing
device towards high performance side often demands inclusion of large data storage
nonvolatile memory devices. It generated a critical requirement for high amount of
memory with less space and fewer electrical signal footprint. Conventional
asynchronous memory devices cannot handle high throughput requirements; hence
there is need to incorporate high density devices in the design. NAND gate based
nonvolatile memory device can be utilized to enhance the on board nonvolatile
storage capacity. General purpose low capacity data processing devices are not
equipped with to handle the access requirements of these devices; hence there rises
a need to bridge NAND based nonvolatile storage devices with conventional data
processing devices, without modifying silicon design.
SUMMARY OF PRESENT INVENTION
In accordance with one aspect of present invention, it can be used to bridge any
intelligent device and NAND gate based nonvolatile memory through programmable logic
device.
In accordance with second aspect of present invention, it abstracts serial memory
access requirements from the data processing device.
In accordance with another aspect of present invention, it generates serial timing
cycles to read or write the memory device.
In accordance with yet another aspect of present invention, it abstracts erase
operation sequences from data processing device and generates appropriate signals.
Annexure‐ II
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent
and descriptive in the description when considered together with figures/flow charts
presented:
Fig. 1 is a representation of signal interface for a NAND gate based nonvolatile
memory device
Fig. 2 is an event flow diagram for page data write process
Fig. 3 is an event flow diagram for page read process
DETAILED DESCRIPTION
Introduction:
NAND gate based nonvolatile memory devices are high density memory devices, which will
be used in large scale nonvolatile storage applications. Memory is organized into
pages and blocks. These type of devices requires a sequential process on
multiplexed lines to access data sequentially with appropriate data integrity (refer fig
1).
Digital-Interface:
Conventional data processing devices are equipped with digital blocks that are
capable to handle low speed general purpose random access memory devices.
Extending this functionality to access NAND gate based nonvolatile memory devices,
demands change of semiconductor level design aspects in data processing devices.
This involves high magnitude of technical and financial implications, which often not
viable as per the cost benefit analysis. It is, in this crunching scenario, a separate
digital fabric; external to the data processing device is needed to attain the required
functionality, with in the techno-commercial boundaries. In context to the availability
of hardware description languages and programming logic devices, this external
digital fabric could become a reality. In fact, it is the very essence of programming
logic devices to serve in these demanding situations.
The digital fabric acts as a bridge between data processing device and memory
device. The activities of this digital interface act for i) data read operation (refer fig
2), ii) data write operation (refer fig 3) and iii) Erase operation.

We Claim that:
1. The interface comprises,
- A programmable logic device hardware
- Configuration details in hardware description language
- electronic circuit elements
2. The interface as in claim 1, is capable of interfacing with any data processing device having memory access capability.
3. The interface as in claim 1, is capable of interfacing with any NAND gate based nonvolatile memory device.
4. The interface as in claim 2, is capable of generating device specific signals to the NAND gate based nonvolatile memory device, independent of data processing device and its operational frequency.
5. The interface as in claim 3, is capable of having flexible provisions to dynamic adaptation future changes in terms of signal duration and sensitivity.