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Non Planar Semiconductor Device Having Doped Sub Fin Region And Method To Fabricate Same
Abstract: Non planar semiconductor devices having doped sub fin regions and methods of fabricating non planar semiconductor devices having doped sub fin regions are described. For example a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins exposing protruding portions of each of the plurality of semiconductor fins above sub fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub fin regions of each of the plurality of semiconductor fins.
Notices, Deadlines & Correspondence
Patent Information
Applicants
INTEL CORPORATION
Inventors
1. GHANI, Tahir
2. LATIF, Salman
3. MUNASINGHE, Chanaka D.
Specification
WE CLAIM:
1. A method of fabricating a semiconductor structure, the method
comprising:
forming a plurality of semiconductor fins above a semiconductor substrate;
forming a solid state dopant source layer above the semiconductor substrate, conformal with the plurality of semiconductor fins;
forming a dielectric layer above the solid state dopant source layer;
recessing the dielectric layer and the solid state dopant source layer to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins; and
driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.
2. The method of claim 1, wherein forming the solid state dopant source layer comprises forming a borosilicate glass (BSG) layer.
3. The method of claim 1, wherein forming the solid state dopant source layer comprises forming a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
4. The method of claim 1, further comprising:
forming a gate electrode conformal with the protruding portions of each of the plurality of semiconductor fins; and
forming source and drain regions in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate electrode.
5. The method of claim 1, wherein driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins comprises forming a dopant concentration interface between each of the protruding portions and corresponding sub-fin regions of each of the plurality of semiconductor fins.
6. The method of claim 1, wherein forming the plurality of semiconductor fins above the semiconductor substrate comprises forming a plurality of single crystalline silicon fins continuous with a bulk single crystalline substrate.
7. A method of fabricating a semiconductor structure, the method
comprising:
forming first and second pluralities of semiconductor fins above a semiconductor substrate;
forming a P-type solid state dopant source layer above the semiconductor
substrate, on and conformal with the first plurality of semiconductor fins; forming a dielectric layer above the P-type solid state dopant source layer; planarizing the dielectric layer and the P-type solid state dopant source layer to expose a top surface of each of the first and second pluralities of semiconductor fins;
implanting N-type dopants into the second plurality of fins, but not into the first plurality of fins;
recessing the dielectric layer and the P-type solid state dopant source layer to approximately a same level below the top surface of each of the first and second pluralities of semiconductor fins, exposing protruding portions of each of the first and second pluralities of semiconductor fins above sub-fin regions of each of the first and second pluralities of semiconductor fins; and driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor fins but not the second plurality of semiconductor fins.
8. The method of claim 7, wherein forming the P-type solid state dopant
source layer comprises:
forming a global P-type solid state dopant source layer on and conformal with the first and second pluralities of semiconductor fins; and
removing the global P-type solid state dopant source layer from the second plurality of semiconductor fins but not the first plurality of semiconductor fins.
9. The method of claim 8, further comprising:
subsequent to removing the global P-type solid state dopant source layer from the second plurality of semiconductor fins but not the first plurality of semiconductor fins, forming a buffer dielectric layer on and conformal with the P-type solid state dopant source layer and on and with the second plurality of semiconductor fins.
10. The method of claim 7, wherein forming the P-type solid state dopant source layer comprises forming a borosilicate glass (BSG) layer.
11. The method of claim 7, further comprising:
forming an N-type gate electrode conformal with the protruding portions of each of the first plurality of semiconductor fins;
forming a P-type gate electrode conformal with the protruding portions of each of the second plurality of semiconductor fins; and
forming source and drain regions in the protruding portions of each of the first and second pluralities of semiconductor fins, on either side of the corresponding gate electrode.
12. The method of claim 7, wherein driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor fins comprises forming a dopant concentration interface between each of the protruding portions and corresponding sub-fin regions of each of the first plurality of semiconductor fins.
13. The method of claim 7, wherein forming the first and second pluralities of semiconductor fins above the semiconductor substrate comprises forming first and
second pluralities of single crystalline silicon fins continuous with a bulk single crystalline substrate.
14. A method of fabricating a semiconductor structure, the method
comprising:
forming first and second pluralities of semiconductor fins above a semiconductor substrate;
forming a P-type solid state dopant source layer above the semiconductor substrate, on and conformal with the first plurality of semiconductor fins;
forming an N-type solid state dopant source layer above the semiconductor substrate, on and conformal with the second plurality of semiconductor fins; forming a dielectric layer above the P-type solid state dopant source layer and above the N-type solid state dopant source layer;
recessing the dielectric layer, the P-type solid state dopant source layer and the N-type solid state dopant source layer to approximately a same level below a top surface of each of the first and second pluralities of semiconductor fins, exposing protruding portions of each of the first and second pluralities of semiconductor fins above sub-fin regions of each of the first and second pluralities of semiconductor fins;
driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor fins but not the second plurality of semiconductor fins; and
driving dopants from the N-type solid state dopant source layer into the sub-fin regions of each of the second plurality of semiconductor fins but not the first plurality of semiconductor fins.
15. The method of claim 14, wherein the driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor fins and the driving dopants from the N-type solid state dopant source layer into the sub-fin regions of each of the second plurality of semiconductor fins are performed in a same process operation.
16. The method of claim 14, wherein forming the P-type solid state dopant source layer comprises:
forming a global P-type solid state dopant source layer on and conformal with the first and second pluralities of semiconductor fins; and
removing the global P-type solid state dopant source layer from the second plurality of semiconductor fins but not the first plurality of semiconductor fins.
17. The method of claim 16, further comprising:
subsequent to removing the global P-type solid state dopant source layer from the second plurality of semiconductor fins, forming a buffer dielectric layer on and conformal with the P-type solid state dopant source layer.
18. The method of claim 14, wherein forming the N-type solid state dopant
source layer comprises:
forming a global N-type solid state dopant source layer on and conformal with the second plurality of semiconductor fins and above the P-type solid state dopant source layer; and
removing the global N-type solid state dopant source layer from above the P- type solid state dopant source layer but not from the second plurality of semiconductor fins.
19. The method of claim 18, further comprising:
subsequent to removing the global N-type solid state dopant source layer from above the P-type solid state dopant source layer, forming a buffer dielectric
layer on and conformal with the N-type solid state dopant source layer and on and conformal with the P-type solid state dopant source layer.
20. The method of claim 14, wherein forming the P-type solid state dopant source layer comprises forming a borosilicate glass (BSG) layer, and wherein forming the N-type solid state dopant source layer comprises forming a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
21. The method of claim 14, further comprising:
forming an N-type gate electrode conformal with the protruding portions of each of the first plurality of semiconductor fins;
forming a P-type gate electrode conformal with the protruding portions of each of the second plurality of semiconductor fins; and
forming source and drain regions in the protruding portions of each of the first and second pluralities of semiconductor fins, on either side of the corresponding gate electrode.
22. The method of claim 14, wherein driving dopants from the P-type solid
state dopant source layer into the sub-fin regions of each of the first plurality of
semiconductor fins comprises forming a dopant concentration interface between
each of the protruding portions and corresponding sub-fin regions of each of the
first plurality of semiconductor fins, and wherein driving dopants from the N-type
solid state dopant source layer into the sub-fin regions of each of the second
plurality of semiconductor fins comprises forming a dopant concentration
interface between each of the protruding portions and corresponding sub-fin
regions of each of the second plurality of semiconductor fins.
23. The method of claim 14, wherein forming the first and second
pluralities of semiconductor fins above the semiconductor substrate comprises
forming first and second pluralities of single crystalline silicon fins continuous
with a bulk single crystalline substrate.
24. A semiconductor structure, comprising:
a plurality of semiconductor fins disposed above a semiconductor substrate;
a solid state dopant source layer disposed above the semiconductor substrate, conformal with sub-fin regions of each of the plurality of semiconductor fins but only to a level below a top surface of the plurality of semiconductor fins,
exposing protruding portions of each of the plurality of semiconductor fins above the sub-fin regions of each of the plurality of semiconductor fins;
a dielectric layer disposed above the solid state dopant source layer, the dielectric layer having a top surface approximately co-planar with the level below the top surface of the plurality of semiconductor fins; and
a dopant concentration interface between each of the protruding portions and corresponding sub-fin regions of each of the plurality of semiconductor fins.
25. The semiconductor structure of claim 24, wherein the solid state dopant source layer is a borosilicate glass (BSG) layer.
26. The semiconductor structure of claim 24, wherein the solid state dopant source layer is a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.
27. The semiconductor structure of claim 24, further comprising:
a gate electrode disposed conformal with the protruding portions of each of the plurality of semiconductor fins; and
source and drain regions disposed in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate electrode.
28. The semiconductor structure of claim 24, wherein the plurality of
semiconductor fins disposed above the semiconductor substrate is a
plurality of single crystalline silicon fins continuous with a bulk single crystalline substrate.
29. The semiconductor structure of claim 24, wherein the dopant concentration interface is an abrupt transition of less than approximately 5E17 atoms/cm3 for each of the protruding portions and of greater than approximately 2E18 atoms/cm3 for the corresponding sub-fin regions of each of the plurality of semiconductor fins.
30. An integrated circuit structure, comprising:
a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion;
a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion;
a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin;
a layer comprising a borosilicate glass (BSG), the layer comprising the BSG directly on sidewalls of the lower fin portion of the second fin, wherein an end of the layer comprising the BSG is in contact with an end of the layer comprising the PSG at a location between the first fin and the second fin;
a first insulating layer comprising nitrogen, the first insulating layer directly on the layer comprising the BSG directly on the sidewalls of the lower fin portion of the second fin;
a second insulating layer comprising nitrogen, the second insulating layer directly on the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin, the second insulating layer over the first insulating layer directly on the layer comprising the BSG directly on the sidewalls of the lower fin portion of the second fin;
a dielectric fill material directly on the second insulating layer directly on the layer comprising the PSG directly on the sidewalls of the lower fin portion of the first fin, the dielectric fill material directly on the second insulating layer over the first insulating layer directly on the layer comprising the BSG directly on the sidewalls of the lower fin portion of the second fin, wherein the dielectric fill material comprises silicon and oxygen;
a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over the dielectric fill material; and
a second gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, the second gate electrode over the dielectric fill material.
31. The integrated circuit structure of claim 30, wherein the end of the layer comprising the BSG is a terminating end, and the end of the layer comprising the PSG is a terminating end.
32. The integrated circuit structure of claim 31, wherein the terminating end of the layer comprising the BSG and the terminating end of the layer comprising the PSG meet at an approximately vertical interface between the terminating end of the layer comprising the BSG and the terminating end of the layer comprising the PSG.
33. The integrated circuit structure of claim 30, further comprising:
a first gate dielectric layer between the first gate electrode and the upper fin portion of the first fin; and
a second gate dielectric layer between the second gate electrode and the upper fin portion of the second fin.
34. The integrated circuit structure of claim 33, wherein the first gate dielectric layer comprises a first high-k dielectric layer, and wherein the second gate dielectric layer comprises a second high-k dielectric layer.
35. The integrated circuit structure of claim 30, wherein the lower fin portion of the first fin has a phosphorous concentration greater than approximately 2E18 atoms/cm3.
36. The integrated circuit structure of claim 30, wherein the upper fin portion of the first fin has a phosphorous concentration less than approximately 5E17 atoms/cm3.
37. The integrated circuit structure of claim 30, wherein the lower fin portion of the first fin has a phosphorous concentration greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the first fin has a phosphorous concentration less than approximately 5E17 atoms/cm3.
38. The integrated circuit structure of claim 30, wherein the lower fin portion of the second fin has a boron concentration greater than approximately 2E18 atoms/cm3.
39. The integrated circuit structure of claim 30, wherein the upper fin portion of the second fin has a boron concentration less than approximately 5E17 atoms/cm3.
40. The integrated circuit structure of claim 30, wherein the lower fin portion of the second fin has a boron concentration greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the second fin has a boron concentration less than approximately 5E17 atoms/cm3.
41. An integrated circuit structure, comprising:
a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion;
a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion;
a first dielectric layer comprising an N-type dopant, the first dielectric layer directly on sidewalls of the lower fin portion of the first fin;
a second dielectric layer comprising a P-type dopant, the second dielectric layer directly on sidewalls of the lower fin portion of the second fin, wherein an end of the second dielectric layer is in contact with an end of the first dielectric layer at a location between the first fin and the second fin;
a first insulating layer comprising nitrogen, the first insulating layer directly on the second dielectric layer directly on the sidewalls of the lower fin portion of the second fin;
a second insulating layer comprising nitrogen, the second insulating layer directly on the first dielectric layer directly on sidewalls of the lower fin portion of the first fin, the second insulating layer over the first insulating layer directly on the second dielectric layer directly on the sidewalls of the lower fin portion of the second fin;
a dielectric fill material directly on the second insulating layer directly on the first dielectric layer directly on the sidewalls of the lower fin portion of the first fin, the dielectric fill material directly on the second insulating layer over the first insulating layer directly on the second dielectric layer directly on the sidewalls of the lower fin portion of the second fin, wherein the dielectric fill material comprises silicon and oxygen;
a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over the dielectric fill material; and
a second gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, the second gate electrode over the dielectric fill material.
42. The integrated circuit structure of claim 41, wherein the N-type dopant is phosphorous.
43. The integrated circuit structure of claim 41, wherein the N-type dopant is arsenic.
44. The integrated circuit structure of claim 41, wherein the P-type dopant is boron.
45. The integrated circuit structure of claim 41, wherein the end of the second dielectric layer is a terminating end, and the end of the first dielectric layer is a terminating end.
46. The integrated circuit structure of claim 45, wherein the terminating end of the second dielectric layer and the terminating end of the first dielectric layer meet at an approximately vertical interface between the terminating end of the second dielectric layer and the terminating end of the first dielectric layer.
47. The integrated circuit structure of claim 41, further comprising:
a first gate dielectric layer between the first gate electrode and the upper fin portion of the first fin; and
a second gate dielectric layer between the second gate electrode and the upper fin portion of the second fin.
48. The integrated circuit structure of claim 47, wherein the first gate dielectric layer comprises a first high-k dielectric layer, and wherein the second gate dielectric layer comprises a second high-k dielectric layer.
49. The integrated circuit structure of claim 41, wherein the lower fin portion of the first fin has a concentration of the N-type dopant of greater than approximately 2E18 atoms/cm3.
50. The integrated circuit structure of claim 41, wherein the upper fin portion of the first fin has a concentration of the N-type dopant of less than approximately 5E17 atoms/cm3.
51. The integrated circuit structure of claim 41, wherein the lower fin portion of the first fin has a concentration of the N-type dopant of greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the first fin has a concentration of the N-type dopant of less than approximately 5E17 atoms/cm3.
52. The integrated circuit structure of claim 41, wherein the lower fin portion of the second fin has a concentration of the P-type dopant of greater than approximately 2E18 atoms/cm3.
53. The integrated circuit structure of claim 41, wherein the upper fin portion of the second fin has a concentration of the P-type dopant of less than approximately 5E17 atoms/cm3.
54. The integrated circuit structure of claim 41, wherein the lower fin portion of the second fin has a concentration of the P-type dopant of greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the second fin has a concentration of the P-type dopant of less than approximately 5E17 atoms/cm3
Documents
Orders
| Section | Controller | Decision Date |
|---|---|---|
Application Documents
| # | Name | Date |
|---|---|---|
| 1 | 6966-CHENP-2015-IntimationOfGrant26-12-2023.pdf | 2023-12-26 |
| 1 | Drawing [10-11-2015(online)].pdf | 2015-11-10 |
| 2 | 6966-CHENP-2015-PatentCertificate26-12-2023.pdf | 2023-12-26 |
| 2 | Description(Complete) [10-11-2015(online)].pdf | 2015-11-10 |
| 3 | 6966-CHENP-2015.pdf | 2015-11-13 |
| 3 | 6966-CHENP-2015-Annexure [22-12-2023(online)].pdf | 2023-12-22 |
| 4 | abstract 6966-CHENP-2015 .jpg | 2016-08-24 |
| 4 | 6966-CHENP-2015-PETITION UNDER RULE 137 [22-12-2023(online)].pdf | 2023-12-22 |
| 5 | Other Patent Document [24-03-2017(online)].pdf | 2017-03-24 |
| 5 | 6966-CHENP-2015-Proof of Right [22-12-2023(online)].pdf | 2023-12-22 |
| 6 | Marked Copy [27-03-2017(online)].pdf | 2017-03-27 |
| 6 | 6966-CHENP-2015-Written submissions and relevant documents [22-12-2023(online)].pdf | 2023-12-22 |
| 7 | Form 13 [27-03-2017(online)].pdf | 2017-03-27 |
| 7 | 6966-CHENP-2015-Correspondence to notify the Controller [02-11-2023(online)].pdf | 2023-11-02 |
| 8 | Description(Complete) [27-03-2017(online)].pdf_600.pdf | 2017-03-27 |
| 8 | 6966-CHENP-2015-US(14)-HearingNotice-(HearingDate-11-12-2023).pdf | 2023-10-31 |
| 9 | 6966-CHENP-2015-8(i)-Substitution-Change Of Applicant - Form 6 [15-12-2022(online)].pdf | 2022-12-15 |
| 9 | Description(Complete) [27-03-2017(online)].pdf | 2017-03-27 |
| 10 | 6966-CHENP-2015-ASSIGNMENT DOCUMENTS [15-12-2022(online)].pdf | 2022-12-15 |
| 10 | Form 26 [10-04-2017(online)].pdf | 2017-04-10 |
| 11 | 6966-CHENP-2015-PA [15-12-2022(online)].pdf | 2022-12-15 |
| 11 | Correspondence By Agent_Power Of Attorney_13-04-2017.pdf | 2017-04-13 |
| 12 | 6966-CHENP-2015-CLAIMS [30-09-2020(online)].pdf | 2020-09-30 |
| 12 | Form 18 [19-05-2017(online)].pdf | 2017-05-19 |
| 13 | 6966-CHENP-2015-FER_SER_REPLY [30-09-2020(online)].pdf | 2020-09-30 |
| 13 | 6966-CHENP-2015-RELEVANT DOCUMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 14 | 6966-CHENP-2015-FORM 3 [30-09-2020(online)].pdf | 2020-09-30 |
| 14 | 6966-CHENP-2015-MARKED COPIES OF AMENDEMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 15 | 6966-CHENP-2015-FORM 13 [26-03-2019(online)].pdf | 2019-03-26 |
| 15 | 6966-CHENP-2015-Information under section 8(2) [30-09-2020(online)].pdf | 2020-09-30 |
| 16 | 6966-CHENP-2015-Annexure [26-03-2019(online)].pdf | 2019-03-26 |
| 16 | 6966-CHENP-2015-OTHERS [30-09-2020(online)].pdf | 2020-09-30 |
| 17 | 6966-CHENP-2015-PETITION UNDER RULE 137 [30-09-2020(online)].pdf | 2020-09-30 |
| 17 | 6966-CHENP-2015-AMMENDED DOCUMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 18 | 6966-CHENP-2015-FER.pdf | 2020-04-23 |
| 18 | 6966-CHENP-2015-Response to office action [30-09-2020(online)].pdf | 2020-09-30 |
| 19 | 6966-CHENP-2015-FER.pdf | 2020-04-23 |
| 19 | 6966-CHENP-2015-Response to office action [30-09-2020(online)].pdf | 2020-09-30 |
| 20 | 6966-CHENP-2015-AMMENDED DOCUMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 20 | 6966-CHENP-2015-PETITION UNDER RULE 137 [30-09-2020(online)].pdf | 2020-09-30 |
| 21 | 6966-CHENP-2015-Annexure [26-03-2019(online)].pdf | 2019-03-26 |
| 21 | 6966-CHENP-2015-OTHERS [30-09-2020(online)].pdf | 2020-09-30 |
| 22 | 6966-CHENP-2015-FORM 13 [26-03-2019(online)].pdf | 2019-03-26 |
| 22 | 6966-CHENP-2015-Information under section 8(2) [30-09-2020(online)].pdf | 2020-09-30 |
| 23 | 6966-CHENP-2015-MARKED COPIES OF AMENDEMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 23 | 6966-CHENP-2015-FORM 3 [30-09-2020(online)].pdf | 2020-09-30 |
| 24 | 6966-CHENP-2015-FER_SER_REPLY [30-09-2020(online)].pdf | 2020-09-30 |
| 24 | 6966-CHENP-2015-RELEVANT DOCUMENTS [26-03-2019(online)].pdf | 2019-03-26 |
| 25 | 6966-CHENP-2015-CLAIMS [30-09-2020(online)].pdf | 2020-09-30 |
| 25 | Form 18 [19-05-2017(online)].pdf | 2017-05-19 |
| 26 | 6966-CHENP-2015-PA [15-12-2022(online)].pdf | 2022-12-15 |
| 26 | Correspondence By Agent_Power Of Attorney_13-04-2017.pdf | 2017-04-13 |
| 27 | 6966-CHENP-2015-ASSIGNMENT DOCUMENTS [15-12-2022(online)].pdf | 2022-12-15 |
| 27 | Form 26 [10-04-2017(online)].pdf | 2017-04-10 |
| 28 | 6966-CHENP-2015-8(i)-Substitution-Change Of Applicant - Form 6 [15-12-2022(online)].pdf | 2022-12-15 |
| 28 | Description(Complete) [27-03-2017(online)].pdf | 2017-03-27 |
| 29 | 6966-CHENP-2015-US(14)-HearingNotice-(HearingDate-11-12-2023).pdf | 2023-10-31 |
| 29 | Description(Complete) [27-03-2017(online)].pdf_600.pdf | 2017-03-27 |
| 30 | Form 13 [27-03-2017(online)].pdf | 2017-03-27 |
| 30 | 6966-CHENP-2015-Correspondence to notify the Controller [02-11-2023(online)].pdf | 2023-11-02 |
| 31 | Marked Copy [27-03-2017(online)].pdf | 2017-03-27 |
| 31 | 6966-CHENP-2015-Written submissions and relevant documents [22-12-2023(online)].pdf | 2023-12-22 |
| 32 | Other Patent Document [24-03-2017(online)].pdf | 2017-03-24 |
| 32 | 6966-CHENP-2015-Proof of Right [22-12-2023(online)].pdf | 2023-12-22 |
| 33 | abstract 6966-CHENP-2015 .jpg | 2016-08-24 |
| 33 | 6966-CHENP-2015-PETITION UNDER RULE 137 [22-12-2023(online)].pdf | 2023-12-22 |
| 34 | 6966-CHENP-2015.pdf | 2015-11-13 |
| 34 | 6966-CHENP-2015-Annexure [22-12-2023(online)].pdf | 2023-12-22 |
| 35 | Description(Complete) [10-11-2015(online)].pdf | 2015-11-10 |
| 35 | 6966-CHENP-2015-PatentCertificate26-12-2023.pdf | 2023-12-26 |
| 36 | 6966-CHENP-2015-IntimationOfGrant26-12-2023.pdf | 2023-12-26 |
| 36 | Drawing [10-11-2015(online)].pdf | 2015-11-10 |
Search Strategy
| 1 | 2020-03-1815-55-28E_18-03-2020.pdf |