DESCRIPTION NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND NONVOLATILE SEMICONDUCTOR APPARATUS USING THE NONVOLATILE MEMORY ELEMENT TECHNICAL FIELD [0001] The present invention relates to a nonvolatile memory element. More particularly, the present invention relates to a resistance variable nonvolatile memory element whose resistance value varies according to an applied electric signal, a manufacturing method thereof, and a nonvolatile semiconductor apparatus using the nonvolatile memory element. BACKGROUND ART [0002] In recent years, with the advancement of digital technologies, higher functionality of electronic hardware such as portable information devices and information appliances have been provided. Therefore, demands for an increase in a capacity of a nonvolatile memory element, reduction in a writing power in the memory element, reduction in write/readout time of the memory element, and longer life of the memory element have been increasing. [0003] It is said that, in response to these demands, miniaturization of an existing flash memory using a floating gate has a limitation. Accordingly, a novel resistance variable nonvolatile memory element using a resistance variable layer as a component of a memory portion has recently attracted attention. This resistance variable nonvolatile memory element has fundamentally a very simple structure in which a resistance variable layer 504 is sandwiched between a lower electrode 503 and an upper electrode 505 as shown in Fig. 32. The resistance varies to a high-resistance state or a low-resistance state by only applying a predetermined electric pulse between the upper and lower electrodes. And, these different resistance states are made to correspond to numerical values to perform storing of data. Because of such simplicities in structure and operation, the resistance variable nonvolatile memory element is expected to attain further miniaturization and cost reduction. Furthermore, since there are some cases where the state transition between the high resistance and the low resistance occurs in order of 100ns or less, the resistance variable nonvolatile memory element has attracted attention from the viewpoint of a high-speed operation, and therefore a variety of proposals thereof have been made. For example, as disclosed in Patent Document 1, there is a resistance variable nonvolatile memory element in which metal ions are taken in and out of the resistance variable layer 504 by application of a voltage to the upper electrode and to the lower electrode, to produce a high-resistance state and a low-resistance state, to thereby store data. Further, as disclosed in Patent Document 2, a resistance variable memory (phase change memory) which changes a crystalline state of a resistance variable layer with an electric pulse to change the resistance state has also been known. In addition to the above, there have been many proposals relating to a resistance variable nonvolatile memory element using a metal oxide for the resistance variable layer 504. The resistance variable memory element using a metal oxide is roughly classified into two types depending on the material used for the resistance variable layer. One is a resistance variable nonvolatile memory element using, as a resistance variable layer, a perovskite material (Pr(1-x)CaXMnO3 (PCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO)) which is disclosed in Patent Document 3 etc.. The other is a resistance variable nonvolatile memory element using a binary transition metal oxide. Since the binary transition metal oxide is very simple in composition and structure as compared to the above identified perovskite material, composition control therefor and film formation using them during manufacturing are relatively easy. In addition, the binary transition metal oxide has an advantage that its compatibility with a semiconductor manufacturing process is relatively favorable. Therefore, the binary transition metal oxide has been intensely studied in recent years. For example, Patent Document 4 and Non-patent Document 1 disclose NiO, V2O5, ZnO, Nb2O5, TiO2, WO3, and CoO as resistance variable materials. Further, Patent Document 5 discloses a resistance variable nonvolatile memory element using, as a variable-resistance material, a suboxide (oxide deviating from stoichiometric composition) of Ni, Ti, Hf, Nb, Zn, W, or Co, etc. Further, Patent Document 6 and Non-patent Document 2 disclose examples where a structure obtained by oxidizing the surface of TiN to form a TiO2 crystalline film in nm order is used for the resistance variable layer. [0004] In addition to the above, Patent Document 7 discloses a so-called one time programmable memory which uses titanium oxide and tantalum oxide (Ta2O5) as resistance variable materials and is capable of writing only once. Patent Document 1: Japanese Laid-Open Patent Application Publication No.2006-40946 Patent Document 2: Japanese Laid-Open Patent Application Publication No.2004-349689 Patent Document 3: U.S.Patent No.6473332 Patent Document 4: Japanese Laid-Open Patent Application Publication No.2004-363604 Patent Document 5: Japanese Laid-Open Patent Application Publication No.2005-317976 Patent Document 6: Japanese Laid-Open Patent Application Publication No.2007-180202 Patent Document 7: Japanese Laid-Open Patent Application Publication No. Hei. 7-263647 Non-patent Document 1: I.G.Beak et al., Tech. Digest IEDM 2004, p587 Non-patent Document 2: Japanese Journal of Applied Physics Vol.45, No.11, 2006, pp.L3 10-L312 DISCLOSURE OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION [0005] However, the nonvolatile memory elements using the above described transition metal oxides for the resistance variable layers have the following problems. [0006] First, in the conventional resistance variable nonvolatile memory element using the transition metal oxide such as NiO, the resistance variable material can be changed from the high-resistance state to the low-resistance state by a short electric pulse of about 100ns, as disclosed in Non-patent Document 1. However, since a long pulse in µs order is required for the resistance variable material to change from the low-resistance state to the high-resistance state, it is difficult to achieve high speed. Further, the resistance state does not change immediately after the structure having the variable resistance material sandwiched between the upper and lower electrodes is formed. That is, it is said that, in order to cause a change in the resistance state, a process of warming-up (hereinafter referred to as a forming process) which applies a special electric impulse between the upper and lower electrodes is required. Considering mass production of resistance variable memories, such forming process is far from desirable. This is because the forming process can be regarded as one manufacturing step, leading to increased cost and complicated manufacturing processes. As defined herein, the forming process is a process for changing the state of the resistance variable nonvolatile memory element immediately after being manufactured, by applying an electric pulse having a magnitude (voltage value) and a width (time) different from those of an electric pulse which enables steady change in the resistance state to take place. For example, supposing a case where, in order to operate a nonvolatile memory element having a potential capability of changing its resistance state with an electric pulse having a voltage of 2V and a width of 100ns, an electric pulse different from this electric pulse must be applied to the nonvolatile memory element immediately after being manufactured (e.g., application of electric pulse of 3V and 1µs ten times), this is expressed that the forming process is required. On the other hand, it is said that in the resistance variable memory having the structure obtained by oxidizing the surface of TiN to form microcrystalline TiO2 (TiO2/TiN structure) which is disclosed in Patent Document 6 and Non-patent Document 2, the forming process is dispensed with. It is said that in this memory, however, the TiO2 forms an aggregate of nanometer-order microcrystal (hereinafter referred to as nanocrystal), and the state of resistance variations depending on the size of this crystal. Generally, the size and crystalline structure of the nanocrystal are highly sensitive to the manufacturing method (it is formed by oxidation in the above), which may lead to significant variations in manufacturing. That is, it is not desirable to use the nanocrystal for the resistance variable layer because the nanocrystal tends to cause variations in the state of resistance variation. [0007] Furthermore, in a case where the transition metal oxide made of Ta2O5 which is disclosed in Patent Document 7 is used as a major component, it serves as an anti-fuse which can be used for only one operation from the high-resistance state to the low-resistance state, and therefore, rewriting cannot be performed. That is, since the resistance state is changed by insulation breakdown of the transition metal oxide in this case, the transition metal oxide which has once been changed to the low-resistance state cannot be restored to the high-resistance state. [0008] The present invention is made in view of the circumstances, and an object of the present invention is to provide a nonvolatile memory element which operates without a need for a forming process, and has high-speed and reversibly-stable rewrite characteristics and desirable resistance value retention characteristics, a manufacturing method of the nonvolatile memory element, which has high affinity with a semiconductor manufacturing process, and a nonvolatile semiconductor apparatus using the nonvolatile memory element. MEANS FOR SOLVING THE PROBLEMS [0009] With a view to achieving the above described objective, a nonvolatile memory element comprises a first electrode; a second electrode; and a resistance variable layer which is disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes; wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. The resistance variable layer may have a layered structure in which at least two layers of a first oxygen-deficient tantalum oxide layer having a composition represented by TaOx (0 < x < 2.5) and a second oxygen-deficient tantalum oxide layer having a composition represented by TaOy (x < y < 2.5) are stacked, and the first oxygen-deficient tantalum oxide layer being the first region and the second oxygen-deficient tantalum oxide layer being the second region. [0010] The second oxygen-deficient tantalum oxide layer may be in contact with the first electrode or the second electrode. [0011] When a resistance value between the first electrode and the second electrode after application of an electric pulse having an electric potential higher than an electric potential of the electrode with which the second oxygen-deficient tantalum oxide layer is not in contact to the electrode with which the second oxygen-deficient tantalum oxide layer is in contact is RH, and a resistance value between the first electrode and the second electrode after application of an electric pulse having an electric potential lower than an electric potential of the electrode with which the second oxygen-deficient tantalum oxide layer is not in contact to the electrode with which the second oxygen-deficient tantalum oxide layer is in contact is RL, RH > RL may be satisfied. [0012] It is preferable that the TaOx satisfies 0.8 ? x ? 1.9. [0013] It is preferable that the TaOy satisfies 2.1 ? y < 2.5. [0014] It is preferable that the second oxygen-deficient tantalum oxide layer has a thickness smaller than a thickness of the first oxygen-deficient tantalum oxide layer. [0015] It is preferable that the second oxygen-deficient tantalum oxide layer has a thickness that is not smaller than 1nm and not larger than 8nm. [0016] A nonvolatile semiconductor apparatus of the present invention comprises a semiconductor substrate: and a memory array including; a plurality of first electrode wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of second electrode wires formed above the plurality of first electrode wires so as to extend in parallel with each other within a plane parallel to a main surface of the semiconductor substrate and so as to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires; wherein each of the nonvolatile memory elements includes, when the first electrode wire is a first electrode and the second electrode wire is a second electrode, a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the first electrode and the second electrode; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. A nonvolatile semiconductor apparatus of the present invention comprises a semiconductor substrate: and a memory array including; a plurality of first electrode wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of second electrode wires formed above the plurality of first electrode wires so as to extend in parallel with each other within a plane parallel to a main surface of the semiconductor substrate and so as to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires; wherein each of the nonvolatile memory elements includes a first electrode connected to the first electrode wire, a second electrode connected to the second electrode wire, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the first electrode and the second electrode; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. Each of the nonvolatile memory elements may includes a current restricting element between the first electrode and the second electrode, and the current restricting element is electrically connected to the resistance variable layer. [0017] The nonvolatile semiconductor apparatus may further comprise a multi-layer memory array including a plurality of memory arrays which are stacked to form a layered structure. [0018] A nonvolatile semiconductor apparatus of the present invention comprises a semiconductor substrate; a plurality of word lines and a plurality of bit lines which are formed on the semiconductor substrate and are arranged to cross each other; a plurality of transistors provided to respectively correspond to intersections of the plurality of word lines and the plurality of bit lines; and a plurality of nonvolatile memory elements provided to respectively correspond to the plurality of transistors; wherein each of the nonvolatile memory elements includes a first electrode, a second electrode, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the first electrode and the second electrode via an associated one of the transistors; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [0019] A nonvolatile semiconductor apparatus of the present invention comprises a semiconductor substrate; a logic circuit formed on the semiconductor substrate and configured to execute predetermined calculation; and a nonvolatile memory element formed on the semiconductor substrate and having a programming function; wherein the nonvolatile memory element includes a first electrode, a second electrode, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the electrodes; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [0020] The nonvolatile semiconductor apparatus may further comprise another specific nonvolatile semiconductor apparatus. [0021] A method of manufacturing a nonvolatile memory element of the present invention including a first electrode; a second electrode; and a resistance variable layer which is disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes, said method comprising a step of manufacturing the resistance variable layer including (A) a step of forming a first region forming a part of the resistance variable layer in a thickness direction thereof and comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and (B) a step of forming a second region which is disposed adjacent the first region in the thickness direction of the resistance variable layer, and comprises a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5). [0022] The step A may be a step of forming a first layer comprising the first oxygen-deficient tantalum oxide, and the step B may be a step of oxidizing a surface of the first layer to form the first region and the second region. As used herein, the phrase “second region disposed adjacent the first region” means both of a configuration in which the first region and the second region are in contact with each other and a configuration in which another region exists between the first region and the second region. [0023] The step A may be a step of forming a first layer which is the first region comprising the first oxygen-deficient tantalum oxide, and the step B may be a step of depositing on the first layer a second layer which is the second region comprising the second oxygen-deficient tantalum oxide. [0024] The first layer may be formed by a sputtering process or a chemical vapor deposition process. [0025] The second layer may be formed by a sputtering process or a chemical vapor deposition process. [0026] The second layer may have a thickness that is not smaller than 1nm and not larger than 8nm. Foregoing object, other object, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments with reference to accompanying drawings. EFFECTS OF THE INVENTION [0027] According to the present invention, it is possible to attain a nonvolatile memory element which is capable of performing a high-speed operation and has reversibly-stable rewrite characteristics and desirable resistance value retention characteristics without a need for a forming process, a method of manufacturing the nonvolatile memory element, which has a high affinity with a semiconductor manufacturing process, and a nonvolatile semiconductor apparatus using the nonvolatile memory element. BRIEF DESCRIPTION OF THE DRAWINGS [0028] [Fig. 1] Fig. 1 is a cross-sectional view showing an example of a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 2] Figs. 2(a) to 2(c) are cross-sectional views showing steps for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 3] Fig. 3 is a view showing an example of operation of Examples 1 to 3 of the nonvolatile memory element according to Embodiment 1 of the present invention which occurs when reading out data; [Fig. 4] Fig. 4 is a view showing an example of operation of Examples 1 to 3 of the nonvolatile memory element according to Embodiment 1 of the present invention which occurs when writing data; [Fig. 5] Figs. 5(a) to 5(c) are views showing the relation between a resistance value of a resistance variable layer included in the nonvolatile memory element according to Embodiment 1 of the present invention, and the number of times of pulse applications; [Fig. 6] Fig. 6 is a view showing an XRD (X-ray diffraction) spectrum of a resistance variable layer comprising a tantalum oxide according to Embodiment 1 of the present invention; [Fig. 7] Figs. 7(a) and 7(b) are views showing X-ray reflectivity spectra of the resistance variable layer comprising the tantalum oxide according to Embodiment 1 of the present invention; [Fig. 8] Figs. 8(a) to 8(c) are cross-sectional views showing configurations of modifications of the nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 9] Fig. 9 is a view showing the relation between the resistance value of the resistance variable layer included in the nonvolatile memory element according to Embodiment 1 of the present invention, and the number of times of pulse applications; [Fig. 10] Fig. 10 is a view showing the relation between the width of an electric pulse applied between electrodes and the resistance value of the resistance variable layer, in a case where the nonvolatile memory element according to Embodiment 1 of the present invention operates; [Fig. 11] Fig. 11 is a view showing a resistance varying characteristics of the resistance variable layer in a case where electric pulses having the same polarity are continuously applied between the electrodes in the nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 12] Fig. 12 is a view showing a resistance varying characteristic of the resistance variable layer in a case where positive and negative electric pulses are applied between the electrodes alternately and continuously 10000 times in the nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 13] Fig. 13 is a view showing Arrhenius plots with respect to the nonvolatile memory element according to Embodiment 1 of the present invention; [Fig. 14] Figs. 14(a) to 14(c) are views showing the relation between the resistance value of a resistance variable layer included in a nonvolatile memory element according to Embodiment 2 of the present invention, and the number of times of pulse applications; [Fig. 15] Figs. 15(a) and 15(b) are a transmission electron microscope photograph and a sketch thereof at a cross section of Example 5 of the nonvolatile memory element according to Embodiment 2 of the present invention, respectively; [Fig. 16] Fig. 16 is a view showing the relation between an oxygen flow rate ratio during sputtering of a resistance variable layer comprising a tantalum oxide layer included in a nonvolatile memory element according to Embodiment 3 of the present invention, and an oxygen content rate in the tantalum oxide layer; [Fig. 17] Figs. 17(a) and 17(b) are views showing the relation between a resistance value of a resistance variable layer included in the nonvolatile memory element according to Embodiment 3 of the present invention, and the number of times of pulse applications; [Fig. 18] Figs. 18(a) to 18(c) are cross-sectional views showing configurations of modifications of the nonvolatile memory elements according to Embodiments 1 to 3 of the present invention; [Fig. 19] Fig. 19 is a block diagram showing a configuration of a nonvolatile semiconductor apparatus according to Embodiment 4 of the present invention; [Fig. 20] Fig. 20 is a perspective view showing a configuration of A part (configuration corresponding to four bits) in Fig. 19; [Fig. 21] Fig. 21 is a cross-sectional view showing a configuration of a nonvolatile memory element included in the nonvolatile semiconductor apparatus according to Embodiment 4 of the present invention; [Fig. 22] Figs. 22(a) to 22(g) are cross-sectional views showing configurations of modifications of the nonvolatile memory element included in the nonvolatile semiconductor apparatus according to Embodiment 4 of the present invention; [Fig. 23] Fig. 23 is a perspective view showing a configuration of a memory array included in a multi-layer structure nonvolatile semiconductor apparatus according to the present invention; [Fig. 24] Fig. 24 is a timing chart showing an example of an operation of the nonvolatile semiconductor apparatus according to Embodiment 4 of the present invention; [Fig. 25] Fig. 25 is a block diagram showing a configuration of a nonvolatile semiconductor apparatus according to Embodiment 5 of the present invention; [Fig. 26] Fig. 26 is a cross-sectional view showing a configuration of C part (configuration corresponding to two bits) in Fig. 25; [Fig. 27] Fig. 27 is a timing chart showing an example of an operation of the nonvolatile semiconductor apparatus according to Embodiment 5 of the present invention; [Fig. 28] Fig. 28 is a block diagram showing a configuration of a nonvolatile semiconductor apparatus according to Embodiment 6 of the present invention; [Fig. 29] Fig. 29 is a block diagram showing a configuration of a relief address storage register included in the nonvolatile semiconductor apparatus according to Embodiment 6 of the present invention; [Fig. 30] Fig. 30 is a cross-sectional view showing a configuration of the relief address storage register included in the nonvolatile semiconductor apparatus according to Embodiment 6 of the present invention; [Fig. 31] Fig. 31 is a flowchart showing a main flow of a process for manufacturing the nonvolatile semiconductor apparatus according to Embodiment 6 of the present invention; and [Fig. 32] Fig. 32 is a cross-sectional view showing a configuration of the conventional memory element. EXPLANATION OF REFERENCE NUMERALS [0029] 100 nonvolatile memory element 101 substrate 102 oxide layer 103 first electrode layer 104 first tantalum oxide layer 105 second tantalum oxide layer 106 resistance variable layer 107 second electrode layer 108 photoresist 109 element region 110 third tantalum oxide layer 200 nonvolatile semiconductor apparatus 201 memory main body 202 memory array 203 row selection circuit/driver 204 column selection circuit/driver 205 write circuit 206 sense amplifier 207 data input/output circuit 208 address input circuit 209 control circuit 210 nonvolatile memory element 211 upper wire 212 lower wire 213 upper electrode 214 resistance variable layer 215 inner electrode 216 current restricting element 217 lower electrode 218 ohmic resistance layer 219 second resistance variable layer 300 nonvolatile semiconductor apparatus 301 memory main body 302 memory array 303 row selection circuit/driver 304 column selection circuit 305 write circuit 306 sense amplifier 307 data input/output circuit 308 cell plate electric power supply 309 address input circuit 310 control circuit 313 nonvolatile memory element 314 upper electrode 315 resistance variable layer 316 lower electrode 400 nonvolatile semiconductor apparatus 401 semiconductor substrate 402 CPU 403 input/output circuit 404 logic circuit 405 analog circuit 406 BIST circuit 407 SRAM 408 relief address storage register 409 nonvolatile memory element 410 write circuit 411 readout circuit 412 latch circuit BL0, BL1, ... bit lines M11, M12, ... memory cells T11, T12, ... transistors WL0, WL1, ... word lines 500 nonvolatile memory element 501 substrate 502 oxide layer 503 lower electrode 504 resistance variable layer 505 upper electrode BEST MODE FOR CARRYING OUT THE INVENTION [0030] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the same reference numerals are used to identify the same or corresponding parts throughout the drawings, and description thereof may be in some cases omitted. [0031] (Embodiment 1) [Configuration of Nonvolatile Memory Element] Fig. 1 is a cross-sectional view showing an example of a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention. [0032] As shown in Fig. 1, a nonvolatile memory element 100 of this embodiment comprises a substrate 101, an oxide layer 102 formed on the substrate 101, a first electrode layer 103 formed on the oxide layer 102, a second electrode layer 107, and a resistance variable layer 106 sandwiched between the first electrode layer 103 and the second electrode layer 107. The resistance variable layer 106 comprises an oxygen-deficient tantalum oxide having a composition represented by TaOz (0 RL is satisfied. [5] The nonvolatile memory element according to any one of Claims 1 to 4, wherein the TaOx satisfies 0.8 ? x ? 1.9. [6] The nonvolatile memory element according to any one of Claims 1 to 4, wherein the TaOy satisfies 2.1 ? y < 2.5. [7] The nonvolatile memory element according to Claim 2 or 3, wherein the second oxygen-deficient tantalum oxide layer has a thickness smaller than a thickness of the first oxygen-deficient tantalum oxide layer. [8] The nonvolatile memory element according to any one of Claims 1 to 4, wherein the second oxygen-deficient tantalum oxide layer has a thickness that is not smaller than 1nm and not larger than 8nm. [9] A nonvolatile semiconductor apparatus comprising: a semiconductor substrate: and a memory array including: a plurality of first electrode wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of second electrode wires formed above the plurality of first electrode wires so as to extend in parallel with each other within a plane parallel to a main surface of the semiconductor substrate and so as to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires; wherein each of the nonvolatile memory elements includes, when the first electrode wire is a first electrode and the second electrode wire is a second electrode, a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the first electrode and the second electrode; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [10] A nonvolatile semiconductor apparatus comprising: a semiconductor substrate: and a memory array including: a plurality of first electrode wires formed on the semiconductor substrate to extend in parallel with each other; a plurality of second electrode wires formed above the plurality of first electrode wires so as to extend in parallel with each other within a plane parallel to a main surface of the semiconductor substrate and so as to three-dimensionally cross the plurality of first electrode wires; and nonvolatile memory elements provided to respectively correspond to three-dimensional cross points of the plurality of first electrode wires and the plurality of second electrode wires; wherein each of the nonvolatile memory elements includes a first electrode connected to the first electrode wire, a second electrode connected to the second electrode wire, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the first electrode and the second electrode; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [11] The nonvolatile semiconductor apparatus according to Claim 9 or 10, wherein each of the nonvolatile memory elements includes a current restricting element between the first electrode and the second electrode, and the current restricting element is electrically connected to the resistance variable layer. [12] The nonvolatile semiconductor apparatus according to Claim 9 or 10, further comprising: a multi-layer memory array including a plurality of memory arrays which are stacked to form a layered structure. [13] A nonvolatile semiconductor apparatus comprising: a semiconductor substrate; a plurality of word lines and a plurality of bit lines which are formed on the semiconductor substrate and are arranged to cross each other; a plurality of transistors provided to respectively correspond to intersections of the plurality of word lines and the plurality of bit lines; and a plurality of nonvolatile memory elements provided to respectively correspond to the plurality of transistors; wherein each of the nonvolatile memory elements includes a first electrode, a second electrode, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the first electrode and the second electrode via an associated one of the transistors; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [14] A nonvolatile semiconductor apparatus comprising: a semiconductor substrate; a logic circuit formed on the semiconductor substrate and configured to execute predetermined calculation; and a nonvolatile memory element formed on the semiconductor substrate and having a programming function; wherein the nonvolatile memory element includes a first electrode, a second electrode, and a resistance variable layer disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to a voltage applied between the electrodes; and wherein the resistance variable layer has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer. [15] The nonvolatile semiconductor apparatus according to Claim 14, further comprising: the nonvolatile semiconductor apparatus as recited in Claim 9, 10, or 13. [16] A method of manufacturing a nonvolatile memory element including a first electrode; a second electrode; and a resistance variable layer which is disposed between the first electrode and the second electrode, a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes, said method comprising: a step of manufacturing the resistance variable layer including (A) a step of forming a first region forming a part of the resistance variable layer in a thickness direction thereof and comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and (B) step of forming a second region which is disposed adjacent the first region in the thickness direction of the resistance variable layer, and comprises a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5). [17] The method of manufacturing a nonvolatile memory element according to Claim 16, wherein the step A is a step of forming a first layer comprising the first oxygen-deficient tantalum oxide, and the step B is a step of oxidizing a surface of the first layer to form the first region and the second region. [18] The method of manufacturing a nonvolatile memory element according to Claim 16, wherein the step A is a step of forming a first layer which is the first region comprising the first oxygen-deficient tantalum oxide, and the step B is a step of depositing on the first layer a second layer which is the second region comprising the second oxygen-deficient tantalum oxide. [19] The method of manufacturing a nonvolatile memory element according to Claim 17 or 18, wherein the first layer is formed by a sputtering process or a chemical vapor deposition process. [20] The method of manufacturing a nonvolatile memory element according to Claim 19, wherein the second layer is formed by a sputtering process or a chemical vapor deposition process. [21] The method of manufacturing a nonvolatile memory element according to Claim 16, wherein the TaOx satisfies 0.8 ? x ? 1.9. [22] The method of manufacturing a nonvolatile memory element according to Claim 16, wherein the TaOy satisfies 2.1 ? y < 2.5. [23] The method of manufacturing a nonvolatile memory element according to Claim 18, wherein the second layer has a thickness that is not smaller than 1nm and not larger than 8nm. ABSTRACT A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0 < x < 2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x < y < 2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.