DESC:TECHNICAL FIELD
[001] The present disclosure generally relates to field plate high-electron-mobility transistor (HEMT) designs. More specifically, the present disclosure relates to drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.

BACKGROUND
[002] Background description includes information that can be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[003] Gallium Nitride high electron mobility transistors, owing to its high bandgap, find applications in fast switching power electronic circuits and high power RF amplifiers. The high critical electric field of 3 MVcm-1, in conjunction with polarization induced high 2D electron gas (2DEG) density causes low on-resistance (Ron), high on current (Ion) and high breakdown voltage (VBD). The most critical design aspect for a high power device is VBD - Ron trade-off, which for lateral power devices is given as Ron = , where ns is the channel electron concentration, µ is channel mobility and EC is the critical electric field of the material. It is imperative to design the HEMT with high breakdown voltage without compromising with on-resistance and it’s RF performance. Johnson’s Figure of merit given as JFOM = VBD × fT indicates that both breakdown voltage and cut-off frequency (fT) should be maximized simultaneously for a high power RF device.
[004] Field Plate technology is the most widely adopted technique for increasing the breakdown voltage in HEMT. There are several variations of the same reported in literature such as gate field plate, source-connected field plate and drain connected field plate. The recently developed tri-gate designs have shown high breakdown voltage by shaping the field profile at the contacts. However, these literature reports have used the lateral field plate configuration, which is ultimately limited by the drift region or gate to drain distance of the device (Lgd). The field plates result in uniform space-charge distribution in the lateral direction and thereby improves the breakdown voltage of the device. However, for high power RF applications, the field plate design is a critical aspect. The Miller capacitance induced by gate-connected field plate can be detrimental to the device switching performance. In this scenario, the drain connected field plate devices can provide better breakdown voltage- RF performance trade-off, maximizing the Johnson’s Figure of Merit. It is also important to discuss the feasibility of developed design for large-signal applications such as power amplifier. We have carried out extensive large signal and small signal analyses of the proposed designs and compared the performance with the conventional architectures. In order to achieve optimum performance, it is imperative to scale down the device without compromising the breakdown voltage. Multiple reports have suggested saturation of breakdown voltage as the field plate length exceeds a particular length. This issue becomes more severe as the device is scaled down in order to enhance the on-state performance.
[005] This translates to a narrower design window for field plate implementation, which requires more complex and precise lithography alignment. Particularly, in case of RF applications, where the design rules for the lateral device dimensions are rather stringent, the use of a lateral field plate becomes less feasible. In addition, as the device scales down, the contribution of the field plate induced parasitic miller capacitance begins to dominate, resulting in degradation in RF performance parameters such as power gain and cut-off frequency. All the above factors push for an innovative design architecture which can provide effective field distribution in scaled devices, without compromising with VBD - RON trade-off and RF PA performance.
[006] Efforts have been made in the prior art to realize effective and efficient solutions for the above-mentioned factors. But none have effectively addressed the aspect of drain connected field plate designs that improves breakdown performance of GaN based HEMT devices.
[007] Thus, there is a need in the art to provide a reliable and efficient drain connected field plate designs for improving breakdown performance of GaN based HEMT devices.
OBJECTS OF THE PRESENT DISCLOSURE
[008] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.
[009] It is an object of the present disclosure to provide drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[0010] It is another object of the present disclosure to provide a simple and effective drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[0011] It is another object of the present disclosure to provide a reliable and efficient drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[0012] It is another object of the present disclosure to provide a robust drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.

SUMMARY
[0013] The present disclosure generally relates to field plate high-electron-mobility transistor (HEMT) designs. More specifically, the present disclosure relates to drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[0014] In an aspect the present disclosure provides for a High Electron Mobility Transistor (HEMT) device for enhancing improvement in breakdown and RF performance. The device may include a semiconductor based HEMT stack, an etched mesa region extending through a semiconductor buffer layer of the HEMT stack. The semiconductor buffer layer may be disposed epitaxially on top of one or more nucleating layers. The device may further include a passivation layer of a predefined thickness which may be partially disposed in the etched mesa region, a drain contact disposed on the passivation layer and a first drain field plate at least partially covering the drain contact. The first drain field plate may be of a first predefined length which may extend vertically into the etched mesa region. The device upon application of a positive drain bias, the extension of the drain field plate into the mesa etched region causes delay in avalanche breakdown.
[0015] In an embodiment, the HEMT stack may further include a semiconductor substrate layer disposed below the one or more nucleating layers and a semiconductor channel layer may be disposed on the semiconductor buffer layer. In an embodiment, the semiconductor forming the substrate may be any Silicon Carbide, Silicon and Sapphire semiconductors. In another embodiment, the semiconductor buffer layer may include any or a combination of C-doped, unintentional doped and Fe-doped buffer layers.
[0016] In an embodiment, the HEMT stack may further include a semiconductor barrier layer disposed on top of a semiconductor channel layer and the semiconductor channel layer may be disposed on top of the semiconductor buffer layer. In an embodiment, the semiconductor barrier layer may include group III-V materials such as AlN, AlGaN and InAlN but not limited to the like. In another embodiment, the semiconductor barrier layer may be N-type doped having any or a combination of uniform, graded, Gaussian doping profile and the like.
[0017] In an embodiment, the passivation layer may cover at least a side surface of the semiconductor barrier layer to provide protection to the device. The passivation layer may include any GaN and any dielectric materials such as any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, SiON and the like.
[0018] In an embodiment a gate contact having a gate length may be deposited between a source contact and the drain contact and the source contact and the drain contact may be located at either side of the device. The source contact and the gate contact may be separated by a first predefined distance, and the gate contact and the drain contact may be separated by a second predefined distance.
[0019] In an embodiment, one or more transition layers may be disposed below the semiconductor buffer layer and above the substrate, and the one or more transition layers may be any or a combination of step graded, linearly graded and AlN interlayer type but not limited to the like.
[0020] In an embodiment, a second drain field plate may extend laterally from the drain contact towards the gate contact, and the second drain field plate may be of a second predefined length.
[0021] In an embodiment, the device may be designed with any or a combination of a source connected field plate connected with the source contact and a gate connected field plate connected with the gate contact.
[0022] In an aspect, the present disclosure provides for a method for designing a High Electron Mobility Transistor (HEMT) device for enhancing improvement for enhancing improvement in breakdown and RF performance. The method may include growing semiconductor based HEMT stack epitaxially, etching a mesa region in the HEMT stack, the etched mesa region may cause isolation of the device, depositing a passivation layer of a predefined thickness, the passivation layer may be partially disposed in the etched mesa region, depositing a drain contact on the passivation layer and depositing a first drain field plate at least partially covering the drain contact, the first drain field plate may be of a first predefined length, where the first drain field plate extends vertically into the mesa etched region.
[0023] In an embodiment, the method may further include depositing a second drain field plate extending laterally from the drain contact towards the gate contact, and the second drain field plate may be of a second predefined length.
[0024] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:
[0026] FIG. 1A illustrates a conventional HEMT device having a HEMT stack, in accordance with an embodiment of the present disclosure.
[0027] FIG. 1B illustrates GaN HEMT design with lateral drain connected field plate, in accordance with an embodiment of the present disclosure
[0028] FIG. 2 illustrates a proposed drain connected vertical field plate design showing the length of vertical field plate, in accordance with an embodiment of the present disclosure.
[0029] FIG. 3 illustrates a proposed drain connected dual field plate design showing the lengths of vertical and lateral field plate respectively, in accordance with an embodiment of the present disclosure.
[0030] FIG. 4 illustrates an exemplary flow diagram of the proposed method in accordance with an embodiment of the present disclosure.
[0031] FIGs. 5A-5D illustrates data associated with the calibration of IV and CV characteristics, in accordance with an embodiment of the present disclosure.
[0032] FIGs. 6A-6E illustrates data associated with the calibration of S-parameters and power amplifier simulation setup for the conventional and the proposed drain connected field plate design, in accordance with an embodiment of the present disclosure.
[0033] FIGs. 7A-7B illustrates data associated with the conventional lateral field plate and proposed drain connected field plate design with a particular emphasis on breakdown voltage, in accordance with an embodiment of the present disclosure.
[0034] FIGs. 8A-8H illustrates data associated with the proposed drain connected field plate design with the electrical field contours being shown, in accordance with an embodiment of the present disclosure.
[0035] FIG. 9 illustrates data associated with the proposed drain connected field plate design again showing a particular emphasis on breakdown voltage, in accordance with an embodiment of the present disclosure.
[0036] FIGs. 10A-10F illustrates data associated with the proposed drain connected field plate design showing a particular emphasis impact of buffer thickness and field plate lengths on breakdown voltage, in accordance with an embodiment of the present disclosure.
[0037] FIGs. 11A-11B illustrates data associated with the proposed drain connected field plate design showing a particular emphasis impact on comparative ON-resistance -breakdown voltage trade-off and ON current-breakdown voltage trade-off, in accordance with an embodiment of the present disclosure.
[0038] FIG. 12 illustrates data associated with the proposed drain connected field plate design with regards to a comparative power figure of merit (FOM) for various designs, in accordance with an embodiment of the present disclosure.
[0039] FIGs. 13A-13D illustrates data associated with the proposed drain connected field plate design again with regards to a comparative small signal RF figure of merit for various designs and with an emphasis on cut-off frequency (fT) and Miller capacitance, in accordance with an embodiment of the present disclosure.
[0040] FIG. 14A-14D illustrates data associated with the proposed drain connected field plate design again with regards to a comparative large signal figure of merit for various designs and with an emphasis on power output, drain efficiency and gain, in accordance with an embodiment of the present disclosure.
[0041] FIG. 15 illustrates an embodiment of the proposed design with varying vertical drain field plate length, in accordance with an embodiment of the present disclosure
[0042] FIG. 16 illustrates an embodiment of the proposed design with dual field plate design comprising of lateral field plate of length LFP-L and vertical drain field plate length LFP-V, in accordance with an embodiment of the present disclosure.
[0043] FIG. 17 illustrates an embodiment of the proposed design with dual field plate design comprising of lateral gate field plate, drain connected vertical drain field plate of length LFP-V, in accordance with an embodiment of the present disclosure.
[0044] FIG. 18 illustrates an embodiment of the proposed design comprising of lateral gate field plate and lateral drain connected field plate and vertical drain connected field plate, in accordance with an embodiment of the present disclosure.
[0045] FIG. 19 illustrates embodiment of the proposed design comprising of lateral source connected field plate and vertical drain connected field plate of length, in accordance with an embodiment of the present disclosure.
[0046] FIG. 20 illustrates an embodiment of the proposed design comprising of lateral source connected field plate and dual drain field plate, in accordance with an embodiment of the present disclosure.
[0047] FIG. 21 illustrates an embodiment of the proposed design comprising of lateral source connected field plate, gate connected field plate and vertical drain field plate, in accordance with an embodiment of the present disclosure.
[0048] FIG. 22 illustrates an embodiment of the proposed design comprising of lateral source connected field plate, gate connected field plate and dual drain field plate, in accordance with an embodiment of the present disclosure.
[0049] FIG. 23 illustrates a first step in the fabrication method for the proposed design showing an Epi-growth of HEMT stack, in accordance with an embodiment of the present disclosure.
[0050] FIG. 24 illustrates a second step in the fabrication method for the proposed design showing a Mesa formation, in accordance with an embodiment of the present disclosure.
[0051] FIG. 25 illustrates a third step in the fabrication method for the proposed design showing a dielectric deposition, in accordance with an embodiment of the present disclosure.
[0052] FIG. 26 illustrates a fourth step in the fabrication method for the proposed design showing an ohmic contact deposition, in accordance with an embodiment of the present disclosure.
[0053] FIG. 27 illustrates a fifth step in the fabrication method for the proposed design showing gate contact formation, in accordance with an embodiment of the present disclosure.
[0054] FIG. 28 illustrates a sixth step in the fabrication method for the proposed design showing drain connected dual field plate deposition, in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0055] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0056] The present disclosure generally relates to field plate high-electron-mobility transistor (HEMT) designs. More specifically, the present disclosure relates to drain connected field plate designs for improving breakdown performance of GaN based HEMT devices. Even more specifically, the present disclosure relates to drain connected field plate designs for improving breakdown performance, breakdown (VBD)-on-resistance (Ron) trade off of GaN based HEMT devices along the improvement in small signal and large signal performance of GaN based HEMT RF power amplifier.
[0057] FIG. 1A illustrates a conventional HEMT device having a HEMT stack. As illustrated, a conventional HEMT device (also referred to as conventional device hereinafter) can have a HEMT stack that may include a semiconductor substrate 102. The semiconductor substrate can be Silicon Carbide (referred to as SiC hereinafter)) substrate but not limited to the like. In another exemplary embodiment, the semiconductor substrate can be any semiconductor such as Silicon and Sapphire semiconductors and the like. The conventional device can include one or more nucleating layers 104 (collectively referred to as nucleating layers 104 and individually as nucleating layer 104) disposed above the semiconductor substrate 102. In an exemplary embodiment, the nucleating layer can be Aluminium Nitride (AlN). A semiconductor buffer layer 106 can be disposed on top of the nucleating layers 104. Further, a semiconductor channel layer 108 can be deposited on top of the semiconductor buffer layer 106. In an exemplary embodiment, the semiconductor channel layer 108 can be formed of but not limited to unintentional doping (also referred to as UID) GaN. Furthermore, the device can include a semiconductor barrier layer 112 (also referred to as barrier layer 112 herein) of predefined thickness disposed on top of the semiconductor channel layer 108. The semiconductor barrier layer 112 can be formed of group III-V materials such as any AlN, AlGaN and InAlN but not limited to the like. The deposition of the semiconductor barrier layer on top of the semiconductor channel layer can generate a two degree electron gas (also referred to as 2DEG hereinafter) sheet in the semiconductor channel layer 108 and at the interface of the semiconductor barrier layer 112 and can be configured as a 2DEG electron gas channel to conduct current between at least two ohmic contacts formed on or in the semiconductor channel layer. As illustrated, at least two ohmic contacts can include a source contact 116 and a drain contact 120 located on both sides of a gate contact 118 having a predefined gate length 130 (also referred to as Lg 130 herein). In yet another embodiment, the source contact 116 and the gate contact 118 can be separated by a first predefined distance 132 (also referred to as Lsg 132), and the gate contact 118 and the drain contact 120 can be separated by a second predefined distance 128 (also referred to as Lgd 128).
[0058] FIG. 1B illustrates GaN HEMT design with lateral drain connected field plate.
[0059] FIG. 2 illustrates a proposed drain connected vertical field plate design showing the length of vertical field plate. `As illustrated the HEMT device 100 (also referred to as device 100 hereinafter) may include the semiconductor based HEMT stack as depicted in FIG. 1. The device 100 may also include an etched mesa region 122 which may extend through a semiconductor buffer layer 106 of the HEMT stack. The semiconductor buffer layer 106 may be disposed epitaxially on top of one or more nucleating layers 104. The device 100 may also include a passivation layer 114. In an exemplary embodiment, the passivation layer 114 may be of a predefined thickness which may be partially disposed in the etched mesa region 122. Further a drain contact 120 may be disposed on the passivation layer 114 and a first drain field plate at least partially covering the drain contact 120. The first drain field plate may be of a first predefined length 124 (also referred to as LFP-V 124) and may extend vertically into the etched mesa region 122. In an exemplary embodiment, upon application of a positive drain bias, the extension of the drain field plate into the mesa etched region 122 may cause delay in avalanche breakdown.
[0060] In an embodiment, the mesa region 122 can be any or combination of SiO2, one or more dielectrics and one or more insulators but not limited to the like.
[0061] In an exemplary embodiment, the semiconductor forming the substrate 102 can be any Silicon Carbide, Silicon and Sapphire semiconductors. In another exemplary embodiment, the semiconductor buffer layer 106 may include any or a combination of C-doped, unintentional doped and Fe-doped buffer layers.
[0062] In an exemplary embodiment, the semiconductor barrier layer 112 can be any group III-V materials such as AlN, AlGaN, InAlN but not limited to the like. In another exemplary embodiment, the semiconductor barrier layer 112 may be N-type doped but not limited to it having any or a combination of uniform, graded, Gaussian doping profile and the like.
[0063] In an exemplary embodiment, the passivation layer 114 may cover at least a side surface of the semiconductor barrier layer 112. The passivation layer 114 may provide protection to the device 100. In another embodiment, the passivation layer 114 may include any GaN and any dielectric materials such as any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, SiON but not limited to the like.
[0064] In another embodiment, one or more transition layers may be disposed below the semiconductor buffer layer 106 and above the substrate 102. In yet another exemplary embodiment, the one or more transition layers may be any or a combination of step graded, linearly graded and AlN interlayer type but not limited to the like.
[0065] FIG. 3 illustrates a proposed drain connected dual field plate design showing the lengths of vertical and lateral field plate respectively, in accordance with an embodiment of the present disclosure. As illustrated, the device 100 may include a second drain field plate extending laterally from the drain contact 120 towards the gate contact 118. In an exemplary embodiment, the second drain field plate may be of a second predefined length 126 (also referred to as LFP-L 126).
[0066] In yet another embodiment, the device may be designed with any or a combination of a source connected field plate connected with the source contact 116 and a gate connected field plate connected with the gate contact 118.
[0067] FIG. 4 illustrates an exemplary flow diagram of the proposed method in accordance with an embodiment of the present disclosure.
[0068] In an aspect, the present disclosure provides for a method 400 for fabricating a High Electron Mobility Transistor (HEMT) device 100 for enhancing improvement in breakdown and RF performance. The method may include at 402, the step of growing semiconductor based HEMT stack epitaxially and at 404, the step of etching a mesa region 122 in the HEMT stack, where the etched mesa region 122 may cause isolation of the device.
[0069] The method 400 may further include at 406, the step of depositing a passivation layer 114 of a predefined thickness, where the passivation layer may be partially disposed in the etched mesa region 122 and at 408, the step of depositing a drain contact 120 on the passivation layer 114.
[0070] Furthermore, the method 400 may include at 410, the step of depositing a first drain field plate at least partially covering the drain contact 120, the first drain field plate having a first predefined length 124 extending vertically into the mesa etched region 122.
[0071] In an embodiment, the method may further include the step of depositing a second drain field plate extending laterally from the drain contact 120 towards the gate contact 118. In an exemplary embodiment, the second drain field plate may be of a second predefined length 126.
[0072] FIGs. 5A-5D illustrates data associated with the calibration of IV and CV characteristics, in accordance with an embodiment of the present disclosure. With regards to these figures, S11 and S22 extracted using TCAD and model, plotted together depicting a good match between TCAD and model. Referring to FIGs. 5A-5D, they show IV and CV calibration for (a) No field plate, (b) Lateral field plate, (c) Vertical field plate and (d) Dual field plate design. Load-pull setup consisting RF PA biased in class-AB operation is shown in Fig. 6E. S-parameter is extracted for the frequency range from 0.5 GHz to 10 GHz (Fig. 6A-D). For RF PA / load-pull simulations and S-parameter extraction using model, Keysight’s ADS suit was used.
[0073] FIGs. 6A-6E illustrates data associated with the proposed drain connected field plate design, in accordance with an embodiment of the present disclosure. FIGs.7A-7B illustrates data associated with the conventional and proposed drain connected field plate design with a particular emphasis on breakdown voltage scaling with gate to drain distance (Lgd), in accordance with an embodiment of the present disclosure. In particular, a breakdown as against Lgd scaling in addition to the limitations of the lateral field plate design. A clear roll-off in the breakdown voltage can be seen when field plate length was increased, which is severe for shorter Lgd values (FIG. 7(A)). This effect is mitigated as the drift region length is increased. FIGs.8A-8C show that with the increase in field plate length, the peak electric field peak shifts away from the drain contact and moves towards the gate. Improvement in breakdown voltage with an increase in field plate length, as depicted in FIG. 7A, is attributed to the relaxation of peak field and the resultant decrease in impact ionization rate as shown in FIG. 8D. However, as the field plate moves closer to the gate, the peak electric field at the gate edge increases significantly. The high impact ionization rates lead to enhanced carrier generation at the gate, leading to early breakdown of the device. This is a critical issue, as the lateral field plate designs do not yield any breakdown voltage improvement beyond certain field plate length. Hence the maximum breakdown voltage is limited by Lgd.
[0074] With regards to the proposed Vertical Field Plate Design: In case of vertical field plate design (FIG. 2), the breakdown voltage increases consistently as a function of field plate lengths as shown in FIG. 7B. FIGs. 8E-8G shows that vertical field plate acts as a parallel plate capacitor in conjunction with the buffer. With the application of positive drain bias, it depletes the localized region situated in the deep buffer. This additional space charge region provides additional voltage blocking capability to the device by re-distributing the electric field vertically into the buffer and not towards the gate. The impact ionization originates away from the channel and hence, delays the avalanche breakdown process. FIG. 7B shows a fall in breakdown voltage beyond a certain field plate depth. It is attributed to high electric field crowding across the etched buffer and substrate and resultant increase in impact ionization as depicted in FIG. 8G and FIG. 8H, respectively. It should be noted that the vertical field plate is as effective as lateral field plate and not limited by the drift region length, however, defined by the buffer thickness.
[0075] FIGs. 8A-8H illustrates data associated with the conventional lateral field plate and proposed drain connected field plate design with the electrical field contours being shown, in accordance with an embodiment of the present disclosure. In particular, electric field contours extracted for lateral field plate design with field plate length respectively as to the figures (a) LF P (L)= 0.5µm, (b) LF P (L)= 1µm, (c) LF P (L)= 1.5µm; for vertical field plate design and (e) LF P (V )= 0.5µm, (f) LF P (V )= 2µm and (g) LF P (V )= 3µm. The impact ionisation rates as function of field plate lengths are represented in (d) and (h) for lateral (cut along X-X’) and vertical field plates (cut along Y-Y’), respectively. Here Lgd is 3µm and tBuffer= 3µm. Drain voltage is 200V, applied in channel.
[0076] FIG. 9 illustrates data associated with the proposed drain connected field plate design again showing a particular emphasis on breakdown voltage, in accordance with an embodiment of the present disclosure. This figure shows simulated off-state breakdown voltage characteristics for conventional, lateral, vertical and dual field plate designs. The simulations are performed at Vgs= -6V for buffer width tBuffer=3µm and Lgd = 3µm for all the devices.
[0077] With regards to Proposed Dual Field Plate Design: Fig. 3 shows a dual field plate architecture deploying both lateral and vertical field plates. The Dual field plate design greatly suppresses the electric field at the drain edge by shifting the peak e-field away from the drain contact in both lateral as well as vertical directions. The e-field relaxation increases the design margin by pushing the breakdown limit to a higher voltage. Fig. 9 compares the breakdown voltage of all the designs explored in this work. The lateral and vertical field plate lengths are optimized for maximum breakdown voltage for fixed Lgd (= 3µm). With the introduction of lateral and vertical field plate, breakdown voltage improved by ~ 1.8× and ~ 2×, respectively, when compared to the conventional design. The Dual field plate design, however, results in highest breakdown voltage, that is ~ 3 × higher compared to conventional HEMT architecture without field plate. Besides, it also results in 6 × reduction in source-to-drain leakage when compared with lateral field plate architecture.
[0078] FIGs. 10A-10F illustrates data associated with the proposed drain connected field plate design showing a particular emphasis impact of buffer thickness and field plate lengths on breakdown voltage, in accordance with an embodiment of the present disclosure. Based on the above design guidelines can be as follows: (i) In case of lateral field plate design, the breakdown voltage improvement with field plate length is limited by impact ionization at the gate edge above a certain field plate length, which apparently is a function of buffer thickness (FIG. 10A-10B); (ii) On the other hand, there is a substantial scaling of breakdown voltage as a function of buffer thickness in case of vertical field plate designs for both unscaled (FIG.10C) and scaled devices (FIG. 10D); (iii) In the case of dual field plate design, as depicted in FIG.10E & 10F, breakdown voltage roll-off with both lateral field plate length and vertical field depth is seen. Optimization of field plate lengths is carried out using simulations for dual field plate design. Hence, within the design window, individual field plate lengths are optimized to give maximum breakdown voltage.
[0079] Accordingly, with respect to FIGs. 10A-10F, what is shown is the Impact of buffer thickness and field plate lengths on breakdown voltage for (a) lateral field plate design (Lgd= 5µm), (b) lateral field plate design (Lgd= 3µm), (c) vertical field plate design (Lgd= 5µm) and (d) lateral field plate design (Lgd= 3µm). (e) Dependency of breakdown voltage on lateral and vertical field plate lengths for dual field plate design with (e)Lgd= 5µm and (f) Lgd= 3µm.
[0080] Referring now to DC figure of merit, FIGs. 11A-11B illustrates data associated with the proposed drain connected field plate design showing a particular emphasis impact of ON-resistance on breakdown voltage, in accordance with an embodiment of the present disclosure. FIG. 11A shows that dual field plate design offers highest breakdown voltage for a given Ron. This attribute enables device scaling without compromising the breakdown voltage while FIG. 11B shows that the dual field plate design offers the highest breakdown voltage for a given ON-current (Ion) through the device. The power figure of merit (FOM) for the three designs is depicted in FIG. 12. The dual field plate design outperforms the rest of the designs and offers maximum power.
[0081] Accordingly, with respect to FIGs. 11A-11B, what is shown is (a) ON-resistance (Ron) - Breakdown Voltage (VBD) trade-off, (b) ON-current (Ion) - Breakdown Voltage (VBD) trade-off for no field plate, lateral, vertical and dual field plate architectures. For design of experiments (DOE) following parameters were varied: i.e. Lgd (1µm to 8µm), tBuffer (1.5µm to 3µm) and corresponding field plate lengths/depths.
[0082] FIG. 12 illustrates data associated with the proposed drain connected field plate design with regards to a comparative power figure of merit (FOM) for various designs, in accordance with an embodiment of the present disclosure. With regards to FIG. 12, the comparative power figure of merit (FOM) for various designs. The dual field plate design offers highest FOM along with high breakdown voltages. For design of experiments (DOE) following parameters were varied: i.e. Lgd (1µm to 8µm), tBuffer (1.5µm to 3µm) and corresponding field plate lengths/depths.
[0083] FIGs. 13A-13D illustrates data associated with the proposed drain connected field plate design again with regards to a comparative small-signal RF figure of merit (FOM) for various designs and with an emphasis on gate voltage and drain voltage, in accordance with an embodiment of the present disclosure. With regards to FIGs. 13A-13D, (a) Cut-off frequency (fT ) as function of gate bias and (b) maximum cut-off frequency roll-off with respect to drain voltage, (c) Relative degradation in cut off frequency as function of drain bias, and (d) Miller capacitance (Cdg) as function of gate bias. Plots are extracted for Lsg = 0.3µm, Lg = 0.1µm, Lgd and field plate lengths are optimized for each design in order to
achieve breakdown voltage of 150V while maximizing ON-state performance.
[0084] FIG. 14A-14D illustrates data associated with the proposed drain connected field plate design again with regards to a comparative large-signal RF (FOM) for various designs and with an emphasis on power output, drain efficiency and gain, in accordance with an embodiment of the present disclosure. With regards to FIGs. 14A-14D, (a) Output power (W) and (b) Output power (dBm) extracted at fixed input power of 35 dBm for different field plate designs; (c) Drain Efficiency and (d) Gain for frequency range
from 3 GHz to 8 GHz.
[0085] Based on the above, the RF figure of merit can be as follows: All the architectures compared here are optimized for 150V breakdown voltage. Following it, small signal and large signal analyses is performed. As for the results, they can include (i) dual field plate device has higher fT¬ among all designs (Figure 13 (a)); (ii) the device linearity is improved in case of dual field plate design (Figure 13 (b),(c)); (iii) Reduced miller capacitance in case of dual field plate design (Figure 13 (d)); (iv) Significantly higher PA output power in case of proposed dual field plate and vertical field plate designs compared to conventional lateral field plate design. (Figure 14(a),(b)); (v)Increased PA drain efficiency at high frequency compared to lateral field plate design.(Figure 14 (c)); (vi) improved PA gain at higher frequency for proposed devices (Figure 14(d)).
[0086] FIG. 15 illustrates an embodiment of the proposed design with varying vertical drain field plate length, in accordance with an embodiment of the present disclosure
[0087] FIG. 16 illustrates an embodiment of the proposed design with dual field plate design comprising of lateral field plate of length and vertical drain field plate length, in accordance with an embodiment of the present disclosure.
[0088] FIG. 17 illustrates an embodiment of the proposed design with dual field plate design comprising of lateral gate field plate, drain connected vertical drain field plate length, in accordance with an embodiment of the present disclosure.
[0089] FIG. 18 illustrates an embodiment of the proposed design comprising of lateral gate field plate and dual drain connected field plate of length, in accordance with an embodiment of the present disclosure.
[0090] FIG. 19 illustrates embodiment of the proposed design comprising of lateral source connected field plate and vertical drain connected field plate of length, in accordance with an embodiment of the present disclosure.
[0091] FIG. 20 illustrates an embodiment of the proposed design comprising of lateral source connected field plate and dual drain field plate, in accordance with an embodiment of the present disclosure.
[0092] FIG. 21 illustrates an embodiment of the proposed design comprising of lateral source connected field plate, gate connected field plate and vertical drain field plate, in accordance with an embodiment of the present disclosure.
[0093] FIG. 22 illustrates an embodiment of the proposed design comprising of lateral source connected field plate, gate connected field plate and dual drain field plate, in accordance with an embodiment of the present disclosure.
[0094] FIG. 23 illustrates a first step in the fabrication method for the proposed design showing an Epi-growth of HEMT stack, in accordance with an embodiment of the present disclosure.
[0095] FIG. 24 illustrates a second step in the fabrication method for the proposed design showing a Mesa formation, in accordance with an embodiment of the present disclosure.
[0096] FIG. 25 illustrates a third step in the fabrication method for the proposed design showing a dielectric deposition, in accordance with an embodiment of the present disclosure.
[0097] FIG. 26 illustrates a fourth step in the fabrication method for the proposed design showing an ohmic contact deposition, in accordance with an embodiment of the present disclosure.
[0098] FIG. 27 illustrates a fifth step in the fabrication method for the proposed design showing gate contact formation, in accordance with an embodiment of the present disclosure.
[0099] FIG. 28 illustrates a sixth step in the fabrication method for the proposed design showing drain connected dual field plate deposition, in accordance with an embodiment of the present disclosure.
[00100] An aspect can provide thus, a vertical Drain connected field plate design for GaN based HEMTs Wherein: A GaN High Electron Mobility Transistor (HEMT) comprising GaN buffer deposited over a transition layer and a substrate; transition layers; barrier layer deposited over GaN buffer; passivation layer covering the barrier layer; and a drain field plate of length LFP-V, at least partially covering the drain contact and extends in vertical direction into the mesa etched region (FIG. 15).
[00101] Another aspect can include the addition lateral field plate, connected from drain contact and extends towards gate contact. (Figure 16).
[00102] Another aspect can include the presence of gate connected field plate (Figure 17, Figure 18)). Another aspect can include presence of source connected field plates. Another aspect can include presence of both source and gate connected field plates. Another aspect can include presence of both source and gate connected field plates.
[00103] In an aspect, the barrier layer can be N-type doped with uniform or graded or Gaussian doping profile. In an aspect, the design can include C-doped or unintentional doped or Fe-doped buffer layers. In an aspect, the design can include SiC or Silicon or Sapphire substrates. In an aspect, the design can include Barrier layer comprising of materials from group III-V of the periodic level such as AlN or AlGaN or InAlN deposited over GaN buffer. In an aspect, the design can include with passivation layer (or spacer) deposited over barrier layer, that may include GaN or any dielectric such as Al2O3, SiN, SiO2, GaO, HfO2, SiON or combination of these.
[00104] In an aspect, the design can include the transition layers can be step graded, linearly graded or AlN interlayer type.
[00105] Another aspect of the disclosure pertains to the steps enumerated in FIGs. 22-27.
[00106] The current disclosure thus offers and affords the following: (i) The proposed vertical and dual field plate design offer ~2x and ~3x improvement in breakdown voltage compared to conventional design without field plate; (ii)It offers better on-state performance; (iii) It offers better Ron vs VBD trade-off; (iv) It offers better breakdown voltage vs gate to drain distance (Lgd) scaling; (v) It offers higher power figure of merit; (vi) It offers better small signal performance and improvement in ft; (vii) It offers better device linearity at high frequency and high drain bias; (viii) In RF PA configurations, it offer higher output power, higher gain and higher drain efficiency.
[00107] The above mentioned method is envisioned to be performed using appropriate physical devices that may be appreciated by a person skilled in the art. As such all physical devices comprising respective various physical materials serve their respective functions and all such materials and their respective manufacturing methods are intended to be covered by this disclosure.
[00108] Thus, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures can be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function can be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limited to any particular named.
[00109] While embodiments of the present invention have been illustrated and described, it will be clear that the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the invention, as described in the claim.
[00110] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[00111] The present disclosure provides a drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[00112] The present disclosure provides a simple and effective drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[00113] The present disclosure provides a reliable and efficient drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[00114] The present disclosure provides a robust drain connected field plate designs for improving breakdown performance and RF performance of GaN based HEMT devices.
[00115] The present disclosure provides a robust drain connected field plate designs that enables ~2x and ~3x improvement in breakdown voltage compared to conventional design without field plate.
[00116] The present disclosure provides a robust drain connected field plate designs that facilitates better on-state performance.
[00117] The present disclosure provides a robust drain connected field plate designs that facilitates better Ron vs VBD trade-off.
[00118] The present disclosure provides a robust drain connected field plate designs that offers better breakdown voltage vs gate to drain distance (Lgd) scaling.
[00119] The present disclosure provides a robust drain connected field plate designs that offers higher power figure of merit.
[00120] The present disclosure provides a robust drain connected field plate designs that offers better small signal performance and improvement in ft.
[00121] The present disclosure provides a robust drain connected field plate designs that offers better device linearity at high frequency and high drain bias.
[00122] The present disclosure provides a robust drain connected field plate designs that offers higher output power, higher gain and higher drain efficiency in RF PA configurations.
,CLAIMS:1. A High Electron Mobility Transistor (HEMT) device for enhancing improvement in breakdown and RF performance said device comprising:
a semiconductor based HEMT stack;
an etched mesa region, wherein the etched mesa region extends through a semiconductor buffer layer of the HEMT stack, the semiconductor buffer layer disposed epitaxially on top of one or more nucleating layers;
a passivation layer, wherein the passivation layer is of a predefined thickness, wherein the passivation layer is partially disposed in the etched mesa region;
a drain contact disposed on the passivation layer;
a first drain field plate at least partially covering the drain contact, wherein the first drain field plate is of a first predefined length, wherein the first drain field plate extends vertically into the etched mesa region; and
upon application of a positive drain bias, the extension of the drain field plate into the mesa etched region causes delay in avalanche breakdown.
2. The device as claimed in claim 1, wherein the HEMT stack further comprises of a semiconductor substrate layer disposed below the one or more nucleating layers and wherein a semiconductor channel layer is disposed on the semiconductor buffer layer and wherein the semiconductor forming the substrate is any Silicon Carbide, Silicon and Sapphire semiconductors and wherein the semiconductor buffer layer comprises any or a combination of C-doped, unintentional doped and Fe-doped buffer layers.
3. The device as claimed in claim 1, wherein the HEMT stack further comprises a semiconductor barrier layer is disposed on top of a semiconductor channel layer, wherein the semiconductor channel layer is disposed on top of the semiconductor buffer layer, and wherein the semiconductor barrier layer comprises group III-V materials, wherein the group III-V materials are any AlN, AlGaN and InAlN and wherein the semiconductor barrier layer is N-type doped having any or a combination of uniform, graded and Gaussian doping profile.
4. The device as claimed in claim 1, wherein the passivation layer covers at least a side surface of the semiconductor barrier layer, wherein the passivation layer provides protection to the device, and wherein the passivation layer comprises any GaN and any dielectric materials such as any or a combination of Al2O3, SiN, SiO2, GaO, HfO2, and SiON.
5. The device as claimed in claim 1, wherein a gate contact having a gate length is deposited between a source contact and the drain contact and wherein the source contact and the drain contact are located at either side of the device and wherein the source contact and the gate contact are separated by a first predefined distance, and the gate contact and the drain contact are separated by a second predefined distance.
6. The device as claimed in claim 1, wherein one or more transition layers are disposed below the semiconductor buffer layer and above the substrate, wherein the one or more transition layers are any or a combination of step graded, linearly graded and AlN interlayer type.
7. The device as claimed in claim 1, wherein a second drain field plate extends laterally from the drain contact towards the gate contact, and wherein the second drain field plate is of a second predefined length.
8. The device as claimed in claim 1, wherein the device is designed with any or a combination of the source connected field plate connected with the source contact and a gate connected field plate connected with the gate contact.
9. A method for designing a High Electron Mobility Transistor (HEMT) device for enhancing improvement in breakdown and RF performance, said method comprising:
growing semiconductor based HEMT stack epitaxially;
etching a mesa region in the HEMT stack, wherein the etched mesa region causes isolation of the device;
depositing a passivation layer of a predefined thickness, wherein the passivation layer is partially disposed in the etched mesa region;
depositing a drain contact on the passivation layer;
depositing a first drain field plate at least partially covering the drain contact, wherein the first drain field plate is of a first predefined length, wherein the first drain field plate extends vertically into the mesa etched region
10. The method as claimed in claim 9, wherein the method further comprises depositing a second drain field plate extends laterally from the drain contact towards the gate contact, and wherein the second drain field plate is of a second predefined length.