Claims:I/We Claim:
1. An on-chip resistance amplifier (100) that amplifies resistance of an on-chip resistor 1 (114) using a control feedback circuit, comprising: 2
a voltage divider (104) that comprises a plurality of symmetric metal oxide 3 semiconductor field effect transistors (MOSFETs) connected at a first high voltage terminal 4 (108), 5
characterized in that, 6
wherein the voltage divider (104) divides voltage at the first high 7 voltage terminal (108) in to (i) a first voltage and (ii) a second voltage using a gain of the 8 voltage divider (104); 9
an operational-amplifier (op-amp) (106) that is connected to the 10 voltage divider (104), wherein the operational-amplifier (op-amp) (106) comprises a P-11 channel metal oxide semiconductor (PMOS) input based op-amp (106), wherein an input of 12 P-channel metal oxide semiconductor (PMOS) input based op-amp (204) is connected to a 13 source of the N-channel metal oxide semiconductor (NMOS) transistor (112), wherein a 14 drain of the N-channel metal oxide semiconductor (NMOS) transistor (112) is connected to 15 the on-chip resistor (114) at a second terminal (110), 16
wherein the op-amp (106) (i) transmits the second voltage that is obtained 17 from the voltage divider (104) to the on-chip resistor, (ii) controls current in the on-chip 18 resistor (114) through the N-channel metal oxide semiconductor (NMOS) transistor (112), 19 (iii) transmits the current to the first high voltage terminal (108), and (iv) generates an 20 amplified resistance at the first high voltage terminal (108) and at a drain of the N-channel 21 metal oxide semiconductor (NMOS) transistor (112), wherein the on-chip resistor (114) at 22
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the second terminal that is connected to the drain of the NMOS transistor (112) acquires the 23 amplified resistance at the drain of the NMOS transistor (112). 24
2. The on-chip resistance amplifier (100) as claimed in claim 1, wherein the operational 1 amplifier (106) holds high gain and operates at a ultra-low input common mode voltage. 2
3. The on-chip resistance amplifier (100) as claimed in claim1, wherein a gate and a 1 source of each symmetric metal oxide semiconductor field effect transistor (MOSFET) in 2 the voltage divider (104) are connected in series to (i) yield voltage division independent of 3 a temperature and process, and (ii) consume ultra-low power. 4
4. The on-chip resistance amplifier (100) as claimed in claim 1, wherein temperature 1 characteristics of the on-chip resistor (114) are linear if the on-chip resistor is a N plus 2 diffused resistor (rnplus). 3
5. The on-chip resistance amplifier (100) as claimed in claim 1, wherein temperature 1 characteristics of the on-chip resistor (114) are non-linear if the on-chip resistor is a N plus 2 poly resistor (rnpoly). 3
6. The on-chip resistance amplifier (100) as claimed in claim 1, comprises a temperature 1 compensation circuit that comprises a second op-amp, wherein the second op-amp provides 2 higher degree of accuracy in amplifying the resistance of the on-chip resistor (114) as the 3 gain error introduced by temperature change in the op-amp (106) gets compensated by the 4 second op-amp (404). 5
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1 7. The on-chip resistance amplifier (100) as claimed in claim 7, wherein the second op2
amp (404) operates at an ultra-low input common mode voltage and high gain.
1 8. The on-chip resistance amplifier (100) as claimed in claim 1, wherein the on-chip
2 resistance amplifier (100) is fabricated on a chip. , Description:BACKGROUND
Technical Field 5
[0001] The embodiments herein generally relate to a semiconductor structure, and more specifically, an on-chip complementary metal-oxide semiconductor (CMOS) resistance amplifier.
Description of the Related Art 10
[0002] Resistors are the essential and common elements of any electronic circuits and extensively used in electronic equipment. They are frequently used in Integrated Circuits. The conventional on-chip resistance takes a large silicon area compared to metal oxide semiconductor MOS transistor. In fabrication, the area is proportional to cost. If the silicon 15 area is more, then the cost of the chip also increases. Therefore, large resistances are avoided to fabricate on the chip. For low power circuits, large resistances are often required but due to limited silicon area they are avoided. Hence the conventional resistor is replaced by a complementary metal-oxide-semiconductor CMOS circuit or a switched capacitor-based resistor circuit to save area. 20
[0003] The existing CMOS based resistance use a metal oxide semiconductor field effect transistor MOSFET biased in the triode region. In triode region the current through and voltage across the MOSFETs are linearly proportional to each other. This acts as a resistance which follows Voltage-Current (V-I) characteristics. Also a feedback or control circuit is required to control the resistance value of the MOSFET. A different circuit has been 25 proposed to bias the MOSFET using feedback so as it acts as primarily as amplified resistance than in triode methodology. Even with feedback system, the existing methodology
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is unable to get good resistance characteristic. Also achieving high value of resistance following linear V-I characteristics is difficult. The control of resistance value is very difficult in previously existing methodology. Also the temperature characteristics are non-linear and have a limited region of operation, the region in which the resistance value is stable with respect to temperature and voltage across it. 5
[0004] Existing methodologies involves a switched capacitor based resistor circuit where precision resistors with large resistance values are implemented by switches and capacitors. This is constructed with resistors, capacitors and switches whose values are accurately known, switched capacitor filters depend only on the ratios between capacitances and the switching frequency. This makes them much more suitable for use within integrated 10 circuits, where the accurately specified absolute value of components such as resistors and capacitors are not economical to construct. It is easier to fabricate reliably with a wide range of values. This methodology has the benefit that the value of resistance can be adjusted by changing the switching frequency. This is a discrete time resistor (such as digital circuit) unlike the conventional resistances, which results in difficulty in using continuous time 15 blocks. In analog circuits, voltage or current reference commonly require resistance with proportional to absolute temperature PTAT or complementary to absolute temperature CTAT characteristics which results in failing to use switch capacitor resistance in place of conventional resistance.
[0005] Accordingly, there remains a need to design an on-chip resistance which 20 involves a small resistor and deriving high resistance from it, also saves a considerable amount of area without compromising the functionality and accuracy.
SUMMARY
[0006] In view of the foregoing, an embodiment herein provides an on-chip resistance 25
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amplifier that amplifies resistance of an on-chip resistor using a control feedback circuit. This circuit includes a voltage divider, an operational amplifier (op-amp), an NMOS transistor, an on-chip resistor. The voltage divider includes one or more metal oxide semiconductor field effect transistors (MOSFETs) that is connected at a first voltage terminal. The voltage divider divides the voltage at the first voltage terminal in to a first voltage and a second voltage using 5 a gain of the voltage divider. The op-amp is a P-channel metal oxide semiconductor (PMOS) input based op-amp and an output. The one input terminal of PMOS op-amp is connected to the voltage divider. The output of PMOS op-amp is connected to a source of the NMOS transistor and a drain of the NMOS transistor is connected to the on-chip resistor at a second terminal. The op-amp transmits the second voltage that is obtained from the voltage divider 10 to the on-chip resistor. This enables current in the on-chip resistor through the NMOS transistor and transmits the current to the high voltage terminal and thus generating an amplified resistance at the high voltage terminal and at the drain of the NMOS transistor. The on-chip resistor at the second terminal obtains the amplified resistance which is at the drain of the NMOS transistor. 15
[0007] In some embodiments, the op-amp holds a high gain and works at an input common mode voltage close to zero volts to a few hundreds of millivolts.
[0008] In some embodiments, the voltage divider is implemented using a gate and a source of each symmetric number of metal oxide semiconductor field effect transistors (MOSFETs) connected in series which makes voltage division independent of temperature 20 and process, and it consumes very less current.
[0009] In some embodiments, the temperature characteristics of the on-chip resistor are linear if the on-chip resistor is an N plus diffused resistor (rnplus).
[0010] In some embodiments, the temperature characteristics of the on-chip resistor are non-linear if the on-chip resistor is an N plus poly resistor (rnpoly). 25
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[0006] In some embodiments, the on-chip resistance amplifier comprises a temperature compensation circuit. This circuit comprises a second op-amp which provides higher degree of accuracy in amplifying the resistance of the on-chip resistor as the gain error introduced by temperature change in the op-amp gets compensated by the second op-amp.
[0007] In some embodiments, the second op-amp operates at an ultra-low input 5 common mode voltage and high gain.
[0008] In some embodiments, the on-chip resistance amplifier is fabricated on a chip.
[0009] The on-chip resistance amplifier amplifies the resistance of the on-chip resistor using a control feedback circuit. This on-chip resistance amplifier follows Voltage-Current (V-I) as a conventional resistor does. The advantage of this amplifier is it works well 10 for ultra-low power voltage and current reference circuits which use high values of resistance to reduce power. Accurate current references use the linear V-I characteristic of resistance as well as proportional to absolute temperature PTAT or complementary to absolute temperature CTAT characteristic of resistance to generate accurate current with respect to temperature. These high values of resistance occupy more area thereby increasing the cost of the chip. 15 Hence the on-chip resistance amplifier 100 works well for these applications.
[0010] Filters are important in several signal chains like hard drive/CD/DVD applications where they are used for partial channel equalisation and antialiasing. The op-amp, resistor capacitor RC architecture is used in such applications because of excellent linearity and low excess noise of the integrators. Constant capacitance scaling is usually 20 adopted for programmability, so that the shape of the transfer characteristic remains independent on the set bandwidth. This involves scaling the resistances. This programmability in resistance may need large resistances which occupy large area. This problem can be solved with the programming resistance by using the on-chip resistance amplifier, by programming the gain of the voltage divider. 25
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[0011] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made 5 within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The embodiments herein will be better understood from the following detailed 10 description with reference to the drawings, in which:
[0011] FIG. 1 is a circuit diagram that illustrates an on-chip resistance amplifier of an on-chip resistor using a control feedback circuit according to some embodiments herein;
[0012] FIG. 2 is a circuit diagram that illustrates an operational amplifier of FIG. 1 according to some embodiments herein; 15
[0013] FIG. 3 is a circuit diagram that illustrates a voltage divider of FIG. 1 according to some embodiments herein;
[0014] FIG. 4 is a circuit diagram that illustrates a resistance amplifier with a temperature compensation circuit according to some embodiments herein;
[0015] FIG. 5 illustrates a layout of resistance amplifier area comparison of large 20 resistance and its equivalent CMOS resistance amplifier with an optimization circuit according to some embodiments herein; and
[0016] FIG. 6 illustrates a layout of resistance amplifier area comparison of large resistance and its equivalent CMOS resistance amplifier without optimization circuit according to some embodiments herein. 25
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DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0017] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are 5 illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. 10 Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
[0018] As mentioned, there remains a need to design an on-chip resistance which involves a small resistor and deriving high resistance from it, also saves a considerable amount of area without compromising the functionality and accuracy. Referring now to the 15 drawings, and more particularly to FIGS. 1 through 6, where, preferred embodiments are shown.
[0019] FIG. 1 is a block diagram that illustrates an on-chip resistance amplifier 100 of an on-chip resistor 114 according to some embodiments herein. The on-chip resistance amplifier 100 includes a resistance amplifier 102, a voltage divider 104, and a first 20 operational amplifier (op-amp) 106, a high voltage terminal 108, a low voltage terminal 110, the NMOS transistor 112 and the on-chip resistor 114. In some embodiments, the high voltage terminal 108 includes voltage (V) ranges from 0.4 Volts to 3.6 Volts. In some embodiments, the low voltage terminal 110 may be connected at ground. The voltage divider 104 is connected to the high voltage terminal 108 and divides voltage V into two a first 25 voltage and a second voltage V/A using a gain (A) of the voltage divider. The voltage divider
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is connected to one of the input of the first op-amp 106 and another input of the first op-amp 106 is connected to a source of the NMOS transistor 112. A drain of the NMOS transistor 112 is connected to the on-chip resistor 114 and on another end connected to the low voltage terminal 110. The first op-amp 106 transmits the second voltage V/A to the on-chip resistor 114 whose resistance value is Ron-chip. The first op-amp 106 controls current in the on-chip 5 resistor 114 (V/A * Ron-chip) and transmits through the NMOS transistor 112 to the high voltage terminal 108. The high voltage terminal 108 includes V potential and current through it is (V/A)*Ron-chip. Thus the amplified resultant resistance Ramp = V/I = V/ [(V/A)*Ron-chip] = (A * Ron-chip) is generated at the first high voltage terminal 108 and at the drain of the NMOS transistor 112. Thus the on-chip resistor 114 at the low voltage terminal 110 that is connected 10 to the drain of the NMOS transistor 112 obtains the amplified resistance.
[0020] In some embodiments, the voltage divider 104 consumes current which is less than current consumed by the on-chip resistor 114 connected to the high voltage terminal 108.
[0021] In some embodiments, the first operational amplifier (op-amp) 106 is a two-15 stage P-channel metal oxide semiconductor (PMOS) input based operational amplifier and the other input is connected to the source of the NMOS transistor 112. In some embodiments, the NMOS transistor 112 is used as a pass transistor whose resistance is (A-1)*Ron-chip and the resistance of the NMOS transistor 112 resistance is adjusted using the first op-amp 106 by controlling gate voltage of the NMOS transistor 112. Hence the NMOS 20 transistor 112 does not depend on process, voltage and temperature. In some embodiments, the first op-amp 106 operates at an input common mode voltage from 0 Volts to 100 milliVolts and its gain is of 70 decibels (dB).
[0022] In some embodiments, the voltage divider 104 is implemented using one or more symmetric metal oxide semiconductor field effect transistors (MOSFETs). In some
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embodiments, the MOSFETs are connected in series to provide voltage division which is independent of temperature and process.
[0023] In some embodiments, ratio between width and length (W/L) of each MOSFET is same. In some embodiments, a body and a source of each MOSFET are connected together. In some embodiments, the voltage divider 104 works at ultra-low power.
[0024] In some embodiments, the on-chip resistance amplifier 100 operates for continuous time blocks. In some embodiments, temperature characteristics of the on-chip resistance amplifier 100 depends on temperature characteristics of the on-chip resistor 114 Ron-chip.
[0025] FIG. 2 is a circuit diagram that illustrates the operational amplifier 106 5 according to some embodiments herein. In some embodiments, the operational amplifier (op-amp) 106 is a high-gain voltage amplifier with a differential input and usually a single-ended output. The op-amp 106 is an integral building block in analog and control circuits. The op-amp 106 includes a two stage P-channel metal oxide semiconductor (PMOS) field effect transistors-based input for input common mode voltages near the ground interconnected. The 10 op-amp 106 generates an output voltage that is typically larger than the potential difference between its input terminals [Vout = A (Vin+ - Vin+) and A = gain of hundreds of thousands (very large)]. In some embodiments, the op-amp 106 holds high gain of 70 deciBels (dB) in the on-chip resistance amplifier 100 and operates at an input common mode voltage close to zero volts to hundreds of millivolts. In some embodiments, the op-amp 106 is used as a 15 building block due to its versatility to control a system using negative feedback.
[0026] FIG. 3 illustrates a circuit diagram of the voltage divider 104 according to some embodiments herein. The voltage divider 104 includes a stack of symmetric metal–oxide–semiconductor field-effect transistors (MOSFETs) connected in series as a diode connected as load to make voltage division ratio independent of temperature, process. 20
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Therefore the relation between input and output is Vout = Vin/D, where D is equal to number of MOSFETS that are connected in series.
[0027] FIG. 4 illustrates a block diagram of the resistance amplifier 100 with a temperature compensation circuit according to some embodiments herein. The resistance amplifier 100 with compensation circuit that is connected in negative feedback loop includes the voltage divider 104, the first operational amplifier (op-amp) 106, the high voltage terminal 108, the low voltage terminal 110, the N-channel metal oxide semiconductor (NMOS) transistor 112, a second P-channel metal oxide semiconductor (PMOS) transistor 402, a second operational amplifier (op-amp) 404, and a second on-chip resistor 406. The voltage divider 104 is connected to the high voltage terminal 108. The voltage divider 104 is connected at least one input of the first op-amp 106 and at least one output of the first op-amp 106 is connected to the source of the NMOS transistor 112. A drain of the NMOS transistor 112 is connected to the on-chip resistor 114 and on the other end connected to the low voltage terminal 110. The other end of the voltage divider 104 is connected to the drain of the second PMOS transistor 402. An input of the second op-amp 404 is connected to the other end of the voltage divider 104 and the output of the second op-amp 404 is connected to the source of the second PMOS transistor 402. The other input of the second op-amp is connected to one end of the second on-chip resistor 406 which is connected to the low voltage terminal 110. The voltage divider 104 that is connected to the first high voltage terminal 108. The voltage divider 104 divides the voltage at the first high voltage terminal 108 using a gain to generate a second voltage. The input voltage Vin, at the high voltage terminal is divided by D times using the voltage divider 104. This (Vin/D) voltage is tracked across the on-chip resistor 106 and the second on-chip resistor 406. This forces a current of Vin/(D*R) + eTemp through the first resistor 114 and Vin/(D*R) - eTemp through the second resistor 406 where ±eTemp is error in gain of op-amp with respect to temperature and ± is
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decided by the connection of op amp with NMOS or PMOS in negative feedback. Due to the opposite behaviour of NMOS and PMOS feedback loop with op-amp, this temperature error is cancelled out by adding both current at the low voltage terminal 110 i.e. Itotal = [Vin/(D*R) + eTemp] + [Vin/(D*R) - eTemp] = 2.[Vin/(D*R)]. The voltage divider 104 draws very less current compared to current through the NMOS transistor 112 and the PMOS transistor 402, so if Vin is input voltage, the resistance amplifier 100 with the temperature compensation circuit draws a total current of I = 2.[Vin/(D*R)]. A resultant resistance shown at the low voltage terminal 110 is Ron-chip = Vin/{2.[Vin/(D*R)]} = (D*R)/2. This is similar to functionality of a small resistance R amplified by D times (Ron-chip = D*R). In some embodiments, as the second op amp 404 with the PMOS transistor 402 generates opposite error with respect to temperature as the first op amp 106 with the NMOS transistor 112 does. As the PMOS transistor 402 is a p-channel layer in an n-channel transistor body and the NMOS transistor 402 is a n-channel layer in an p-channel transistor body, they generate an equal and opposite error with respect to temperature. The resistance amplifier 100 with the temperature compensation circuit adds error of the op-amp 106 and the second op-amp 404 which cancel out the error as the op-amp 106 is connected with NMOS transistor 112 and the second op-amp 404 is connected with PMOS transistor 402. This gives much accurate amplified resistance. Thus, it improves the accuracy of amplified resistance by 15 to 20 times with respect to temperature.
[0028] FIG. 5 illustrates a layout area comparison of large resistance and its equivalent CMOS resistance amplifier with temperature compensation circuit according to some embodiments herein. In some embodiments, an on-chip area of large resistance of 23M is 0.12mm2 and resistance amplifier is 0.0018mm2 (including two 150 times small rnplus i.e. 153kO and 150 symmetric MOSFETs (voltage divider) and 2 opamp with their NMOS and 5 PMOS transistor) and the area diminished is 0.12/0.0018 ˜ 65. The maximum error in
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resistance value with in temperature range (-55oC to 125oC) is 0.06% i.e. 23MO ± 0.014MO. The maximum error in resistance value with voltage change of 1V across it = 0.8% i.e. 23MO ± 0.184MO. In an embodiment, the total power consumption is 600nW and bandwidth of tens of kilohertz. The bandwidth is enhanced by burning more power i.e. designing op amps with higher current. In an embodiment, the temperature compensation circuit improves the 5 amplified resistance accuracy by 15 to 20 times. When resistance amplifier with compensation circuit compared with the resistance amplifier without compensation circuit, the first one may have extra hardware, high power consumption, low resistance amplification gain.
[0029] FIG. 6 illustrates a layout area comparison of large resistance and its 10 equivalent CMOS resistance amplifier without compensation circuit according to some embodiments herein. In some embodiments, the on-chip area of large resistance of 23MO is 0.12mm2 and resistance amplifier is 0.0011mm2 (including 150 times small rnplus i.e. 153kO and 150 symmetric MOSFETs (the voltage divider 104) and the op-amp 106 and the NMOS transistor 112), and the area diminished is 0.12/0.0011 ˜ 110. The maximum error in 15 resistance value with in temperature range (-55oC to 125oC) = 0.7% i.e. 23MO ± 0.16MO. The maximum error in resistance value with voltage change of 1V across it = 0.4% i.e. 23MO ± 0.092MO. In an embodiment, the power of consumption is 300nW.
[0030] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the
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embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.