Abstract: A new design of optical S-R Latch has been made that can retain two stable states depending upon the input combinations. The basic design consists of two all-optical NAND gates, each of which comprises of one beam combiner for two input laser beams coming through two sinusoidal input diffraction gratings, an optical 4f setup along with a frequency plane filter.
Claims:1. An optical S-R latch comprising of two all optical NAND gates has been proposed.
2. The all optical NAND gate consists of all optical AND and NOT gates.
3. An optical AND gate consists of two input gratings, a beam combiner, and an optical 4f setup along with a spatial filter and three double convex lenses.
4. An optical NOT gate consists of one input grating, a beam combiner, and an optical 4f setup along with a spatial filter, two double convex lenses and one cylindrical lens.
5. For a particular input combination one stable state is achieved and retained until and unless the input combination is reversed.
6. The last output will be retained for input combination of 1-1.
7. The output is invalid for input combination of 0-0.
, Description:The basic building block of the all-optical S-R latch is two two-input all-optical NAND gates, which are comprised of optical AND and optical NOT gates as described in the patent publication3. The inputs of the NAND gates are considered as the pulsed laser light, where the presence and absence of light designates logic 1 and 0 respectively.
The two inputs of the NAND gate are modulated by two sinusoidal gratings gr1 and gr2 respectively, which can be characterized as
whereFo= spatial frequency and (x, y) is the spatial coordinate of the grating plane.
Both the inputs from gratings gr1 and gr2 are then introduced into a beam combiner, wherein they incident on the double convex lens to form an image of unity magnification. That is, in the image plane of the two gratings (corresponding to plane 16) it produces the final grating structure that can be written as
"gr=gr1×gr2"
The light then goes on to get Fourier Transformed optically to form a 3x3 optical impulse array. Essentially it looks like optical dots on the screen in the frequency plane 18, which is the back-focal plane of lens17. The operation can be represented as
"F" _"1" "=F.T." ["gr1×gr2" ]
The operations of the frequency plane filter, filter, for AND gate is shown in Figure2. An appropriate spatial filter is chosen for this frequency plane that allows only one corner optical dot corresponding to the (1, 1) spectral order. It makes the light emerge out of the filter only if both the sources at gr1 and gr2 are ON. The light from this filter, which is essentially a point source, again gets Fourier Transformed to give the output on the screen22. In case any of the sources are absent, then there is no illumination on the screen.
The finally output (F_2) is determined by the operation
"F" _"2" "=F.T." ["F" _"1" "×filter" ]
This output is then connected to the following logical NOT operation through a waveguide. For this purpose a similar system is used except of a cylindrical lens in the place of the spherical Fourier Transform lens. The single input of this section is modulated by a same gr1 grating whereas, another input to the beam combiner is always ON, i.e. mathematically in this case
When the input light at gr1 is not there, the light from the control source enters the system, and a uniform horizontal spectrum is formed on the first screen after passing through the cylindrical lens. A spatial filter is used as before, which allows the light to pass through it from a particular region. Hence the output screen is illuminated, suggesting logic 1.
When input light is there, the spectrum on the first screen becomes discontinuous. The filter is selected, such that the slit is at a discontinuity of the spectrum. Hence light does not pass through it, and the output screen remains dark, suggesting logic 0.
The truth table of the NAND gate logic is as follows:
INPUT A INPUT B OUTPUT Y
0 0 1
0 1 1
1 0 1
1 1 0
Table 1: NAND gate truth table
The corresponding results of this optical gate are as shown in Figure 5 and 6.
This property of the optical NAND gate is used to create the optical S-R latch – an optical passive circuit to latch the output state created by the input signal unless another appropriate input changes it. The property of this latch is similar to its corresponding electronic circuit. The operational behavior is as follows4,5:
When the input S (Set) = R (Reset) = 1, the output of the latch attains its normal resting state, i.e. outputs remain in state prior to input.
For S = 0, R = 1,Qwill go high since at least one input of the first NAND becomes low. In this case since both the inputs of the second NAND gate goes high, Q ¯ becomes low. Now, this Q value will remain high even if the SET input goes high because it will retain the previous state.
For S= 1, R = 0, Q will go low and remain low even if the RESET input goes high.
For S = R = 0. Output is unpredictable because the latch is being set and reset at the same time. This state is invalid for the operation.
The truth table of this S-R latch is as follows:
S R Q Q ¯
0 0 Invalid Invalid
0 1 1 0
1 0 0 1
1 1 Previous State Previous State
Table 2: S-R Latch truth table
The output waveforms of the optical S-R latch are shown in Figure 6 & 7, which follows the above truth table.
Figure 7
Figure 6
The condition to be obeyed for the successful operation of this S-R latch: The time between the successive input pulses must be greater than the time taken by one optical pulse to cover the total optical path. For optical ICs this condition is easily attainable.
| # | Name | Date |
|---|---|---|
| 1 | 201931010615-ENDORSEMENT BY INVENTORS [21-03-2024(online)].pdf | 2024-03-21 |
| 1 | 201931010615-FORM 1 [19-03-2019(online)].pdf | 2019-03-19 |
| 2 | 201931010615-DRAWINGS [19-03-2019(online)].pdf | 2019-03-19 |
| 2 | 201931010615-FER.pdf | 2023-10-05 |
| 3 | 201931010615-COMPLETE SPECIFICATION [19-03-2019(online)].pdf | 2019-03-19 |
| 3 | 201931010615-FORM 13 [08-02-2022(online)].pdf | 2022-02-08 |
| 4 | 201931010615-FORM 18 [24-11-2021(online)].pdf | 2021-11-24 |
| 5 | 201931010615-COMPLETE SPECIFICATION [19-03-2019(online)].pdf | 2019-03-19 |
| 5 | 201931010615-FORM 13 [08-02-2022(online)].pdf | 2022-02-08 |
| 6 | 201931010615-DRAWINGS [19-03-2019(online)].pdf | 2019-03-19 |
| 6 | 201931010615-FER.pdf | 2023-10-05 |
| 7 | 201931010615-ENDORSEMENT BY INVENTORS [21-03-2024(online)].pdf | 2024-03-21 |
| 7 | 201931010615-FORM 1 [19-03-2019(online)].pdf | 2019-03-19 |
| 1 | search_strategy_615E_19-05-2022.pdf |
| 2 | 201931010615SearchHistoryE_17-09-2023.pdf |