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Methods And Systems For Designing Correlation Filter

Abstract: A system and a method for designing a correlation filter in a multi-processor system are provided. The system includes a multi-core processor coupled to a first memory and one or more co-processors coupled to one or more respective second memories. The method includes partitioning, by the multi-core processor, each frame of a plurality of frames associated with media content into a plurality of pixel-columns. The plurality of pixel-columns are systematically stored width-wise in a plurality of temporary matrices by a plurality of threads of the multi-core processor. The plurality of temporary matrices are transferred by the multi-core processor to one or more respective second memories in a plurality of streams simultaneously in an asynchronous mode. A plurality of filter harmonics of the correlation filter are computed by performing linear algebraic and fast Fourier transform operations involving at least the plurality of temporary matrices, to obtain the correlation filter.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
26 February 2015
Publication Number
13/2017
Publication Type
INA
Invention Field
PHYSICS
Status
Email
iprdel@lakshmisri.com
Parent Application
Patent Number
Legal Status
Grant Date
2023-10-18
Renewal Date

Applicants

TATA CONSULTANCY SERVICES LIMITED
Nirmal Building, 9th Floor, Nariman Point, Mumbai, Maharashtra 400021, India

Inventors

1. KALELE, Amit
S2 Poorna, TCS Sahayadri Park, Rajiv Gandhi infotech Park, Phase 3, Hinjewadi, Pune 411057, India
2. JAIN, Anubhav
S2 Poorna, TCS Sahayadri Park, Rajiv Gandhi infotech Park, Phase 3, Hinjewadi, Pune 411057, India
3. CHALAMALA, Srinivasa Rao
GS3-21, Tata Consultancy Services, Deccan Park, No 1., Software units layouts, HiTEC city, Madhapur, Hyderabad, 500081, India
4. NAMBIAR, Manoj Karunakaran
TCS Gateeway Park, MIDC, Andheri East Mumbai, India

Specification

DESC:METHODS AND SYSTEMS FOR DESIGNING CORRELATION FILTER ,CLAIMS:1. A computer-implemented method for designing a correlation filter in a multi-processor system having a multi-core processor coupled to a first memory and one or more co-processors coupled to one or more respective second memories, the method comprising:
receiving, by the multi-core processor, a media content comprising a plurality of frames;
partitioning, by the multi-core processor, each frame of the plurality of frames into a plurality of pixel-columns having equal width;
systematically storing the plurality of pixel-columns width-wise in a plurality of temporary matrices, wherein storing the plurality of pixel-columns in the plurality of temporary matrices is performed in parallel by a plurality of threads of the multi-core processor;
transferring, by the multi-core processor, the plurality of temporary matrices to one or more respective second memories in a plurality of streams simultaneously in an asynchronous mode; and
computing, by the one or more co-processors, a plurality of filter harmonics of the correlation filter in the plurality of streams, wherein computing in a stream of the plurality of streams comprises performing compute operations involving at least the plurality of temporary matrices, to obtain the correlation filter.

2. The method as claimed in claim 1, wherein the media content comprises one of a video and a set of images.
3. The method as claimed in claim 1, wherein the multi-core processor comprises a central processing unit (CPU).
4. The method as claimed in claim 3, wherein each of the one or more co-processors of the set of second multi-core processors comprises a graphic processing unit (GPU).
5. The method as claimed in claim 4, wherein the CPU is coupled to the set of GPUs by a bus.
6. The method as claimed in claim 5, wherein the bus is a Peripheral Component Interconnect (PCI) bus.
7. The method as claimed in claim 1, wherein the correlation filter comprises Optimal Trade-Off Circular Harmonic Function (OTCHF) filter.
8. The method as claimed in claim 1, wherein systematically storing the plurality of pixel-columns width-wise comprises:
extracting single pixel-column from each of the plurality of frames; and
storing the extracted single pixel-column extracted from each of the plurality of frames in a temporary matrix of the plurality of temporary matrices.

9. The method as claimed in claim 1, wherein prior to computing the plurality of filter harmonics of the correlation filter, the method comprises distributing the plurality of temporary matrices in a plurality of sets of batches to each of the plurality of streams, wherein each stream of the plurality of streams comprises a plurality of compute threads operating in parallel.

10. The method as claimed in claim 1, wherein the compute operations comprises linear algebraic and Fast Fourier transform operations.

11. A multi-processor system for designing a correlation filter, the system comprising
a first memory;
a multi-core processor coupled to the first memory;
one or more co-processors coupled to the multi-core processor; and
one or more respective second memories associated with the one or more co-processors, wherein the multi-core processor is capable of executing programmed instructions stored in the first memory and the one or more co-processors are capable of executing programmed instructions stored in the one or more respective second memories to:
receive, by the multi-core processor, a media content comprising a plurality of frames;
partition, by the multi-core processor, each frame of the plurality of frames into a plurality of pixel-columns having equal width;
systematically store the plurality of pixel-columns width-wise in a plurality of temporary matrices, wherein storing the plurality of pixel-columns in the plurality of temporary matrices is performed in parallel by a plurality of threads of the multi-core processor;
transfer, by the multi-core processor, the plurality of temporary matrices to one or more respective second memories in a plurality of streams simultaneously in an asynchronous mode; and
compute, by the one or more co-processors, a plurality of filter harmonics of the correlation filter in the plurality of streams, wherein computing in a stream of the plurality of streams comprises performing compute operations involving at least the plurality of temporary matrices, to obtain the correlation filter.

12. The system as claimed in claim11, wherein the media content comprises one of a video and a set of images.

13. The system as claimed in claim 11, wherein the multi-core processor comprises a central processing unit (CPU).

14. The system as claimed in claim 12, wherein each of the one or more co-processors of the set of second multi-core processors comprises a graphic processing unit (GPU).

15. The system as claimed in claim 13, wherein the CPU is coupled to the set of GPUs by a bus.

16. The system as claimed in claim 14, wherein the bus is a PCI bus.

17. The system as claimed in claim 11, wherein the correlation filter comprises Optimal Trade-Off Circular Harmonic Function (OTCHF) filter.

18. The system as claimed in claim11, wherein to systematically store the plurality of pixel-columns width-wise, the multi-core processor is configured by the instructions to:
extract single pixel-column from each of the plurality of frames; and
store the extracted single pixel-column extracted from each of the plurality of frames in a temporary matrix of the plurality of temporary matrices.

19. The system as claimed in claim 11, wherein prior to computing the plurality of filter harmonics of the correlation filter, the multi-core processor is configured by the instructions to distribute the plurality of temporary matrices in a plurality of sets of batches to each of the plurality of streams, wherein each stream of the plurality of streams comprises a plurality of compute threads operating in parallel.

20. The system as claimed in claim 11, wherein the compute operations comprises linear algebraic and fast Fourier transform operations.

Documents

Application Documents

# Name Date
1 641-MUM-2015-POWER OF AUTHORITY-(21-04-2015).pdf 2015-04-21
2 641-MUM-2015-PatentCertificate18-10-2023.pdf 2023-10-18
2 641-MUM-2015-CORRESPONDENCE-(21-04-2015).pdf 2015-04-21
3 REQUEST FOR CERTIFIED COPY [09-02-2016(online)].pdf 2016-02-09
4 OTHERS [23-02-2016(online)].pdf 2016-02-23
5 Drawing [23-02-2016(online)].pdf 2016-02-23
6 Description(Complete) [23-02-2016(online)].pdf 2016-02-23
7 Form 3 [14-10-2016(online)].pdf 2016-10-14
8 PD015505IN-SC SPEC FOR FILING.pdf ONLINE 2018-08-11
9 PD015505IN-SC SPEC FOR FILING.pdf 2018-08-11
10 PD015505IN-SC FORM 3.pdf ONLINE 2018-08-11
11 PD015505IN-SC FORM 3.pdf 2018-08-11
12 FIGURES-TCS-PD015505IN-SC.pdf ONLINE 2018-08-11
13 FIGURES-TCS-PD015505IN-SC.pdf 2018-08-11
14 ABSTRACT1.JPG 2018-08-11
15 641-MUM-2015-Form 1-150715.pdf 2018-08-11
16 641-MUM-2015-Correspondence-150715.pdf 2018-08-11
17 641-MUM-2015-FER.pdf 2020-02-13
18 641-MUM-2015-Information under section 8(2) [24-07-2020(online)].pdf 2020-07-24
19 641-MUM-2015-FORM 3 [24-07-2020(online)].pdf 2020-07-24
20 641-MUM-2015-OTHERS [11-08-2020(online)].pdf 2020-08-11
21 641-MUM-2015-FER_SER_REPLY [11-08-2020(online)].pdf 2020-08-11
22 641-MUM-2015-COMPLETE SPECIFICATION [11-08-2020(online)].pdf 2020-08-11
23 641-MUM-2015-CLAIMS [11-08-2020(online)].pdf 2020-08-11
24 641-MUM-2015-ABSTRACT [11-08-2020(online)].pdf 2020-08-11
25 641-MUM-2015-PatentCertificate18-10-2023.pdf 2023-10-18
26 641-MUM-2015-IntimationOfGrant18-10-2023.pdf 2023-10-18

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