Claims:1. A packaged device comprising:
a host chip comprising a processor core;
a chiplet comprising a memory coupled to communicate with the processor core via a first hardware interface at a first side of the chiplet; and
a second hardware interface comprising conductive contacts at a second side of the chiplet, wherein the second side is opposite the first side, wherein a first minimum metallization feature pitch of the first hardware interface is smaller than a second minimum metallization feature pitch of the second hardware interface, wherein the chiplet overlaps a first surface region of the host chip, and wherein, of the chiplet and the second hardware interface, a second surface region of the host chip is overlapped by only the second hardware interface.
, Description:BACKGROUND
1. Technical Field
[0001] This disclosure generally relates to integrated circuitry and more particularly, but not exclusively, to a memory array which is integrated in a chiplet of a packaged device.
2. Background Art
[0002] The term “data locality” refers to a physical proximity of a memory resource, which is for storing data, to compute circuitry which accesses the data to or from said memory resource. Data locality is important in many graphics and other computational applications. Typically, a relatively close locality of data and compute circuitry is associated with improvements to processor execution speed, and overall throughput. As a result, close data locality often contributes to energy efficiency for data loading operations and/or data storing operations by a processor.
[0003] Hierarchical cache systems are one example of a technology that provides improvements to data locality. However, there are various manufacturing and performance limitations associated with the integration of cache memory with one or more processor cores in a monolithic integrated circuit (IC) chip. Such limitations include difficulties associated with fabricating large IC chips, inefficiencies with associated circuit logic, and increased routing latency and/or power consumption, especially for central processing units (CPUs) or graphical processing units (GPUs) with large core counts.
[0004] As successive generations of semiconductor fabrication continue to scale in terms of size, operational speed, and power efficiency, there is expected to be an increasing demand placed on solutions to improve the locality of data for use by one or more processor cores.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
[0006] FIG. 1A illustrates a cross-sectional side view showing elements of a system to provide access to a memory of a chiplet according to an embodiment.
[0007] FIG. 1B illustrates a functional block diagram showing elements of a system to provide memory functionality with a chiplet according to an embodiment.
[0008] FIG. 2 illustrates a flow diagram showing elements of a method to provide memory functionality with a chiplet according to an embodiment.
[0009] FIG. 3 illustrates a functional block diagram showing elements of a multi-core system including a memory chiplet according to an embodiment.
[0010] FIG. 4 illustrates a layout diagram showing elements of an integrated circuit chip which is configured to access a memory chiplet according to an embodiment.
[0011] FIG. 5A illustrates a layout diagram showing elements of an integrated circuit chip which is configured to access a memory chiplet according to an embodiment.
[0012] FIG. 5B illustrates a functional block diagram showing elements of a memory chiplet according to an embodiment.
[0013] FIGs. 6A, 6B illustrate cross-sectional side views each of a respective packaged device according to a corresponding embodiment.
[0014] FIGs. 7A, 7B illustrate cross-sectional side views each of a respective packaged device according to a corresponding embodiment.
[0015] FIG. 8 illustrates a functional block diagram showing a computing device in accordance with one embodiment.
[0016] FIG. 9 illustrates a functional block diagram showing an exemplary computer system, in accordance with one embodiment.
[0017] FIG. 10 illustrates a cross-sectional view of an interposer implementing one or more embodiments.

DETAILED DESCRIPTION
[0018] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.
[0019] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate a greater number of constituent signal paths, and/or have arrows at one or more ends, to indicate a direction of information flow. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.