FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
PARALLEL DRIVING DEVICE AND POWER CONVERSION DEVICE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED
AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 100-8310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.
2
DESCRIPTION
5 Field
[0001] The present invention relates to a parallel
driving device that drives a circuit having a plurality of
parallel-connected power semiconductor elements
(hereinafter, appropriately abbreviated as "semiconductor
10 element(s)"), and also relates to a power conversion device
including the parallel driving device.
Background
[0002] For parallel-connected semiconductor elements,
15 currents flowing through the individual semiconductor
elements are not equal to one another during the operation
of an inverter because of a variation in characteristic
among the semiconductor elements, or in wiring between the
parallel-connected semiconductor elements. In this case, a
20 loss in each of the semiconductor elements causes a
temperature imbalance between the semiconductor elements.
As a result, a particular semiconductor element becomes
high in temperature. If this state continues, the thermal
cycle life of the semiconductor element is shortened,
25 thereby making it highly likely that the particular
semiconductor element fails in the worst case.
[0003] To solve the above problem, Patent Literature 1
described below discloses a technique of alternate control
that selects an on-duty element and an off-duty element
30 from a plurality of semiconductor elements and periodically
alternates a driving signal between the on-duty element and
the off-duty element, such that the imbalance of loads on
the semiconductor elements used in parallel are eliminated
3
to equalize the loads, thereby preventing the degradation
of a particular semiconductor element. In Patent
Literature 1, the word "loads" included in the term
"imbalance of loads" is not used to mean "targets to be
5 supplied with power", but is used to mean "damage".
Citation List
Patent Literature
[0004] Patent Literature 1: Japanese Patent Application
10 Laid-open No. 2017-55259
Summary
Technical Problem
[0005] The technique disclosed in Patent Literature 1
15 described above can eliminate the imbalance of loads on the
semiconductor elements to equalize the loads.
Unfortunately, the alternate control that periodically
alternates the on-duty element and the off-duty element, as
described in Patent Literature 1, fails to maintain the
20 temperature balance between the semiconductor elements.
[0006] For the technique disclosed in Patent Literature
1, the on-duty element and the off-duty element are
alternately driven without being driven simultaneously.
Given that a conduction loss in a semiconductor element is
25 in proportion to the square of the current flowing through
the semiconductor element, driving the on-duty element and
the off-duty element simultaneously provides a smaller
conduction loss. When the technique disclosed in Patent
Literature 1 is applied, thus, there is a problem of
30 increase in a loss in each individual semiconductor element.
[0007] The present invention has been achieved to solve
the above problems, and an object of the present invention
is to provide a parallel driving device that, when driving
4
a plurality of semiconductor elements in parallel, can
minimize an increase in loss in a semiconductor element,
and can also maintain the temperature balance between the
semiconductor elements.
5
Solution to Problem
[0008] In order to solve the above problems and achieve
the object, the present invention is a parallel driving
device to drive a plurality of semiconductor elements
10 connected in parallel. The parallel driving device
includes a control unit and a driving circuit. The control
unit detects a temperature difference between the
semiconductor elements on the basis of detected values
provided by temperature sensors that detect temperatures of
15 the individual semiconductor elements. The control unit
generates a control signal for changing a timing at which
to turn on a first semiconductor element specified from the
semiconductor elements on the basis of the temperature
difference. The driving circuit generates a first driving
20 signal for driving the semiconductor elements, and
generates a second driving signal that is the first driving
signal delayed on a basis of the control signal, and
applies the second driving signal to the first
semiconductor element.
25
Advantageous Effects of Invention
[0009] The parallel driving device according to the
present invention has an effect of minimizing an increase
in loss in the semiconductor element and also maintaining
30 the temperature balance between the semiconductor elements
when driving the semiconductor elements in parallel.
Brief Description of Drawings
5
[0010] FIG. 1 is a diagram illustrating a configuration
example of a power conversion device including a parallel
driving device according to a first embodiment.
FIG. 2 is a diagram illustrating a detailed
5 configuration of the parallel driving device according to
the first embodiment along with semiconductor elements that
are targets to be driven.
FIG. 3 is a time chart for explaining operation of the
relevant parts in the first embodiment.
10 FIG. 4 shows waveform diagrams illustrating the
operating state of the semiconductor elements at three time
points of the time chart illustrated in FIG. 3.
FIG. 5 is a diagram illustrating a detailed
configuration of a parallel driving device according to a
15 second embodiment along with the semiconductor elements
that are targets to be driven.
FIG. 6 is a diagram illustrating loss characteristics
of a semiconductor element for explaining operation of the
parallel driving device according to the second embodiment.
20 FIG. 7 shows waveform diagrams illustrating the
operating state of the semiconductor elements that operate
in accordance with a first control method in the second
embodiment.
FIG. 8 shows waveform diagrams illustrating the
25 operating state of the semiconductor elements that operate
in accordance with a second control method in the second
embodiment.
FIG. 9 is a diagram illustrating a configuration
example of a general constant-voltage driving circuit.
30 FIG. 10 is a waveform diagram for explaining operation
of the constant-voltage driving circuit illustrated in FIG.
9.
FIG. 11 is a diagram illustrating a configuration
6
example of a constant-current driving circuit in a third
embodiment.
FIG. 12 is a waveform diagram for explaining operation
of the constant-current driving circuit illustrated in FIG.
5 11.
FIG. 13 is a diagram illustrating loss characteristics
of semiconductor elements when the semiconductor elements
are driven using the constant-current driving circuit in
the third embodiment.
10 FIG. 14 is a block diagram illustrating an example of
the hardware configuration to implement functions of the
control unit in the first to third embodiments.
FIG. 15 is a block diagram illustrating another
example of the hardware configuration to implement the
15 functions of the control unit in the first to third
embodiments.
Description of Embodiments
[0011] A parallel driving device and a power conversion
20 device according to embodiments of the present invention
will be described in detail below with reference to the
accompanying drawings. The present invention is not
limited to the embodiments described below.
[0012] First embodiment.
25 FIG. 1 is a diagram illustrating a configuration
example of a power conversion device 100 including a
parallel driving device 50 according to a first embodiment.
FIG. 2 is a diagram illustrating a detailed configuration
of the parallel driving device 50 according to the first
30 embodiment along with semiconductor elements 1a and 1b that
are targets to be driven.
[0013] In FIG. 1, the power conversion device 100
according to the first embodiment includes an inverter
7
circuit 1 and the parallel driving device 50. A DC power
supply 110 is a source of DC-power to apply a DC voltage to
the inverter circuit 1. The DC power supply 110 can be a
converter that converts an AC voltage output from an
5 external AC power supply (not illustrated) to a DC voltage.
The inverter circuit 1 is a power conversion circuit to
convert DC power supplied from the DC power supply 110,
into AC power. The inverter circuit 1 is provided with
semiconductor elements 1a, 1b, 1c, 1d, 2a, 2b, 2c, 2d, 3a,
10 3b, 3c, and 3d. A motor 80, which is a load, is connected
to output terminals of the inverter circuit 1. The motor
80 is driven with AC power supplied from the inverter
circuit 1. Examples of the motor 80 include an induction
motor or a synchronous motor.
15 [0014] In the inverter circuit 1, the semiconductor
element 1a and the semiconductor element 1b are connected
in parallel to form a U-phase upper arm, while the
semiconductor element 1c and the semiconductor element 1d
are connected in parallel to form a U-phase lower arm. The
20 term "upper arm" indicates a semiconductor element or a
group of semiconductor elements connected to the positive
side or higher potential side of the DC power supply 110.
The term "lower arm" indicates a semiconductor element or a
group of semiconductor elements connected to the negative
25 side or lower potential side of the DC power supply 110. A
circuit having the upper and lower arms connected in series
is referred to as "leg".
[0015] The same applies to a V-phase and a W-phase.
Similarly, as described below, the semiconductor element 2a
30 and the semiconductor element 2b are connected in parallel
to form a V-phase upper arm, while the semiconductor
element 2c and the semiconductor element 2d are connected
in parallel to form a V-phase lower arm. The semiconductor
8
element 3a and the semiconductor element 3b are connected
in parallel to form a W-phase upper arm, while the
semiconductor element 3c and the semiconductor element 3d
are connected in parallel to form a W-phase lower arm.
5 [0016] The inverter circuit 1 is a three-phase inverter
circuit including three legs each having the seriesconnected upper and lower arms for the corresponding phase.
A diode is connected in inverse parallel to each of the
semiconductor elements 1a to 1d, 2a to 2d, and 3a to 3d.
10 FIG. 1 illustrates Insulated Gate Bipolar Transistors
(IGBTs) as examples of the semiconductor elements. However,
the semiconductor elements are not limited thereto. MetalOxide-Semiconductor Field-Effect Transistors (MOSFETs)
instead of the IGBTs can be used as the semiconductor
15 elements.
[0017] The parallel driving device 50 is a device that
drives a plurality of parallel-connected semiconductor
elements. The parallel driving device 50 includes a gate
driving circuit 2 that is a driving circuit, and a control
20 unit 10. The control unit 10 generates a control signal 5
for controlling each of the semiconductor elements 1a to 1d,
2a to 2d, and 3a to 3d, and outputs the control signal 5 to
the gate driving circuit 2. On the basis of the control
signal 5, the gate driving circuit 2 generates a driving
25 signal 6 for driving each of the semiconductor elements 1a
to 1d, 2a to 2d, and 3a to 3d, and outputs the driving
signal 6 to the inverter circuit 1. FIG. 1 illustrates an
example case where the target to be driven by the parallel
driving device 50 is a three-phase inverter circuit.
30 However, the target is not limited thereto. The target to
be driven by the parallel driving device 50 can be a
single-phase inverter circuit including two legs, or a
half-bridge circuit including a single leg.
9
[0018] For ease of explanation, FIG. 2 illustrates only
some of the units of the inverter circuit 1, the gate
driving circuit 2, and the control unit 10, the illustrated
units being relevant to the description of the outline of
5 the first embodiment. Specifically, the control unit 10
includes a gate control unit 3 and a temperature difference
calculator 4. The gate driving circuit 2 includes a first
driving circuit 21 and a second driving circuit 22. The
second driving circuit 22 includes a first circuit 22a and
10 a second circuit 22b. The semiconductor element 1a is
accommodated in a module 12a. The semiconductor element 1b
is accommodated in a module 12b. In the module 12a, a
temperature sensor 8a to detect the temperature of the
semiconductor element 1a is provided. In the module 12b, a
15 temperature sensor 8b to detect the temperature of the
semiconductor element 1b is provided.
[0019] Although it is most desirable to detect the
temperature of an on-chip diode as a temperature of the
semiconductor element itself, the temperature to detect can
20 be the temperature of a substrate having a semiconductor
element installed thereon, or the temperature of a heat
sink having a module attached thereto. To sum up,
temperatures of any sections that can determine a
difference in temperature between a plurality of
25 semiconductor elements can be detected.
[0020] Next, the operation of the parallel driving
device 50 according to the first embodiment is described
with further reference to FIGs. 3 and 4 in addition to FIG.
2. FIG. 3 is a time chart for explaining operation of the
30 relevant parts in the first embodiment. FIG. 4 shows
waveform diagrams illustrating the operating state of the
semiconductor elements 1a and 1b at three time points of
the time chart illustrated in FIG. 3.
10
[0021] The temperature sensor 8a detects the temperature
of the semiconductor element 1a. The temperature sensor 8b
detects the temperature of the semiconductor element 1b. A
detected value Ta by the temperature sensor 8a and a
5 detected value Tb by the temperature sensor 8b are input to
the temperature difference calculator 4. The temperature
difference calculator 4 calculates an absolute value |TbTa| that is a difference between the detected value Tb and
the detected value Ta. This absolute value |Tb-Ta| is
10 represented as ΔT. ΔT is referred to as "temperature
difference". Information about the temperature difference
ΔT is transmitted to the gate control unit 3. The gate
control unit 3 generates the control signal 5 on the basis
of the temperature difference ΔT. The control signal 5
15 includes a signal for generating a voltage to be applied to
the motor 80 to drive the motor 80, and in addition,
includes a signal for changing the timing at which to turn
on a particular semiconductor element.
[0022] On the basis of the control signal 5 input to the
20 gate driving circuit 2, the gate driving circuit 2 changes
the timing at which to turn on the semiconductor element 1a
or the semiconductor element 1b. For example, a
semiconductor element having been determined to have a
relatively high temperature is driven in accordance with
25 the driving signal 6 for delaying the turn-on timing, while
a semiconductor element having been determined not to have
a relatively high temperature is driven in accordance with
a normal driving signal 6 without a delay control.
[0023] A signal generated by the first driving circuit
30 21 is applied to a gate of the semiconductor element 1a
through the first circuit 22a of the second driving circuit
22, and is also applied to a gate of the semiconductor
element 1b through the second circuit 22b of the second
11
driving circuit 22. The first circuit 22a and the second
circuit 22b can be configured in any manner. An example of
the configuration is described as follows. Each of the
first circuit 22a and the second circuit 22b includes a
5 non-delay circuit to allow a first driving signal generated
by the first driving circuit 21 to pass through the nondelay circuit without a delay, and a delay circuit to delay
the first driving signal generated by the first driving
circuit 21 and output a second driving signal that is the
10 delayed first signal. These non-delay circuit and delay
circuit are connected in parallel to each other. Normally,
a driving signal is output via the non-delay circuit. When
a semiconductor element is determined to have a relatively
high temperature, a driving signal is output via the delay
15 circuit.
[0024] The time chart in FIG. 3 illustrates a state in
which the temperature difference between the semiconductor
elements 1a and 1b increases with the lapse of time. The
upper portion of the time chart illustrates variations in
20 the detected values Ta and Tb of temperatures of the
semiconductor elements 1a and 1b detected by the
temperature sensors 8a and 8b, respectively. The lower
portion of the time chart illustrates a variation in the
temperature difference ΔT calculated by the temperature
25 difference calculator 4. The time chart shows three time
points T0, T1, and T2 on the horizontal axis representing
time to distinguish whether the semiconductor elements 1a
and 1b are in the initial state immediately after the start
of operation, or in the state after the lapse of a certain
30 time period, or in the state in which the above delay
control is active with the increasing temperature
difference increased.
[0025] FIG. 4 illustrates a gate voltage Vge to be
12
applied to the gate of each of the semiconductor elements
1a and 1b, a collector-emitter voltage Vce to be applied
between a collector and an emitter of each of the
semiconductor elements 1a and 1b, and a collector current
5 Ic flowing to the collector of each of the semiconductor
elements 1a and 1b. FIG. 4 illustrates the operating
waveform of the semiconductor element 1a with the dotted
line, and illustrates the operating waveform of the
semiconductor element 1b with the solid line.
10 [0026] In the initial state immediately after the start
of operation, as illustrated in FIG. 4(a), there is hardly
any difference between the operating waveforms of the
semiconductor elements 1a and 1b. In contrast, after a
certain period of time has elapsed since the start of
15 operation of the inverter circuit 1, a temperature
difference between the semiconductor elements 1a and 1b is
caused by various factors. In general, when a
semiconductor has a higher temperature, a current flows
through the semiconductor more easily. In FIG. 3, at and
20 around the time T1, the semiconductor element 1b has a
higher temperature than that of the semiconductor element
1a. As a result, as illustrated in FIG. 4(b), the
collector current Ic is higher in the semiconductor element
1b than in the semiconductor element 1a although the gate
25 voltage Vge is equal in both the semiconductor elements 1a
and 1b. In view of the above, in the first embodiment,
when the temperature difference ΔT exceeds a first
threshold that is a threshold Tth1, the semiconductor
element 1b is driven by using a method of the present
30 application. For the purpose of specifying the
semiconductor element 1b with the temperature difference ΔT
having exceeded the threshold Tth1, the semiconductor
element 1b in this state is sometimes referred to as "first
13
semiconductor element".
[0027] FIG. 4(c) illustrates the operating waveform
during the operation period in accordance with the method
of the present application. During the operation period in
5 accordance with the method of the present application, the
delay circuit in the second circuit 22b operates, so that
the semiconductor element 1b having a higher temperature is
delayed in being turned on. Due to this operation, a
current flows only through the semiconductor element 1a
10 during a certain period of time since the semiconductor
element 1a is turned on. For this reason, the current
distribution is concentrated on the semiconductor element
1a having a lower temperature. As a result, while a loss
in the semiconductor element 1a increases, a loss in the
15 semiconductor element 1b decreases. Accordingly, the
temperature difference ΔT decreases, and consequently the
temperature balance between the semiconductor elements 1a
and 1b is maintained. Thereafter, when it is observed that
the temperature difference ΔT has decreased below the
20 second threshold that is a threshold Tth2, the operation
returns to a normal operation. The threshold Tth2 is set
to reduce the fluctuation of the operation. The value of
the threshold Tth2 is smaller than that of the threshold
Tth1. When the temperature difference ΔT exceeds the
25 threshold Tth1 again after the operation has returned to
the normal operation, the method of the present application
is activated. Each time the temperature difference ΔT
exceeds the threshold Tth1, the method of the present
application is activated. Since no turn-on loss occurs in
30 a semiconductor element delayed in being turned on, the
temperature of this semiconductor element decreases more
than the semiconductor element having been turned on
earlier. For this reason, the temperature difference
14
between the semiconductor elements 1a and 1b is reduced,
and consequently the temperature balance between the
semiconductor elements 1a and 1b can be maintained. This
configuration also extends the power cycle life of the
5 semiconductor elements 1a and 1b, and accordingly can
improve the reliability of the semiconductor elements 1a
and 1b. Further, this configuration can simplify a cooler
that cools the semiconductor elements 1a and 1b, and thus
can contribute to a reduction in costs of the power
10 conversion device.
[0028] The above descriptions have been made for the
case where the semiconductor elements 1a and 1b of the Uphase upper arm are driven. The same control is also
executed when the semiconductor elements 1c and 1d of the
15 U-phase lower arm are driven. The same applies to the Vphase and the W-phase. The method of the present
application is also applied individually and independently
to the upper arm and the lower arm for the U, V, and Wphases. This enables the inverter circuit 1 provided with
20 a plurality of semiconductor elements to maintain the
temperature balance between the semiconductor elements 1a
and 1b simply and autonomously without executing
complicated control.
[0029] FIG. 1 illustrates an example case where each of
25 the upper and lower arms for each of the U, V, and W-phases
forming the inverter circuit 1 has the two parallelconnected semiconductor elements. However, the number of
parallel-connected semiconductor elements is not limited to
two. Each of the upper and lower arms for each of the U, V,
30 and W-phases can have three or more parallel-connected
semiconductor elements. In a case where the number of
parallel-connected semiconductor elements is equal to or
larger than three, temperature differences among these
15
semiconductor elements can be detected. Alternatively, a
temperature difference between the maximum temperature and
the minimum temperature of the semiconductor elements can
be detected. Alternatively, a temperature difference
5 between the maximum temperature of a semiconductor element
and the average temperature of all semiconductor elements
can be detected. In these cases, the first semiconductor
element can be defined as a semiconductor element having
the maximum temperature with the temperature difference
10 exceeding the threshold.
[0030] As described above, the parallel driving device
according to the first embodiment generates a control
signal for changing the timing at which to turn on the
first semiconductor element specified from a plurality of
15 semiconductor elements on the basis of a temperature
difference between the semiconductor elements. Then, the
parallel driving device generates a first driving signal
for driving the semiconductor elements, and generates a
second driving signal that is the first driving signal
20 delayed on the basis of the control signal, and applies the
second driving signal to the first semiconductor element.
This can maintain the temperature balance between the
semiconductor elements and minimize an increase in loss in
the semiconductor element, as well.
25 [0031] The method according to the first embodiment
delays turning on a semiconductor element having a higher
temperature only when the temperature difference exceeds a
threshold, and drives all of the parallel-connected
semiconductor elements together when the temperature
30 difference does not exceed the threshold. As a result, an
increase in the conduction loss can be minimized as
compared to the technique disclosed in Patent Literature 1
in which the on-duty element and the off-duty element are
16
alternately driven.
[0032] Second embodiment.
FIG. 5 is a diagram illustrating the detailed
configuration of a parallel driving device 50A according to
5 a second embodiment along with the semiconductor elements
1a and 1b that are targets to be driven. In FIG. 5, in the
parallel driving device 50A according to the second
embodiment, the gate driving circuit 2, included in the
parallel driving device 50 according to the first
10 embodiment illustrated in FIG. 2, is replaced with a gate
driving circuit 2A. In the gate driving circuit 2A, the
first driving circuit 21 is replaced with a driving circuit
23 having a voltage variable function. Other
configurations are the same as or identical to those of the
15 first embodiment, the same or identical constituent
elements are denoted by like reference signs, and redundant
explanations thereof are omitted.
[0033] FIG. 6 is a diagram illustrating loss
characteristics of a semiconductor element for explaining
20 operation of the parallel driving device 50A according to
the second embodiment. In FIG. 6, the horizontal axis
represents the collector current Ic, while the vertical
axis represents a turn-on loss Eon. That is, FIG. 6
illustrates dependence of the turn-on loss Eon in a general
25 semiconductor element on the current. In FIG. 6, the thick
solid curve shows the loss characteristics of a single
semiconductor element, and is a downward convex curve. The
horizontal axis and the vertical axis in FIG. 6 are
normalized. The turn-on loss relative to the rated current
30 "1×Ic" is expressed as "1×E". In FIG. 6, the thin solid
curve shows the loss characteristics when two semiconductor
elements are connected in parallel. Since the two
semiconductor elements connected in parallel operate
17
simultaneously, the current that flows through the two
semiconductor elements is twice a current flowing when a
single semiconductor element operates. For this reason,
the loss curve for the two semiconductor elements connected
5 in parallel is a downward convex curve interconnecting the
origin O and the point P. At the point P, the double turnon loss "2×E" is provided relative to the current "2×Ic"
that is twice the rated current.
[0034] The first embodiment delays turning on the
10 specified, first semiconductor element on the basis of the
temperature difference ΔT, thereby maintaining the
temperature balance. As discussed above, dependence of the
turn-on loss Eon in a general semiconductor element on the
current is shown by the downward convex curve. Accordingly,
15 as illustrated in FIG. 6, the loss curve for two
semiconductor elements connected in parallel has a
characteristic of being located below the loss curve for a
single semiconductor element. Consider carrying a current
of "0.7×Ic" through each semiconductor element in driving
20 the two semiconductor elements in parallel. When these two
semiconductor elements are not driven in parallel, a
current of "1.4×Ic" flows through the one semiconductor
element. In the case of the two semiconductor elements not
being driven in parallel, thus, the operation point is
25 represented as "Q". In contrast, when the two
semiconductor elements are driven in parallel, the
operation point is represented as "R". It is thus
understood that the turn-on loss is lower when the
semiconductor elements are driven in parallel. Conversely,
30 in the case of carrying equal currents through the
semiconductor elements, the turn-on loss increases when the
semiconductor elements are not driven in parallel, as
compared to when the semiconductor elements are driven in
18
parallel.
[0035] In view of the above, the second embodiment
proposes a method to reduce the turn-on loss by setting a
positive bias voltage of the gate (hereinafter, "gate
5 voltage") higher than the normal value in delaying turning
on a semiconductor element having a higher temperature.
The gate voltage is varied by the driving circuit 23 having
a voltage variable function illustrated in FIG. 5. The
gate voltage is varied when the temperature difference ΔT
10 is in excess of the threshold Tth1. The gate voltage is
varied for both the semiconductor elements 1a and 1b.
[0036] FIG. 7 shows waveform diagrams illustrating the
operating state of the semiconductor elements 1a and 1b
that operate in accordance with a first control method in
15 the second embodiment. There are various possible timings
at which to vary the gate voltage. In the second
embodiment, the gate voltage is varied simultaneously with
the timing at which to turn on the semiconductor element.
FIG. 7(c) illustrates the operating waveform when the gate
20 voltage is varied. The operating waveforms illustrated in
FIGs. 7(a) and 7(b) are identical to those illustrated in
FIGs. 4.
[0037] It is preferable to select the value of gate
voltage in such a manner as to provide a loss curve lying
25 below the loss curve of FIG. 6 for the two semiconductor
elements driven in parallel. An example of that loss curve
thus provided is shown with the dot-and-dash line in FIG. 6.
On the loss curve shown with the dot-and-dash line, the
operation point is represented as "S" when the current of
30 "1.4×Ic" flows. It is thus understood that the turn-on
loss at the operation point "S" is decreased relative to
that at the operation point "R" when the semiconductor
elements are driven in parallel.
19
[0038] When the gate voltage is varied simultaneously
with the timing at which to turn on the semiconductor
element, the turn-on speed increases as compared to when
the gate voltage is not varied. Accordingly, the effect of
5 further reducing the turn-on loss is obtained. The effect
of reducing the conduction loss is also obtained by setting
the gate voltage higher than the normal value.
[0039] FIG. 8 shows waveform diagrams illustrating the
operating state of the semiconductor elements 1a and 1b
10 that operate in accordance with a second control method in
the second embodiment. In the second control method, as
illustrated in FIG. 8(c), the gate voltage is increased
after the turn-on period ends. The operating waveforms
illustrated in FIGs. 8(a) and 8(b) are identical to those
15 illustrated in FIGs. 4 and 7.
[0040] In a case where the gate voltage is increased at
the turn-on timing, there is a possibility that the current
may exceed the maximum turn-on current, and then the
overcurrent detection function may become active, or the
20 semiconductor elements may be subjected to an unintentional
stress. In contrast, when the gate voltage is increased
after the turn-on period ends, then the increase in the
turn-on speed can be minimized. As a result, the effect of
reducing the conduction loss is obtained, and preventing
25 the turn-on current from exceeding the maximum value, as
well.
[0041] As described above, the parallel driving device
according to the second embodiment includes the driving
circuit according to the first embodiment with a voltage
30 variable function added. When the first semiconductor
element has been specified, at the time of applying the
first and second driving signals to the semiconductor
elements, the driving circuit having a voltage variable
20
function increases the voltage level of the first and
second driving signals at the timing at which to turn on
the semiconductor elements, such that the voltage level
becomes higher than the voltage level of the first and
5 second driving signals when the first semiconductor element
has not been specified. As a result, the effects of
reducing the turn-on loss and the conduction loss can be
obtained.
[0042] In the parallel driving device according to the
10 second embodiment, when the first semiconductor element has
been specified, at the time of applying the first and
second driving signals to the semiconductor elements, the
driving circuit having a voltage variable function
increases the voltage level of the first and second driving
15 signals after the semiconductor element is turned on, such
that the voltage level becomes higher than the voltage
level of the first and second driving signals when the
first semiconductor element has not been specified. As a
result, the effect of reducing the conduction loss can be
20 obtained.
[0043] Third embodiment.
As described in the second embodiment, dependence of
the turn-on loss in a semiconductor element on the current
is shown by a downward concave curve. This characteristic
25 is often observed in general when a driving circuit
referred to as "constant-voltage driving circuit" is used.
The turn-on loss decreases as the turn-on speed is higher.
The turn-on loss increases as the turn-on speed is lower.
One of the characteristics to determine the turn-on speed
30 is a current rising speed. First, the turn-on
characteristics of a semiconductor element are described
below.
[0044] A voltage to be applied to the gate needs to be
21
increased to turn on the semiconductor element. A self
arc-extinguishing semiconductor element, which is
preferably used as a power semiconductor element, has a
parasitic capacitance referred to as "gate capacitance".
5 For the self arc-extinguishing semiconductor element, the
gate capacitance is charged to thereby increase the gate
voltage. When the gate voltage exceeds a gate threshold
voltage Vth, a current starts flowing. The self arcextinguishing semiconductor element has characteristics of
10 providing a higher current rising speed at the time of
turn-on as the gate charging current is larger before the
gate voltage reaches the gate threshold voltage Vth.
[0045] FIG. 9 is a diagram illustrating a configuration
example of a general constant-voltage driving circuit 30.
15 FIG. 10 is a waveform diagram for explaining operation of
the constant-voltage driving circuit 30 illustrated in FIG.
9. The first driving circuit 21 illustrated in FIG. 2 is a
component corresponding to the constant-voltage driving
circuit 30 illustrated in FIG. 9.
20 [0046] FIG. 10 illustrates a gate charging current, a
gate voltage, and a gate control signal in order from the
upper portion. In a case where the constant-voltage
driving circuit is used, the gate charging current is
maximized immediately after the start of application of the
25 gate voltage as illustrated in FIG. 10. In contrast, the
gate charging current at and around the gate threshold
voltage Vth is relatively low. Due to this characteristic,
dependence of the turn-on loss on the current is shown by a
downward convex curve as illustrated in FIG. 6. As
30 described in the second embodiment, this characteristic
results in an increase in the loss in the inverter circuit
in its entirety.
[0047] In view of this, the third embodiment uses a
22
driving circuit that provides an upward convex curve
showing dependence of the turn-on loss on the current.
Specifically, a constant-current driving circuit is used.
FIG. 11 is a diagram illustrating a configuration example
5 of a constant-current driving circuit 32 in the third
embodiment. FIG. 12 is a waveform diagram for explaining
operation of the constant-current driving circuit 32
illustrated in FIG. 11.
[0048] FIG. 12 illustrates a gate charging current, a
10 gate voltage, and a gate control signal in order from the
upper portion. In a case where the constant-current
driving circuit 32 is used, the gate charging current is
maintained approximately at a constant value immediately
after the start of application of the gate voltage as
15 illustrated in FIG. 12. Thus, a gate charging current Igc
flowing from the constant-current driving circuit 32 at and
around the gate threshold voltage Vth is higher than a gate
charging current Igv flowing from the constant-voltage
driving circuit 30 at and around the same gate threshold
20 voltage Vth. At the gate threshold voltage Vth, a self
arc-extinguishing semiconductor element is turned on.
[0049] FIG. 13 is a diagram illustrating loss
characteristics of semiconductor elements when the
semiconductor elements are driven using the constant25 current driving circuit 32 in the third embodiment. The
loss characteristics of the semiconductor elements driven
using the constant-current driving circuit 32 are shown by
an upward convex curve as illustrated in FIG. 13.
Similarly to FIG. 6, the loss characteristic of a single
30 semiconductor element are shown with the thick solid line
and the thick dotted line, while the loss characteristic of
two semiconductor elements connected in parallel are shown
with the thin solid line. Both the loss characteristics
23
are shown by upward convex curves. One of the curves
showing the loss characteristic of a single semiconductor
element lies below the other curve showing the loss
characteristic of two semiconductor elements connected in
5 parallel. In the case of use of the constant-current
driving circuit 32, therefore, the turn-on loss does not
increase even though the semiconductor element having a
lower temperature bears a burden of being turned on as the
semiconductor element having a higher temperature is
10 delayed in being turned on. The reasons why the loss
characteristics are shown by the upward convex curves can
be explained as follows.
[0050] For the constant-voltage driving circuit 30, the
gate voltage increases in such a manner as to draw an
15 upward convex curve as illustrated in FIG. 10. The reason
for this is that the gate capacitance is charged so as to
increase in accordance with a time constant CR that is the
product of a gate resistance R and a gate capacitance C.
In contrast, the constant-current driving circuit 32 has a
20 characteristic of increasing the gate voltage linearly as
the gate capacitance is charged with a constant gate
current. In general, the rate of increase in the current
relative to the increase in the gate voltage, which is
regarded as a transmission characteristic of a self arc25 extinguishing semiconductor element, is attributable to the
characteristics of the self arc-extinguishing semiconductor
element.
[0051] For the constant-voltage driving circuit 30, the
gate voltage increases along an upward convex curve in
30 accordance with the time constant CR. Due to this
characteristic, an increase in the gate voltage with
respect to time is gentle after the gate voltage exceeds
the gate threshold voltage Vth. Accordingly, the rate of
24
increase in the current is so gentle that the current rises
slowly. In the constant-current driving circuit 32, in
contrast, the gate voltage increases linearly, such that
the increase in the gate voltage with respect to time after
5 the gate voltage exceeds the gate threshold voltage Vth is
greater than that in the constant-voltage driving circuit
30. Accordingly, the rate of increase in the current
becomes higher than that of the constant-voltage driving
circuit 30, and the current rises faster accordingly. Thus,
10 the turn-on loss in the constant-current driving circuit 32
is decreased more as the switching current is increased
than in the constant-voltage driving circuit 30. That is,
the turn-on loss is shown by the upward convex curve as
illustrated in FIG. 13.
15 [0052] As explained above, the parallel driving device
according to the third embodiment uses the constant-current
driving circuit to form the gate driving circuit. Due to
this configuration, the effect of further reducing the loss
in the inverter circuit in its entirety can be obtained.
20 [0053] Next, the hardware configuration to implement the
functions of the control unit 10 according to the first to
third embodiments is described with reference to the
drawings of FIGs. 14 and 15. FIG. 14 is a block diagram
illustrating an example of the hardware configuration to
25 implement the functions of the control unit 10 in the first
to third embodiments. FIG. 15 is a block diagram
illustrating another example of the hardware configuration
to implement the functions of the control unit 10 in the
first to third embodiments.
30 [0054] In order to implement the functions of the
control unit 10 according to the first to third embodiments,
as illustrated in FIG. 14, the hardware configuration can
be configured to include a processor 300 to perform
25
calculation, a memory 302 to store therein programs to be
read by the processor 300, and an interface 304 through
which a signal is input/output.
[0055] The processor 300 may be calculation means such
5 as a calculation device, a microprocessor, a microcomputer,
a CPU (Central Processing Unit), or a DSP (Digital Signal
Processor). As the memory 302, a nonvolatile or volatile
semiconductor memory such as a RAM (Random Access Memory),
a ROM (Read Only Memory), a flash memory, an EPROM
(Erasable Programmable ROM), and an EEPROM® 10 (Electrically
EPROM), a magnetic disk, a flexible disk, an optical disk,
a compact disk, a MiniDisk, and a DVD (Digital Versatile
Disk) can be exemplified.
[0056] The memory 302 has stored therein programs that
15 execute the functions of the control unit 10 according to
the first to third embodiments. The processor 300
transmits or receives necessary information through the
interface 304, executes the programs stored in the memory
302, references tables stored in the memory 302, and can
20 thereby perform the processing described above. Results of
the calculation performed by the processor 300 can be
stored in the memory 302.
[0057] The processor 300 and the memory 302 illustrated
in FIG. 14 can be replaced with a processing circuitry 305.
25 A single circuit, a combined circuit, an ASIC (Application
Specific Integrated Circuit), an FPGA (Field-Programmable
Gate Array) or a combination thereof corresponds to the
processing circuitry 305. Information to be input to or
output from the processing circuitry 305 can be transmitted
30 or received through the interface 304.
[0058] The configurations described in the above
embodiments are only examples of the content of the present
invention. The configurations can be combined with other
26
well-known techniques, and part of each of the
configurations can be omitted or modified without departing
from the scope of the present invention.
5 Reference Signs List
[0059] 1 inverter circuit; 1a to 1d, 2a to 2d, 3a to 3d
semiconductor element; 2, 2A gate driving circuit; 3 gate
control unit; 4 temperature difference calculator; 5
control signal; 6 driving signal; 8a, 8b temperature
10 sensor; 10 control unit; 12a, 12b module; 21 first
driving circuit; 22 second driving circuit; 22a first
circuit; 22b second circuit; 23 driving circuit with
voltage variable function; 30 constant-voltage driving
circuit; 32 constant-current driving circuit; 50, 50A
15 parallel driving device; 80 motor; 100 power conversion
device; 110 DC power supply; 300 processor; 302 memory;
304 interface; 305 processing circuitry.
27
We Claim :
1. A parallel driving device to drive a plurality of
parallel-connected semiconductor elements, the parallel
driving device comprising:
5 a control unit to detect a temperature difference
between the semiconductor elements on a basis of detected
values provided by temperature sensors, the temperature
sensors detecting temperatures of the individual
semiconductor elements, and to generate a control signal
10 for changing a timing at which to turn on a first
semiconductor element specified from the semiconductor
elements on the basis of the temperature difference; and
a driving circuit to generate a first driving signal
for driving the semiconductor elements, and to generate a
15 second driving signal that is the first driving signal
delayed on the basis of the control signal and apply the
second driving signal to the first semiconductor element.
2. The parallel driving device according to claim 1,
20 wherein
when the number of the parallel-connected
semiconductor elements is two, the temperature difference
is a difference in temperature between the two
semiconductor elements, and the first semiconductor element
25 is a semiconductor element with the temperature difference
exceeding a threshold, and
when the number of the parallel-connected
semiconductor elements is equal to or larger than three,
the temperature difference is a difference between maximum
30 and minimum temperatures of the semiconductor elements, or
is a difference between a maximum temperature of a
semiconductor element and an average temperature of all of
the semiconductor elements, and the first semiconductor
28
element is the semiconductor element having the maximum
temperature with the temperature difference exceeding a
threshold.
5 3. The parallel driving device according to claim 2,
wherein when the temperature difference exceeds a threshold,
the driving circuit applies the second driving signal to
the first semiconductor element, and when the temperature
difference decreases to a threshold or smaller, the driving
10 circuit applies the first driving signal to the first
semiconductor element.
4. The parallel driving device according to any one of
claims 1 to 3, wherein when the first semiconductor element
15 is specified,
in applying the first and second driving signals to
the semiconductor elements, the driving circuit increases a
voltage level of the first and second driving signals at a
timing at which to turn on the semiconductor elements, such
20 that the voltage level becomes higher than a voltage level
of the first and second driving signals when the first
semiconductor element is not specified.
5. The parallel driving device according to any one of
25 claims 1 to 3, wherein when the first semiconductor element
is specified,
in applying the first and second driving signals to
the semiconductor elements, the driving circuit increases a
voltage level of the first and second driving signals after
30 the semiconductor element is turned on, such that the
voltage level becomes higher than a voltage level of the
first and second driving signals when the first
semiconductor element is not specified.
29
6. The parallel driving device according to any one of
claims 1 to 5, wherein the driving circuit is a constantvoltage driving circuit.
5
7. The parallel driving device according to any one of
claims 1 to 3, wherein the driving circuit is a constantcurrent driving circuit.
8. A power conversion device comprising:
the parallel driving device according to any one of
claims 1 to 7; and
a power conversion circuit including the semiconductor
elements to be driven by the parallel driving device.