FIELD OF INVENTION:
The present invention relates generally to the field of semiconductor
device manufacturing and, more specifically, to digital circuit designing,
employing a novel gate engineered approach.
BACKGROUND AND PRIOR ART:
THE overwhelming growth of the metal oxide semiconductor field effect
transistor (MOSFET) technology in the last five decades can be attributed
to the scaling of device dimensions. The scaling has significantly
increased speed, functionality and packing density and' has reduced
power dissipation, chip cost etc. However, the continuation of scaling
below 22 nm technology node is extremely challenging due to short
channel effects (SCE), gate tunneling, leakage, and source/drain series
resistance. In literature most of the work focuses on reducing transistor
size to reduce circuit area but it leads to various aforementioned negative
effects. Since scaling the dimensions of MOS devices to enhance the
performance of devices is restricted by SCEs and other issues, therefore,
it is wise to go for the architectural changes in devices to enhance the
performance and to keep Moore's law valid for some more time.
Therefore, it is the need of the hour to develop devices with multifunctionality,
that is, development of single devices, which can realize a
full Boolean equation.
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The most common approach for digital circuit designing is based on the
static CMOS logic in which transistor count of a digital circuit grows
linearly with increasing number of input. A two input logic gate requires
atleast four transistors. A typical two input NAND/NOR gate needs four
transistors and an XOR/XNOR gate needs eight transistors for. Due to
self-loading effect the static CMOS based digital logic gates are limited to
four inputs only. Beyond four inputs, load capacitance is dominated by
intrinsic capacitance of the logic gate. Fig. 1 shows static CMOS based
NAND, NOR, and XOR gate.
To implement a compact digital design, various efforts have been made to
reduce the number of transistors in basic building blocks, like
NOR/NAND/XOR/AND/OR. Various design techniques are available to
reduce total transistor count requirement of a logic gate including ratioed
logic, pseudo-NMOS logic, transmission gate based logic, differential
cascade voltage switch logic (DCVSL), and dynamic gates etc. Most of
these techniques need either n-logic or p-logic blocks for evaluation of
inputs wherein p and n logic blocks are same as used in static CMOS
based gates. These techniques improve circuit area and self-loading effect
partially.
Fig. 2 illustrates basic concept of a dynamic logic gate. When "En" is low,
output is pre-charged to VDD via PMOS transistor "Mp". When "En" is
high NMOS transistor "Me" turns ON and output is conditionally pulled
down based on the inputs.
Roman Sordan et. al. made attempt to design Logic gates with a single
graphene transistor. Fig. 3 illustrates concept of logic gate design with a
single grapheme, transistor as proposed by Roman Sordan et. al. Here R
is the output resistance of the graphene transistor, which depends on
the gate voltage VG. Although this method realizes a two input NAND,
XOR, and OR logic gates with a single transistor, however, it needs an
input stage to ensure that applied gate voltage is the average of two input
voltages. This input stage results in an extra area penalty to the design.
In addition to that the operating voltage needed is 50 V, which is
significantly larger than the state of the art operating voltage currently
used for the submicron technology. Further, Roman Sordan et. al. does
not disclose whether his concept is extendable to design complex digital
circuits or not. Yuqing Xu et. al. also uses similar concept to design logic
gates with single molecular field effect transistors except the operating
voltage is smaller ranging from -2V to 2V. Fig. 4 shows the concept
proposed by Yuqing Xu et. al..
To the best of our knowledge and search, we could not find any prior art
employing gate engineering approach based single device implementing
any complete Boolean expression. Our invention/method proposed and
simulated gate engineered single devices implementing various Boolean
expressions representing various digital circuits, like, NOR, NAND, XOR,
FULL ADDER, MULTIPLEXER ETC.
SUMMARY OF THE INVENTIONThe
present invention provides a method for implementing any Boolean
expression with a single metal oxide field effect transistor (MOSFET).
The method uses an array of gate electrode patterns to implement
any Boolean expression wherein number of rows in the array is equal to
number of product terms in a Boolean expression while number of gate
patterns in a row is equal to numbers of input variable in the product
term of the corresponding row. All rows may have equal or unequal
number of gate patterns depending on the number of input variables in
different product terms. A single transistor is used for evaluation of a
Boolean expression that eliminates need of multiple transistors and
interconnects used for implementing different logic functions.
The method can use either a PMOS transistor or a NMOS
transistor to realize any Boolean expression. The base transistor, which
we call as an evaluation transistor, can have doped source/drain (S/D)
or metallic S/D) or any other technology for fabricating a MOSFET. In
realizing a circuit using our proposed invention, we can use PMOS
transistor as a base (evaluation transistor) and need an NMOS transistor
for discharging the output before an evaluation. The output node can get
charged through the evaluation transistor, depending on the values of
inputs. A Boolean expression can be realized by PMOS evaluation
transistor based structure by using complementary values of all
variables present in the Boolean equation. These complementary
variables will act as inputs (through gate pattern) for the PMOS
evaluation transistor. For example if an arbitrary target Boolean equation
is Y = AB + CD then inputs for PMOS evaluation transistor will be A', B',
C, and D\ This will be implemented by using two rows of gate electrode
patterns, one using A' and B' and the second row using C and DSimilarity, we can use a single NMOS transistor as a base
(evaluation transistor) and an additional PMOS transistor is used to precharge
output node to high value. The output node can get discharged
through the evaluation transistor, depending on the values of inputs. To
realize a Boolean equation by using a single NMOS transistor as a
evaluation transistor, the target Boolean equation is complemented first
and the resultant complemented values are used as inputs. For example
if the Boolean expression is Y=AB +CD. After complementing it becomes
YN = (AB +CD)' = A'C + AT)' + B'C +B?D\ Here A', B', C and D' will act as
inputs through gate pattern to the NMOS evaluation transistor.
Therefore, we need four rows of gate patterns with each row having two
gate patters to realize A'C\ A'D', B'C, and B'P', which finally implements
Y=AB +CD.
A Boolean expression can also be implemented by using an NMOS
evaluation transistor along with an additional NMOS pre-discharging
transistor. In this case, there is no need to complement the Boolean
expression, as has been done above. It remain same for the evaluation
i.e. YN = Y = AB +CD. However, the output will not be pulled to VDD, since
NMOS evaluation transistor cannot pass ' 1 ' efficiently. In this case, we
just need two rows to implement Y = AB +CD.
The additional pre-charging/ discharging transistor used in
realizing a Boolean equation can be replaced by using two evaluation
transistors in complementary mode. The complementary mode means
that NMOS evaluation and PMOS evaluations transistors are used
together. We tested our invention by developing NAND, NOR, XOR
circuits, adders etc. using our invention.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS:
Fig. 1 shows static CMOS based (a) NAND gate (b) NOR gate (c) XOR gate
circuits according to one aspect of the prior art;
Fig. 2 illustrate basic concept of dynamic gate according to another
aspect of the prior art;
FIG.3 shows a two-input logic gate incorporating one monolayer
grapheme transistor as proposed by Roman Sordan et. al. according to
another aspect of the prior art;
Fig. 4 shows design of a two-input logic gate with single molecular field
effect transistor as proposed by Yuqing Xu et. al. according to another
aspect of the prior art;
Fig. 5 shows the concept of a generalized Boolean equation
implementation with a single evaluation transistor having gate electrode
pattern array according to our proposed method wherein
Fig. 5a uses a single PMOS evaluation transistor with cylindrical
substrate;
Fig. 5b uses a single PMOS evaluation transistor with cuboidal
substrate;
Fig. 5c uses a single NMOS evaluation transistor with cylindrical
substrate;
Fig. 5d uses a single NMOS evaluation transistor with cuboidal
substrate;
Fig. 5e uses a single NMOS evaluation transistor with NMOS • predischarging
transistor;
Fig. 6a illustrates implementation of output sum (S) of a 1-bit full adder
according our proposed method;
Fig. 6b illustrates implementation of output, carry (Co) of a 1-bit full
adder according our proposed method;
Fig. 6(c) Simulated waveforms of the proposed full adder.
Fig. 7a shows implementation of a two input XOR gate according to our
proposed method;
Fig. 7b shows simulated waveforms of the proposed XOR gate in Fig. 7a;
Fig. 8a shows implementation of a two input NAND gate according to our
proposed method;
Fig. 8b shows simulated waveforms of the proposed NAND gate in Fig.
8a;
Fig. 9a shows implementation of a two input NOR gate according to our
proposed method;
Fig. 9b shows waveforms of the proposed NOR gate in Fig. 9a;
DESCRIPTION OF THE PREFERRED EMBODIMENTS:
•Our invention proposes a method to implement any Boolean equation byusing
a single evaluation transistor only. This method significantly
reduces area of any digital circuits representing that Boolean equation.
Instead of connecting different multiple transistors for designing a digital
circuit, out method patterns gate electrode/electrodes of an evaluation
transistor for designing a digital circuit.
Fig. 5 shows our proposed device (invention). to implement a general
Boolean equation. The evaluation device can be either a PMOS or an
NMOS transistor. In case of a PMOS transistor for evaluation of inputs,
output load capacitor is connected to an additional NMOS transistor
which discharges output when enable signal (En) goes high and output is
conditionally charged to VDD based on the state of inputs. When an
*
NMOS transistor is used for evaluation of inputs, the output is connected
to a PMOS transistor that pre-charges the output to VDD once enable (En)
becomes high and output discharges conditionally according to inputs.
Enable input is made high at the transition of any input and goes low
subsequently and output remains same or toggles based on the inputs of
the evaluation transistor. The proposed device uses an array of gate
electrode patterns for different inputs. The gap between two adjacent gate
patterns in a row of the array is set in such a way so that the complete
channel underlying the row is inverted when the all gate pattern invert
parts of their underlying channel in that row. In this way, the values of
inputs at gate patterns make evaluation transistor ON or OFF.
The channel substrate can be of any shape which can support parallel
rows of gate electrode pattern. For example Fig. 5a uses a cylindrical
substrate with gate patterns on the surface of the substrate. These gate
patterns are deposited after deposition of a gate oxide layer on the
substrate. Fig. 5b shows the use of a cubiodal shape substrate with
multiple gate pattern rows. Fig. 5c and Fig. 5d show the general concept
using with single NMOS evaluation. Fig. 5e show the generalized device
in static CMOS configuration.
Explanation: If the Boolean expression to be realized is Y = F (h, h,
I3, , In). The general expression for inputs of PMOS evaluation
transistor is Yp = F(h', h\ h\ , In') which is obtained by just replacing
inputs variables in the input expression by their complementary values.
If Yp is a sum of n product terms, then evaluation transistor gate
patterns have n rows with each row has number of gate patterns equal to
number of variables in any row. Fig 5a and 5b show general structure
with PMOS evaluation transistor.
Similarly, to realize a Boolean equation using NMOS evaluation
transistor, the inputs of NMOS evaluation transistor becomes YN = F (h,
h, I3, , In)' and if YN is sum of n product terms, then evaluation
transistor gate patterns have n rows with each row has number of gate
patterns equal to number of variables in any row. Fig 5c and 5d show
general structure with NMOS evaluation transistor. When NMOS
evaluation transistor is used with additional NMOS pre-discharging
transistor, then YN = Y = F (h, b, I3, , In) remains same and no
complementary operation is needed, however, output high value will not
be VDD, as NMOS is not better suited for the transfer of *1An example of implementation of a 1-bit full adder is shown in Fig. 6a
and Fig. 6b for Sum and Carry outputs of a 1-bit full adder circuit
respectively which are described as follow;
S = AB'Cj1 + A'BCj1 + A'B'Cj + ABC
Co = AB + BCj + ACj
Where A and B are two 1-bit inputs and G is input carry. S and C0 are
expression for Sum and Carry outputs. Corresponding expression for
PMOS evaluation transistor becomes
S(P) = A'BC + AB'C. + ABC- ' + Ai'Bn i '/C^ I
C(P) = A'B' + B'C.' + A'C"
The inputs to gate patterns of PMOS evaluation transistor are applied
according to equations 3 and 4. As can be seen from equation (3), the
Sum S(P) expression has four product„terms hence it will need four rows
of gate pattern. Each product term has three input variables that can be
realized by three gate pattern in each row. Therefore, the sum expression
is implemented by a 4 * 3 array of gate patterns as shown in Fig. 6a.
Similarly the carry output C0(P) expression is implemented by a 3X2
array of gate pattern as shown in Fig. 6b. Our invention is not limited to
1-bit adder only; we can implement different digital expressions by using
different gate pattern arrays. The simulated Output waveforms of the
proposed full adder shown in fig. 6 (c) varifies the operation of a full
adder.
Fig. 7a shows the three variations of a two input XOR logic gate by using
a single PMOS evaluation transistor, a single NMOS evaluation transistor
and the combination of both. Fig. 7b shows simulated waveforms of the
proposed XOR logic gate. For the case of single PMOS evaluation
transistor, when both inputs are equal (high or low), then both the
channels of the evaluation transistor are off and output remains in a
discharged state ('0'). When both inputs are different, then either top or
bottom channel conducts and hence output goes high. Similarly for the
case of a single NMOS evolution transistor, when both inputs are equal,
then either top or bottom channels of NMOS conducts and discharges
the output to low. Further, when the both inputs are different both
channels remain OFF and output remains in a charged state ('1').
Therefore Fig. 7 implements operation of an XOR logic gate correctly.
We can eliminate pre-charge or pre-discharge transistor at the output by
adding a complementary evaluation transistor similar to the design of
static CMOS logic gates.
Fig. 8a shows implementation of a two input NAND logic gate. In case of
a PMOS evaluation transistor, when at least one input is low, output gets
charged to high value and when both the inputs are high both top and
bottom channels become OFF and output remains low. For the case of an
NMOS evaluation transistor, when both inputs are high NMOS conducts
and hence discharges output to low state. Further, when any input is
low NMOS becomes OFF and output remains pre-charged to high value.
NAND gate is also implemented by using both NMOS and PMOS
evaluation transistors together that eliminates the need of pre-charging
or pre-discharging transistors at the output. Fig.8b shows simulated
waveforms of the proposed NAND logic gate.
Fig. 9a shows the implementation of a two input NOR logic gate with
single NMOS or with single PMOS or both types of evaluation transistors.
In case of single PMOS evaluation transistor, when both inputs are low
the transistor conducts and output gets charged to high state, otherwise
transistor is OFF and output remains discharged. In case of single
NMOS evaluation transistor, the output discharges when any input is
high otherwise output remains pre-charged to high value. In this way, a
two inputs NOR gate is implemented. When both types of evaluation
transistors are used, pre-charging or pre-discharging transistors are not
required at the output. Fig. 9b shows simulated waveforms of the
proposed two input NOR gate.
SUGGESTED CLAIMS ON:
1. A method for implementing a Boolean expression comprises:
A single evaluation transistor having engineered gate electrode;
The gate electrode has an array of gate metal patterns;
Number of rows in the gate pattern array is equal to number of
product terms in the Boolean equation;
Number of gate patterns in a row is equal to the number of input
variables in the product term representing that row.
2. Evaluation transistor used in claim 1 can be NMOS or PMOS
transistor.
3. When evaluation transistor of claim 1 is PMOS, then
complementary values of all variables present in the Boolean
equation are used as inputs (through gate pattern) for the PMOS
evaluation transistor. Besides, a pre-discharging NMOS transistor
is connected to the output node that discharges output node to
ground at the transition of any input.
4. When evaluation transistor of claim 1 is NMOS, the target Boolean
equation is complemented first and the resultant complemented
values are used as inputs for . the evaluation transistor gate
pattern. A pre-charging PMOS transistor is connected to the
output that charges output to high value at the transition of any
input.
5. A single NMOS can also be used with a pre-discharging NMOS at
the output and Boolean expression remains same as the target
expression for a NMOS evaluation transistor.
6.- Any Boolean expression can be implemented according to claim 1
by changing ' gate electrode patterns based on the number of
product terms and number of input variables in each product
term. This will be governed by the use of new NMOS or PMOS
evaluation transistor equations.
7. Evaluation transistor used in claim 1 can be doped source/drain
based or Schottky barrier metal source /drain based or based on
any other technology used for implementing a metal oxide
semiconductor field effect transistor (MOSFET).
8. A method for implementing a Boolean expression comprises:
Combination of gate pattered NMOS and PMOS transistors is
employed for evaluation of any Boolean expression. For the PMOS
transistor, the complementary values of all variables present in the
target Boolean equation are used as inputs (through gate pattern
and for the NMOS transistor, the target Boolean equation is
complemented first and the resultant expression is used as
inputs for the evaluation transistor gate pattern.