Description:RELATED APPLICATION
[0001] This patent application is related to India Patent Application No. 201647015459, filed on 04 May 2016, entitled “PCI EXPRESS ENHANCEMENTS”.

FIELD
[0002] This disclosure pertains to computing system, and in particular (but not exclusively) to point-to-point interconnects.
BACKGROUND
[0003] Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.
[0004] As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. But as the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.
[0005] In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to full blown interconnect architectures that facilitate fast communication. Unfortunately, as the demand for future processors to consume at even higher-rates corresponding demand is placed on the capabilities of existing interconnect architectures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 illustrates an embodiment of a computing system including an interconnect architecture.
[0007] FIG. 2 illustrates an embodiment of a interconnect architecture including a layered stack.
[0008] FIG. 3 illustrates an embodiment of a request or packet to be generated or received within an interconnect architecture.
[0009] FIG. 4 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture.
[0010] FIG. 5 illustrates an embodiment of an example two connector interconnect channel.
[0011] FIG. 6 is a simplified block diagram of a cross section of an interconnect structure including vias.
[0012] FIG. 7 is a representation of a cross section of an interconnect employing backdrilling of via stubs.
[0013] FIG. 8 is a block diagram representing a capability structure including a lane error status register.
[0014] FIG. 9 is a simplified diagram illustrating data flows on a multi-lane interconnect.
[0015] FIG. 10 shows representations of example framing token symbols.
[0016] FIG. 11 is a simplified diagram illustrating data flows including an example skip (SKP) ordered set.
[0017] FIG. 12 is a simplified block diagram illustrating lane errors that can be reported to an error register.
[0018] FIGS. 13A-13D are flowcharts illustrating example techniques for reporting lane errors of a link.
[0019] FIG. 14 illustrates an embodiment of a block diagram for a computing system including a multicore processor.
[0020] FIG. 15 illustrates another embodiment of a block diagram for a computing system including a multicore processor.
[0021] FIG. 16 illustrates an embodiment of a block diagram for a processor.
[0022] FIG. 17 illustrates another embodiment of a block diagram for a computing system including a processor.
[0023] FIG. 18 illustrates an embodiment of a block for a computing system including multiple processors.
[0024] FIG. 19 illustrates an example system implemented as system on chip (SoC).
[0025] Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0026] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven’t been described in detail in order to avoid unnecessarily obscuring the present invention.
, Claims:1. An apparatus comprising:
I/O logic to:
schedule a first SKP ordered set (OS) to be sent on a particular one of a plurality of lanes of a link, wherein the first SKP OS is scheduled to be sent on the link according to a particular interval;
identify that a link training state machine associated with the link is to enter a recovery state; and
generate a second SKP OS to be sent on the particular lane based on entry of the link into the recovery state, wherein the SKP OS is to be sent prior to the entry into the recovery state, and the second SKP OS is to be sent prior to the interval; and
a transmitter (222, 406) to:
send the first SKP OS on the particular lane; and
send the second SKP OS on the particular lane.