DESC:FORM – 2

THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003

COMPLETE SPECIFICATION
(SEE SECTION 10, RULE 13)

PERIPHERAL BUS ARCHITECTURE FOR READING SENSOR DATA

BHARAT ELECTRONICS LIMITED
OUTER RING ROAD, NAGAVARA, BANGALORE 560045, KARNATAKA, INDIA

THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

TECHNICAL FIELD
[0001] The present invention relates generally to a bus architecture. The invention, more particularly, relates to a bus architecture for reading digital sensor data on multi-node serial network and implementation method therefor.

BACKGROUND
[0002] Sensors form an integral part of modern precision machines to acquire data related to position, pressure, temperature, etc. Precision machines are typically used for performing tasks such as positioning, cutting, picking and placing of one or more objects and other similar high precision jobs accurately. Analog sensors have been used conventionally in these machines/systems for acquiring the data through feedback. Analog sensor based machines/systems having multiple node configurations are less complicated when the feedback is required at multiple nodes for processing. They are buffered to make the data available at multiple nodes for further processing.

[0003] With advancement in technology, digital sensors are being increasingly used in precision machines/systems. Digital sensors give feedback in digital format such as synchronous serial interface (SSI), serial peripheral interface (SPI), inter-integrated circuit (I2C), and the like, to cater to processing hardware requirements. This also helps to achieve better noise immunity and accuracies. Some of these digital sensors work synchronously using clock and data (SSI and other similar formats). However, when data is required at multiple nodes, point to point communication of digital sensors has always been a hindrance as it cannot be implemented the same way as Analog sensors. There are many applications wherein sensor feedback from one sensor is required at multiple nodes or a single sensor is only to be used to make the machinery cost effective and less complicated.

[0004] European Patent office publication EP3416061A1 refers to a method of sharing a common serial peripheral bus among multi master process controllers connected to digital sensors that work on SPI. It works with bus switching as an arbitration methodology, whereby only one master is granted access to the bus. However, the method is specific to SPI bus and uses multiplexing approach which will introduce delay and latency in the data processing.

[0005] There is therefore felt a need of an invention which solves the above defined problems in a multi-node environment, with digital sensor connected so that the data is efficiently and effectively acquired and handled at all the nodes.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0006] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and modules.

[0007] Figure 1 illustrates a schematic diagram depicting a system with bus topology for peripheral bus for reading sensor data, according to an exemplary implementation of the present invention.

[0008] Figure 2 illustrates a block diagram depicting a hardware engine of the system illustrated in Figure 1.

[0009] Figure 3 illustrates a graphical timing diagram depicting control of peripheral bus for reading sensor data, according to an exemplary implementation of the present invention.

[0010] Figure 4 illustrates a graphical timing diagram depicting control of peripheral bus for reading sensor data, according to another exemplary implementation of the present invention.

[0011] Figure 5 illustrates a graphical diagram depicting control of peripheral bus for reading sensor data, according to yet another exemplary implementation of the present invention.

[0012] Figure 6 illustrates a flow chart depicting the steps involved in a method for reading sensor data by bus arbitration, implemented by the hardware engine of system illustrated in Figure 2.

[0013] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

SUMMARY
[0014] This summary is provided to introduce concepts of the invention related to a peripheral bus architecture for reading sensor data, as disclosed herein. This summary is neither intended to identify essential features of the invention as per the present invention nor is it intended for use in determining or limiting the scope of the invention as per the present invention.

[0015] In accordance with an embodiment of the present invention a system is provided for reading data from a sensor associated with a plurality of devices. The system comprises: a peripheral bus having a clock channel, a DATA channel and an arbitration (ARB) channel, connected between the sensor and the plurality of devices, wherein each device comprises: a clock generator configured to generate a device clock (DC); a bus arbitrator configured to monitor the status of the ARB channel; a data processing unit configured to process and decode data received on the data channel; a ping pulse generator configured to generate a ping pulse; and a control unit in communication with the clock generator, the bus arbitrator, the data processing unit and the ping pulse generator. The control unit is configured to: command the bus arbitrator to monitor the status of the ARB channel; monitor the clock channel, on the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state communicated by the bus arbitrator to the control unit; command the bus arbitrator to drive the ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on the clock channel; generate and transmit the clock (CLK) on the clock channel subsequent to the driving of the ARB channel to the ‘HIGH’ state, wherein the clock (CLK) is generated by dividing the device clock (DC) by a predetermined factor; and monitor the DATA channel, and transmit data received from the sensor on the DATA channel to the data processing unit, or release the ARB channel to the ‘LOW’ state or ‘HIGH-Z’ state upon receiving a ping pulse on the DATA channel.

[0016] In an embodiment, the control unit of each device, in the event of the ‘HIGH’ status of ARB channel and failure of the clock (CLK), is configured to: command the ping pulse generator thereof to generate the ping pulse, and transmit the ping pulse on the DATA channel; command the bus arbitrator thereof to drive the released ARB channel to the ‘HIGH’ state; and generate and transmit the clock (CLK) on the clock channel subsequent to the driving of the ARB channel to the ‘HIGH’ state.

[0017] In accordance with another embodiment of the present invention, there is provided a method for reading data from a sensor associated with a plurality of devices. The method comprises: providing a peripheral bus between the sensor and the plurality of devices, wherein the peripheral bus includes a clock channel, a DATA channel and an arbitration (ARB) channel; monitoring, by each of the plurality of devices, the status of the ARB channel; monitoring, by each of the plurality of devices, the clock channel, corresponding to the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state; driving, by any one device of the plurality of devices, the ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on the clock channel; transmitting, by said any one device, the clock (CLK) on the clock channel; and reading, by each of the plurality of devices, data from the sensor, in presence of the clock (CLK) on the clock channel and the ‘HIGH’ state of the ARB channel.

[0018] In an embodiment, the method, in the event of power shut down of the said any one device, includes: driving, by another device of the plurality of devices, the ARB channel to the ‘HIGH’ state; and transmitting, by said another device, the clock (CLK) on the clock channel.

[0019] In another embodiment, the method, in the event of the ‘HIGH’ status of ARB channel and failure of the clock (CLK), includes: transmitting, by another device of the plurality of devices, a ping pulse on the DATA channel; releasing, by said any one device upon receiving the ping pulse on the DATA channel, the ARB channel to the ‘LOW’ state or ‘HIGH-Z’ state; driving, after release of the DATA channel, by said another device, the ARB channel to ‘HIGH’ state; transmitting, by said another device, the clock (CLK) on the clock channel.

[0020] In accordance with yet another embodiment of the present invention, there is provided a device for reading data from a sensor through a peripheral bus including a clock channel, a DATA channel and an arbitration (ARB) channel connected between the sensor and the device. The device comprises: a clock generator configured to generate a device clock (DC); a bus arbitrator configured to monitor the status of the ARB channel; a data processing unit configured to process and decode data received on the data channel; a ping pulse generator configured to generate a ping pulse; and a control unit in communication with the clock generator, the bus arbitrator, the data processing unit and the ping pulse generator. The control unit is configured to: command the bus arbitrator to monitor the status of the ARB channel; monitor the clock channel, on the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state communicated by the bus arbitrator to the control unit; command the bus arbitrator to drive the ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on the clock channel; generate and transmit the clock (CLK) on the clock channel subsequent to the driving of the ARB channel to the ‘HIGH’ state, wherein the clock (CLK) is generated by dividing the device clock (DC) by a predetermined factor; monitor the DATA channel, and transmit data from the sensor received on the DATA channel to the data processing unit, or release the ARB channel to ‘LOW’ state or ‘HIGH-Z’ state upon receiving a ping pulse on the DATA channel.

DETAILED DESCRIPTION
[0021] The various embodiments of the present invention describe about a system for reading data from a sensor associated with a plurality of devices/nodes through a peripheral bus architecture for a multi-node serial data network, hereinafter referred to as sensor peripheral bus (SPB) architecture. It further describes a method for reading data from the sensor associated with the plurality of devices by a bus arbitration technique and SPB hardware engine for implementing the bus arbitration technique through the system to formulate the sensor peripheral bus. The SPB architecture as disclosed herein applies to applications where digital sensor data is required concurrently at multiple devices/nodes connected on the same network. Throughout the invention, the terminology “device” and “node” is used interchangeably as it is intended to refer to the same hardware.

[0022] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.

[0023] However, the systems and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently invention and are meant to avoid obscuring of the presently invention.

[0024] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0025] Figure 1 illustrates a schematic diagram of a system (100) for reading data from the sensor (50) associated with a plurality of devices/nodes (10a, 10b…10n), according to an exemplary implementation of the present invention. The diagram depicts a bus topology for a sensor peripheral bus (SPB) for reading the sensor data. As illustrated, the system comprises the sensor peripheral bus (SPB) (20) having three channels namely a clock (CLK) channel, a DATA channel and an arbitration (ARB) channel as shown in Figure 1. These channels have the electrical specifications of TIA/EIA-485-A which is the telecommunication industry’s most widely used transmission line standard. This helps in achieving multi-node bus topology where any node or device (1 to n) can be a primary master. Accordingly, these channels are bi-directional. Each channel is a two wire RS-485 network connected in a multipoint configuration and allows for data transmission in both directions, but only in one direction at a time. Termination requirement (Parallel or AC) for each channel is dependent on the cable length run between the devices and sensor.

[0026] Figure 2 illustrates a block diagram depicting a hardware engine of the system illustrated in Figure 1. The hardware engine is a part of each device/node (10a, 10b…10n) of the system (100). Accordingly, each device (10) comprises a clock generator (101), a bus arbitrator (103), a ping pulse generator (104), a data processing unit (105), and a control unit (102) in communication with the clock generator (101), the bus arbitrator (103), the ping pulse generator (104) and the data processing unit (105). The clock generator (102) is configured to generate a device clock (DC). The bus arbitrator (103) is configured to monitor the status of the ARB channel. The ping pulse generator (104) is configured to generate a ping pulse. The data processing unit (105) is configured to process and decode data received on the DATA channel.

[0027] The device clock (DC) generated by the clock generator (101) is fed to the control module (102) which decides the generation or monitoring of the clock (CLK) based on the arbitration. The bus arbitrator (103) sends the ARB channel status, whether ‘HIGH-Z’, ‘LOW’ or ‘HIGH’, to the control unit (102) for controlling the direction of data and clock (CLK) on the DATA and clock channels respectively. The bus arbitrator (103) is also controlled by the control unit (102) on whether to drive the ARB channel or monitor the ARB channel. DATA channel monitoring is implemented in the control unit (102) based on the bus arbitrator (103) control. The ping/sync pulse generator (104) output is fed to the control unit (102) which in turn decides when to transmit the ping/sync pulse on the DATA channel. The data processing unit (105) receives the clock (CLK) and data from the control unit (102) for processing and decoding the sensor data. All the units (102-105) are synchronized using the device clock (DC) generated by the clock generator (101).

[0028] Thus, control unit (102) is configured to command the bus arbitrator (103) to monitor the status of the ARB channel. The control unit is also configured to monitor the clock (CLK) channel, corresponding to the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state, as communicated by the bus arbitrator (103) to the control unit (102), and is further configured to command the bus arbitrator (103) to drive the ARB channel to a ‘HIGH’ state in absence of the clock (CLK) on the clock channel, and to generate and transmit the clock (CLK) on the clock channel subsequent to the driving of the ARB channel to the ‘HIGH’ state. The device (10) operates as a primary controller of the peripheral bus (20) by driving the ARB channel to the ‘HIGH’ state. The sensor (10) is configured to transmit data on the DATA channel upon receiving the clock (CLK) on the clock channel. The control unit (102) is further configured to monitor the DATA channel, and transmit data received from the sensor (10) on the DATA channel to the data processing unit (105), or release the ARB channel to the ‘LOW’ state or ‘HIGH-Z’ state upon receiving the ping pulse on the DATA channel.

[0029] In an embodiment, the control unit (101) of each device (10a, 10b…10n), in the event of the ‘HIGH’ status of ARB channel and failure of the clock (CLK), is configured to command the ping pulse generator (104) thereof to generate the ping pulse, and transmit the ping pulse on the DATA channel; command the bus arbitrator (103) thereof to drive the ARB channel, released by the primary controller, to the ‘HIGH’ state; and generate and transmit the clock (CLK) on the clock channel subsequent to the driving of the ARB channel to the ‘HIGH’ state. Accordingly, the device which transmits the ping pulse operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state.

[0030] In an exemplary non-limiting embodiment, the frequency of the device clock (DC) is at least 10 times greater than the clock (CLK) on the clock channel, i.e. the control unit (101) of each device (10a, 10b…10n) is configured to generate the clock (CLK) by dividing the device clock (DC) by a predetermined factor/value of 10.

[0031] Figure 3 illustrates a graphical timing diagram depicting control of SPB by the primary controller for reading sensor data, according to an exemplary implementation of the present invention. Any node/device (10a to 10n) on power up monitors the ARB channel status. If the ARB channel status is in ‘High-Z’ state or ‘Low’ state, then the device monitors the CLK channel. If there is no clock on the SPB then the device becomes the primary controller by driving the ARB line HIGH. Once, the line is driven high, the primary controller device starts transmitting the sensor clock on CLK channel after tD seconds as shown in Figure 2. The sensor will start transmitting the data after receiving the clock (CLK) on clock channel. Other nodes/devices connected on the SPB will listen to the bus for clock (CLK) and data transmitted on clock & DATA channels. They decode the sensor data for further processing. Each data cycle repeats every tCY seconds as shown in Figure 2.

[0032] Figure 4 illustrates a graphical timing diagram depicting control of SPB by a secondary device on shut down of the primary controller, according to another exemplary implementation of the present invention. If there is power shut down of the primary controller, then ARB channel is not driven. Immediately after Tfailure (Time between ARB channel ‘High-Z’ state to ‘High’ state which is > 2 tCY), another/secondary device on the SPB will pull the ARB channel high and starts transmission of clock (CLK) on the clock channel to become the primary controller of the bus as shown in Figure 3.

[0033] Figure 5 illustrates a graphical diagram depicting control of SPB by the another/secondary device on clock (CLK) failure of the primary controller, according to yet another exemplary implementation of the present invention. If the primary controller is powered on, but the clock (CLK) generation has failed, ARB channel will still be in ‘High;’ state, but no data will be transmitted by the sensor due to non-availability of the clock (CLK). Then one of another nodes / secondary devices on the bus transmits a ping pulse on the DATA channel after Tfailure (>2 tCY seconds). On seeing this ping pulse, the primary controller releases or shuts down the ARB channel to ‘LOW’ state or ‘HIGH-Z’ state deeming failure of its clock generation circuitry. Once the ARB channel is released shut down, the another node/secondary device that has transmitted the ping pulse will drive the ARB channel to ‘HIGH’ state after Tgen seconds (<2 tCY seconds) to become the primary controller of the SPB and starts clock (CLK) transmission on the clock channel, as shown in Figure 4.

[0034] Figure 6 illustrates a flow chart depicting the steps involved in a method for reading data from a sensor (50) associated with a plurality of devices (10a, 10b…10n) by a bus arbitration technique implemented by the system shown in figure 1. This method is implemented in the system through the SPB hardware engine of each device as shown in Figure 5. Each device (10a, 10b…10n) first checks the ARB channel, and if the ARB channel is not driven then ARB will be made HIGH after Tfailure by any one device. After ARB is made HIGH, clock is generated after tD seconds by that device. Data from the DATA channel is sampled, and if there is no ping pulse monitored on the DATA channel then the data processing module (105) is invoked to process and decode the data received from the sensor on the DATA channel. If a ping pulse is detected then the ARB channel is released to ‘LOW’ state or not driven i.e. ‘HIGH-Z’ state and clock (CLK) failure is reported. If clock (CLK) is available and ARB channel is in ‘HIGH’ state then data is sampled and data processing module (105) is invoked. Else if ARB channel is in ‘HIGH’ state and clock (CLK) is not available then a ping pulse is generated on the DATA channel during this error state after Tfailure seconds.

[0035] Thus, referring to Figures 3 and 6, the method for reading data from the sensor (50) associated with the plurality of devices (10a, 10b…10n) comprises the following steps: providing a peripheral bus (20) having a clock (CLK) channel, a DATA channel and an arbitration (ARB) channel, between the sensor and the plurality of devices; monitoring, by each of the plurality of devices (10a, 10b… 10n), the status of the ARB channel; monitoring, by each of the plurality of devices (10a, 10b… 10n), the clock channel, on the status of the ARB channel being ‘LOW’ state or ‘HIGH-Z’ state; driving, by any one device of the plurality of devices, the ARB channel to ‘HIGH’ state in absence of a clock (CLK) on the clock channel, wherein said any one device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state; transmitting, by said any one device, the clock (CLK) on the clock channel whereby the rest of plurality of the devices operate based on the clock (CLK) and the ‘HIGH’ state of the ARB channel and the sensor (50) transmits the data on the DATA channel upon receiving the clock (CLK) on the clock channel; and reading, by each of the plurality of devices (10a, 10b… 10n), data from the sensor (50), in presence of the clock (CLK) on the clock channel and the ‘HIGH’ state of the ARB channel.

[0036] Referring to figures 4 and 6, the method, in the event of power shut down of the primary controller, includes: driving, by another device of the plurality of devices, the ARB channel to ‘HIGH’ state; and transmitting, by said another device, the clock on the clock channel; wherein said another device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state.

[0037] Referring to figures 5 and 6, the method, in the event of the ‘HIGH’ status of ARB channel and failure of the clock (CLK), includes: transmitting, by another device of the plurality of devices, a ping pulse on the DATA channel; releasing, by the primary controller upon receiving the ping pulse on the DATA channel, the ARB channel to ‘LOW’ state or ‘HIGH-Z’ state; driving, after release of the DATA channel by the primary controller, the ARB channel to ‘HIGH’ state; and transmitting, by said another device, the clock (CLK) on the clock channel; wherein said another device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state.

TECHNICAL ADVANTAGES
[0038] At least some of the technical advantages provided by the presently disclosed system and method for reading data from a sensor associated with a plurality of devices through a peripheral bus architecture and a bus arbitration technique, are as under:
Any device or node can be a primary controller in the event of failure or shut down of an initial primary controller, thus making it a multi-master bus topology.
The bus arbitration technique is adopted to decide the primary controller of the peripheral bus, which enables reading of sensor data at all the nodes/devices without bus contention.
The peripheral bus architecture uses an additional channel apart from the standard data and clock channel required to devise the arbitration technique in synchronous serial interface.

[0039] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:WE CLAIM:

1. A system (100) for reading data from a sensor (50) associated with a plurality of devices (10a, 10b… 10n), said system (100) comprising:
a peripheral bus (20) connected between said sensor (50) and said plurality of devices (10a, 10b… 10n), wherein said peripheral bus (20) includes a clock (CLK) channel, a DATA channel and an arbitration (ARB) channel;
each device (10) comprising:
a clock generator (101) configured to generate a device clock (DC);
a bus arbitrator (103) configured to monitor the status of said ARB channel;
a ping pulse generator (104) configured to generate a ping pulse;
a data processing unit (105) configured to process and decode data received on the DATA channel; and
a control unit (102) in communication with said clock generator (101), said bus arbitrator (103), said ping pulse generator (104) and said data processing unit (105), said control unit (101) configured to:
command said bus arbitrator (103) to monitor the status of said ARB channel;
monitor said clock channel, corresponding the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state communicated by said bus arbitrator (103) to said control unit (101);
command said bus arbitrator (103) to drive said ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on said clock channel;
generate and transmit the clock (CLK) on said clock channel subsequent to the driving of said ARB channel to the ‘HIGH’ state; and
monitor said DATA channel, and
transmit data received from said sensor (10) on said DATA channel to said data processing unit (105), or
release said ARB channel to the ‘LOW’ state or ‘HIGH-Z’ state upon receiving a ping pulse on said DATA channel.

2. The system (100) as claimed in claim 1, wherein said device operates as a primary controller of the peripheral bus (20) by driving said ARB channel to the ‘HIGH’ state.

3. The system (100) as claimed in claim 1, wherein said the sensor (10) is configured to transmit data on said DATA channel upon receiving the clock (CLK) on said clock channel.

4. The system (100) as claimed in claim 1, wherein,
said bus arbitrator (103) drives said ARB channel to the ‘HIGH’ state after a predetermined time of Tfailure seconds, and
said control unit (101) transmits the clock (CLK) on said clock channel after a predetermined time period of tD seconds.

5. The system (100) as claimed in claims 1 and 2, wherein said control unit (101) of each device (10a, 10b…10n), in the event of the ‘HIGH’ status of said ARB channel and failure of the clock (CLK), is configured to:
command said ping pulse generator (105) thereof to generate the ping pulse, and transmit the ping pulse on said DATA channel;
command said bus arbitrator (103) thereof to drive said ARB channel, released by said primary controller, to the ‘HIGH’ state; and
generate and transmit the clock (CLK) on said clock channel subsequent to the driving of said ARB channel to the ‘HIGH’ state; and
wherein the device which transmits the ping pulse operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state.

6. The system (100) as claimed in claim 5, wherein,
said ping pulse generator (105) transmits the ping pulse after a predetermined time period of Tfailure seconds,
said bus arbitrator (103) drives said ARB channel to the ‘HIGH’ state after a predetermined time period of Tgen seconds, and
said control unit (101) transmits the clock (CLK) on said clock channel after a predetermined time period of tD seconds.

7. The system (100) as claimed in claims 1-6, wherein,
data is transmitted periodically by said sensor (50) on said DATA channel after every predetermined time of tCY seconds,
the predetermined time period of Tfailure seconds is greater than 2 tCY seconds (Tfailure > 2 tCY), and
the predetermined time period of Tgen seconds is greater than 2 tCY seconds (Tgen > 2 tCY).

8. The system (100) as claimed in claims 1-7, wherein said control unit (101) of each device (10a, 10b…10n) is configured to generate the clock (CLK) by dividing said device clock (DC) by a predetermined factor.

9. A method for reading data from a sensor (50) associated with a plurality of devices (10a, 10b… 10n), the method comprising:
providing a peripheral bus (20) between the sensor and the plurality of devices, wherein the peripheral bus (20) includes a clock (CLK) channel, a DATA channel and an arbitration (ARB) channel;
monitoring, by each of the plurality of devices (10a, 10b… 10n), the status of the ARB channel;
monitoring, by each of the plurality of devices (10a, 10b… 10n), the clock channel, corresponding to the status of the ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state;
driving, by any one device of the plurality of devices, the ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on the clock channel;
transmitting, by said any one device, the clock (CLK) on the clock channel; and
reading, by each of the plurality of devices (10a, 10b… 10n), data from the sensor (50), in presence of the clock on the clock channel and the ‘HIGH’ state of the ARB channel.

10. The method as claimed in claim 9, wherein said any one device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to ‘HIGH’ state, and the rest of plurality of the devices operate based on the clock (CLK) transmitted by the primary controller and the ‘HIGH’ state of the ARB channel.

11. The method as claimed in claim 9, wherein the method includes transmitting, by the sensor (50) upon receiving the clock (CLK) on the clock channel, the data on the DATA channel.

12. The method as claimed in claims 9 and 10, wherein the method, in the event of shut down of the primary controller, includes:
driving, by another device of the plurality of devices, the ARB channel to the ‘HIGH’ state; and
transmitting, by said another device, the clock (CLK) on the clock channel; and
wherein said another device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to the ‘HIGH’ state.

13. The method as claimed in claims 9 and 10, wherein the method, in the event of the ‘HIGH’ status of ARB channel and failure of the clock (CLK), includes:
transmitting, by another device of the plurality of devices, a ping pulse on the DATA channel;
releasing, by the primary controller upon receiving the ping pulse on the DATA channel, the ARB channel to the ‘LOW’ state or the ‘HIGH-Z’ state;
driving, by said another device, after release of the DATA channel, the ARB channel to the ‘HIGH’ state; and
transmitting, by said another device, the clock (CLK) on the clock channel;
wherein said another device operates as a primary controller of the peripheral bus (20) by driving the ARB channel to the ‘HIGH’ state.

14. The method as claimed in claim 9, wherein the clock channel and the DATA channel are connected between the sensor (50) and each of the plurality of devices (10a, 10b… 10n), and the ARB channel is connected between each of the plurality of devices (10a, 10b… 10n).

15. A device (10) for reading data from a sensor (50) through a peripheral bus (20) including a clock (CLK) channel, a DATA channel and an arbitration (ARB) channel connected between said sensor (50) and said device (10), said device comprising:
a clock generator (101) configured to generate a device clock (DC);
a bus arbitrator (103) configured to monitor the status of said ARB channel;
a ping pulse generator (104) configured to generate a ping pulse; and
a data processing unit (105) configured to process and decode data received on said data channel;
a control unit (102) in communication with said clock generator (102), said bus arbitrator (103), said ping pulse generator (104), and said data processing unit (105), said control unit (101) configured to:
command said bus arbitrator (103) to monitor the status of said ARB channel;
monitor said clock channel, corresponding to the status of said ARB channel being a ‘LOW’ state or a ‘HIGH-Z’ state, communicated by said bus arbitrator (103) to said control unit (101);
command said bus arbitrator (103) to drive said ARB channel to a ‘HIGH’ state in absence of a clock (CLK) on said clock channel;
generate and transmit the clock (CLK) on said clock channel subsequent to the driving of said ARB channel to the ‘HIGH’ state, wherein the clock (CLK) is generated by dividing said device clock (DC) by a predetermined factor;
monitor said DATA channel, and
transmit data from said sensor (10) received on said DATA channel to said data processing unit (105), or
release said ARB channel to the ‘LOW’ state or ‘HIGH-Z’ state upon receiving a ping pulse on said DATA channel.

Dated this 15th day of March, 2019
FOR BHARAT ELECTRONICS LIMITED
(By their Agent)

D. MANOJ KUMAR (IN/PA-2110)
KRISHNA & SAURASTRI ASSOCIATES LLP