PHASE ERROR MEASUREMENT CIRCUIT WITH REFERENCELESS GAIN AND
OFFSET-CALIBRATION
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] None
FIELD OF THE INVENTION
[0002] The disclosure relates generally to phase error measurement circuit and in particular to a gain and offset-calibrated 3-state phase detector.
DESCRIPTION OF THE RELATED ART
[0003] Multi-phase high-frequency periodic signals are widely used in signal processing ICs. Signal processing ICs include I/Q carriers for up-down conversion in radios, multi-phase carriers for wideband phase modulation, multi-phase clocks in clock data recovery (CDR) etc. In these, static phase errors are caused due to misplaced clock signals. This could cause imperfect image rejection, degraded error vector magnitude (EVM), reduced adjacent channel power ratio (ACPR), and higher bit error rate (BER). Accurate phase error measurement can help correct either the source (e.g. by asymmetrical capacitive loading in a Quadrature Voltage Controlled Oscillator) or its result (e.g. by phase shifting in baseband).
[0004] The US patent US7999583B2 discloses an apparatus that includes a phase-locked loop (PLL) circuit and a phase-frequency detector that is configured to output phase error signals. The published patent application WO2016076419A1 discloses a digital phase measuring device and a digital phase difference measuring device that are capable of accurate and real-time measurement. Another published patent application US5477177A discloses a phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising

pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width “A 2-GHz CMOS image-reject receiver with LMS calibration”, L. Der et al (2003)discloses system level techniques on ICs for phase error measurement. “Measuring Phase and Delay Errors Accurately in I/Q Modulators”, Stroet (2006), uses external equipment that includes a spectrum analyzer to measure image rejection of an on-chip mixer. “A CMOS Magnitude/Phase Measurement Chip for Impedance Spectroscopy” by P. Kassanos et al (2013) discusses on using XOR gates at low frequencies.

SUMMARY OF THE INVENTION
[0005] In various embodiments the invention proposes systems and involving two or more signals. In one embodiment a method of measuring quadrature phase error in circuits is proposed, including the steps of:
a. providing a first input signal to a first flip-flop of a phase detector and a
second input signal to a second flip-flop of the phase detector. The first output voltage
V1, is obtained by
�1 = ��� I� + ���1 J + ��
Where Kpd is the unknown gain and Ve is the offset voltage. The flip-flops are configured to operate in a first mode where the first input signal leads the second input signal.
b. interchanging the input signals between the flip-flops to obtain the second
output voltage V2, The second output voltage given by
�2 = ��� I —- ���1 I + ��
where the flip-flops operate in the first mode;
c. providing the first input signal to the first flip-flop of the phase detector
and the second input signal to the second flip-flop of the phase detector to obtain the
third output voltage V3,
�3 = -���^ � -���1) + ��
when the flip-flops are configured to operate in a second mode when the second input signal leads the first input.
d. interchanging the input signals between the flip-flops to obtain the fourth
output voltage V4,
�4 = - ��� I� + ���1 J + ��
wherein the flip-flops operate in the second mode; and
e. combining the output voltages to eliminate the unknown gain Kpd and
offset voltage Ve and to determine the phase error (Ac|)r1). The phase error is given by
���1 = � (12 + ��1-+ ��2+- ��3-- ��4-).

[0006] In some embodiments the method is incorporated in a phase error measurement circuit to measure phase error. In various embodiments the circuit directly operates with input signals and does not require a reference.
[0007] In various embodiments an error-compensating circuit architecture to eliminate phase errors between a first input signal and a second input signal is disclosed. The error-compensating circuit architecture includes one or more phase detectors to measure the phase difference between the first input signal and the second input signal and a first and a second auxiliar y phase detector. Each phase detector includes a first flip-flop t hat receives the first input signal and a second flip-flop that receives the second input signal. The flip-flops are configured to operate either in a first mode when the first input signal leads the second input signal or a second mode when the second input signal leads the first input signal. The first auxiliary phase detector is configured to add a phase angle of integer multiples of π to the measured phase difference between the first input signal and the second input signal in order to allow for better settling of waveforms and the second auxiliary phase detector is configured to either initiate a reset command at a first predetermined time or to release the reset after a second predetermined time. The error-compensating circuit architecture on receiving the first input signal and the second input signal adds a phase angle of integer multiples of π to the measured phase difference, initiates the reset bit at the first predetermined time and releases the reset after the second predetermined time to eliminate the phase error.
[0008] In some embodiments the flip-flops comprise one or more control bits for operation in either the first mode or the second mode. In some embodiments the reset command is initiated at a first predetermined time when the output of both the flip-flops of the second auxiliary phase detector is in logic HIGH state. In other embodiments the reset command is released at a second predetermined time when the first input signal rises from its logic LOW state to a logic HIGH state.
[0009] In various embodiments the invention is an integrated circuit chip for measuring phase error between a first input signal and a second input signal that includes an edge

selector configured to receive a first input signal and a second input signal, a fir st enhanced phase error detector (EPD) configured to operate on the rising edge of the input signals, a second enhanced phase error detector configured to operate on the falling edge of the input signals. The edge selector routes the appropriate edges to the first EPD and the second EPD. An output selector is configured to select the appropriate output from the first EPD or the second EPD. The integrated circuit chip also includes an analog to digital controller that converts the analog signals to digital form and a digital engine that incorporates the method of measuring quadrature phase error In various embodiments the integrated circuit chip on receiving the first input signal and the second computes the phase error.
[0010] In some embodiments the chip can be implemented on system-on-chip applications for phase error diagnostic or phase correctional aid purposes. [0011] In various embodiments the chip can be incorporated in SSB up/down converters for a communication device where the chip detects the phase error in the local oscillator signal used for the SSB up/down converter. In various other embodiments the chip can also be incorporated in phase modulators where the chip compares the phase of the output signal with the phase of a reference signal and produces an error signal.

BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The invention has other advantages and features which will be mor e r eadily apparent from the following detailed description of the disclosure and the appended claims, when taken in conjunction with the accompanying drawings, in which:
[0013] FIG. 1 illustrates the flowchart of the method of eliminating the phase error in a circuit receiving two or more input signals.
[0014] FIG. 2A illustrates the flowchart of the method of error compensation in a circuit receiving signals.
[0015] FIG. 2B illustrates a detector receiving two input signals I and Q.
[0016] FIG. 2C shows an error compensating circuit architecture receiving two input signals.
[0017] FIG. 2D illustrates an integrated circuit chip incorporating the error compensating circuit architecture.
[0018] FIG. 3A shows a 3-state phase detector.
[0019] FIG. 3Billustrates state diagram of a 3-state phase detector receiving two input signals I and Q.
[0020] FIG. 3C illustrates the ideal waveforms of the 3-state phase detector when signal I leads signal Q by an angle φ.
[0021] FIG. 3D illustrates the ideal waveforms of the 3-state phase detector when signal I lags behind signal Q by an angle φ.
[0022] FIG. 3E illustrates the ideal and real waveforms of the 3-state phase detector when signal A leads signal B by an angle φ.
[0023] FIG. 3F shows the increase in area of real waveform the 3-state phase detector when signal A leads signal B by an angle φ.

[0024] FIG. 4A illustrates the TSPC DFF used in the PD.
[0025] FIG. 4B shows PD waveforms using DFF
[0026] FIG 4C illustrates the enhanced phase detector (EPD) having two auxiliary PD.
[0027] FIG 4D shows the waveform for Mo= 1for the enhanced phase detector (EPD) having two auxiliary PDs.
[0028] FIG 5 shows the chip architecture incorporating the method of eliminating the phase error.
[0029] FIG. 6 shows individual chip measurements over frequency and the performance summary.
[0030] FIG. 7 illustrates the simulated characteristics of the proposed PMC.

DETAILED DESCRIPTION
[0031] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.
[0032] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on." Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.
[0033] The invention in its various embodiments proposes a method of measuring quadrature phase error (Δϕr1) in integrated circuits that include two or more signals. Further the method may be incorporated in a compact, on-chip, standalone I/Q phase error measurement circuit (PMC) that may directly operate with high frequency inputs and does not require a reference.
[0034] In various embodiments the method of measuring quadrature phase error 100in two or more signals includes the steps as shown in FIG. 1. In step 101the first input signal is fed to a first flip-flop of a phase detector and the second input signal is fed to a second flip-flop of the phase detector. In step 102 when the first input signal leads the second input signal the flip-flops are forced to operate in mode 1 to generate a first output voltage V1in step 103given by
V^ = Kpcj f- + Acprl J + Ve…………..(1)-

In step 104 the input signals are interchanged between the first flip-flop and the second flip-flop. The second output voltage V2 is computed in step 105. The second output voltage is given by
V2 = Kpd(32π-Δφr1)+Ve………….(2)
In step 106 when the second input signal leads the first input signal the flip-flops are forced to operate in mode 2. The third output voltage V3 is computed in step 107 and is given by
V3 = Kpd(32π-Δφr1)+Ve………….(3)
In step 108 the input signals are interchanged between the first flip-flop and the second flip-flop. The fourth output voltage V4 is computed in step 109 and is given by
V4 = -Kpd(π2 + Δφr1)+Ve…………….(4)
In step 110 the phase error ���1 is determined by combining the output voltages V1, V2, V3 and V4as given by
V1-V2+V3-V4 r 1
= (5)
V1+V2-V3-V4 π 2
The combination of output voltages given in equation (5) eliminates the unknown phase detector gain Kpd and the offset voltage Ve and the phase error is given by ���1=�£ + ( �1-��2+��3-�4^……………(6)
[0035] In various embodiments the method 100 is incorporated in a phase error measurement circuit to measure phase error. In various embodiments the circuit operates on input signals of any frequency and does not require a reference.
[0036] In various embodiments the invention is an error-compensating circuit architecture 400 that eliminates phase measurement errors between a first input signal 401 and a second input signal 402. The phase measurement error is due to phase mismatches either in the input path or the output path. The method of error compensation 200 is as shown in FIG. 2A. In step 201 the phase detector receives the first input signal

and the second input signal. The first signal is received by a first flip-flop of the phase detector and the second signal is received by a second flip-flop of the phase detector. The phase difference φ between the first input signal and the second input signal are measured in step 202. In step 203a phase angle of 2π is added to the phase difference φ. The addition of 2π lets the second input signal to settle down. In step 204 the reset is initiated one cycle after the output of the second flip-flop goes high. In step 205 the reset is released after a predetermined time when the first input signal changes state from LOW to HIGH.
[0037] In various embodiments the error-compensating circuit architecture 400 as shown in FIG. 2C includes one or more phase detectors 300 as shown in FIG. 2B to measure the phase difference between the first input signal 301 and the second input signal 302. Each phase detector includes a first flip-flop 310 that receives the first input signal 301 through a flipping circuit 330 and a second flip-flop 320 that receives the second input signal 302 through the flipping circuit 330. The flip-flops 310, 320 are configured to operate either in a first mode or a second mode. The flip-flops operate in the first mode when the first input signal 301 leads the second input signal 302. The flip-flops operate in the second mode when the second input signal 302 leads the first input signal 301.
[0038] In some embodiments the error-compensating circuit architecture 400 further includes a first auxiliary phase detector 300-2and a second auxiliary phase detector300-3 as shown in FIG. 2C. The first auxiliary phase detector 300-2 is configured to add a phase angle of 2π to the measured phase difference between the first input signal 401 and the second input signal 402. The second auxiliary phase detector 300-3 is configured to initiate a reset command at a first predetermined time that elongates the reset to one cycle even after the output of the second flip-flop goes high. The second auxiliary phase detector 300-3 is further configured to release the reset after a second predetermined time when the first input signal 401 changes state from logic LOW to logic HIGH state.

[0039] In various embodiments when the error-compensating circuit 400 receives the first input signal 401 and the second input signal 402 the first auxiliary phase detector 300-2 of the error-compensating circuit 400 adds a phase angle of 2π to the measured phase difference and initiates the reset bit at the first predetermined time. The error-compensating circuit 400 further releases the reset after the second predetermined time when the first input signal 401 changes state from logic LOW to logic HIGH, to eliminate the phase error.
[0040] In various embodiments the flip-flops410, 420, 430, 440, 450, 460 of the error-compensating circuit400 includes control bits M 411, 421, 431, 441, 451, 461 and T 413, 423, 433, 443, 453, 463 to force either the first mode or the second mode. When the first input signal 401 leads the second input signal, M0=1 and the circuit operates in the first mode. When the second input signal 402 leads the first input signal, M0=0 and hence the circuit operates in the second mode.
[0041] In some embodiments the second auxiliary phase detector 300-3 initiates the reset command at a first predetermined time when the outputs of both the flip-flops of the second auxiliary phase detector are in logic HIGH state.
[0042] In some embodiments the input signals to the circuit are of high frequency in the range of gigahertz. In some embodiments the input signals are of the same frequency.
[0043] In various embodiments the error-compensating circuit architecture is incorporated in an integrated circuit chip 500 as shown in FIG. 2D for measuring phase error between a first input signal 501 and a second input signal 502. The integrated circuit chip 500 includes an edge selector 530 configured to receive the first input signal 501 and the second input signal 502, a first enhanced phase error detector (EPD) 541 that is configured to operate on the rising edge of the input signals, a second EPD 542 that is configured to operate on the falling edge of the input signals and an output selector 550 that selects the appropriate output from the first EPD 541 or the second EPD 542. In some embodiments the edge selector 530 routes the appropriate edges to the first EPD

541 and the second EPD 542. In some embodiments the integrated circuit chip 500 also includes an analog to digital converter 560 that converts the analog signals to digital form and a digital engine 570 that incorporates the method of measuring quadrature phase error. In various embodiments the integrated circuit chip, on receiving the first input signal and the second input signal computes the phase error. In various embodiments the method is incorporated in a phase error measurement circuit to measure the phase error and to eliminate the error in the circuit.
[0044] In various embodiments the invention discloses an SSB up/down converter, a phase modulator, or a clock and data recovery circuit that incorporates the systems and methods as disclosed in FIG. 1 and FIG. 2A-2D. Further, the error compensating circuitry as disclosed here can be used in any diagnostic or correctional aid systems using multiple high-frequency clock phases which also fall within the scope of the invention.
[0045] In various embodiments the integrated circuit chip is used in SSB up/down converters for a communication device to detect the phase error in the local oscillator signals used for the mixer. The phase error is measured using the method and the phase shift between the input signals is corrected by this amount to get a resulting spectrum.
[0046] In some embodiments the integrated circuit chip is also used in phase modulators to compare the phase of the output signal with the phase of a reference signal to produce an error signal
EXAMPLES
Example 1Ideal and real time behavior of a 3 state phase detector
[0047] A 3-state phase detector (PD), is as shown in FIG.3A. The state diagram, and idealized waveforms of the PD are as shown in FIG.3B, FIG.3C and FIG.3D. A flipping circuit is used to interchange the inputs to the two D-flip-flops (DFFs). When driven by two inputs at the same frequency, the PD cycles between states as shown in FIG. 3B, 00

and 10 (mode AB when A leads B) or between 00 and 01 (mode BA when B leads A). M0 = 1 forces mode AB and M0 = 0 forces mode BA. To force the modes, the DFFs have additional inputs M and T. FIG.3C shows the ideal waveform when the signal A leads signal B by an angle ϕ. The output V0 generated in mode AB is given by V0= Kpdϕ and the output generated in mode BA is given by V0 = Kpd(ϕ-2π). FIG. 3D shows the ideal waveform when the signal A lags behind signal B by an angle ϕ. The output V0 generated in mode AB is given by V0= Kpd(2π-ϕ) and the output generated in mode BA is given by V0 = -Kpdϕ. FIG.3E shows inputs A and B with a phase difference ϕ. In mode AB, with zero rise/fall times and no mismatch, the output is Kpdϕ. In reality as shown in FIG. 3F, the output is of the form Kpdϕ+Ve.
[0048] Phase mismatches in the input or reset paths cause an output offset Ve. This linear
model holds when the ϕ is such that QA and QB settle to their logic levels. In such a case,
an increment by Δϕ changes the area by the same amount as in the ideal case. The
unknowns Kpd and Ve can be eliminated by repeating the measurement with (a) both
modes AB and BA, and (b) interchanged inputs. In our case, we would like to measure I/Q accuracy where rising edge of Q lags that of I by - + A(prl. Table. 1 shows the 4
measurements for this case. Combining the outputs according to the expression given eliminates Kpd and Ve and determines Δϕr1 accurately.
Table 1: Measurements for I/Q accuracy where rising edge of Q lags that of I by


Example 2 Phase measurement and modification of architecture to compensate for the measured phase error
[0049] FIG. 4A shows the TSPC DFF used in the PD. Controls M and T are added to the DFF as shown in FIG. 4B in to force the desired mode. Node X pre-charges to Vdd only if MT = 0. If M0 = 1 FFB pre-charges only after its T(= QA) goes to zero. This means that QA has to be 1 before QB can be 1, forcing mode AB in which A is the leading signal. The pre-charge window for FFB is only a quarter cycle. At higher frequencies, node X in FFB is only partially pre-charged, resulting in a slow discharge of QB and consequently, delayed reset. Additionally, the reset pulse is narrow in the conventional 3-state PD. At 2.4 GHz in 0.13 μm CMOS, none of the internal waveforms settles completely and there is an error of several degrees in the measured phase. To remedy this, the architecture is modified to (a) Add 2π to the measured phase i.e. in mode AB, QA goes high at the rising edge of A and QB goes high at the rising edge of B in the next cycle, (b) Initiate reset one cycle after QB goes high. This allows QB to settle completely, (c) Release the reset at the rising edge of A so that FFA is guaranteed a half cycle for pre-charge. FIG. 4C shows the complete circuit. It uses two auxiliary PDs to accomplish the above. The timing diagrams as shown in FIG. 4D highlights the above features.
Example 3 Integrated circuit incorporating the method of eliminating the quadrature phase error
[0050] FIG. 5 shows the chip used to demonstrate embodiments of the invention. It has a 2.4GHz cross-coupled LC QVCO which provides the same four phases I, Q, �, � to an SSB mixer and the proposed PMC. With the SSB mixer, phase errors are measured using IBR measurements on a spectrum analyzer. Baseband side errors are corrected by flipping IBB and QBB. RF side errors are not corrected. Image rejection in an SSB mixer driven by I, Q, �, � is related to the phase difference between fundamental components of � - �and � - �. This is equal to (Δϕr1+Δϕf1+Δϕr2+Δϕf2)/4. The phase difference

between the rising edges of I and Q is Δϕr1, that between � and, � is Δϕr2. The phase differences between the respective falling edges are Δϕf1 and Δϕf2.
[0051] The EPD measures the phase difference between rising edges of the input waveforms. The chip includes two EPDs, one operating on the rising edge and another on the falling edge. For the latter, negative edge triggered counterparts are used. Two dummy EPDs are used to symmetrically load the 4 QVCO phases. An edge selector routes the appropriate edges to the two EPDs. Phase errors introduced in the edge selector are not corrected. Transmission gate MUXes are used for the selector since they have smaller mismatch induced phase errors than active digital MUXes. Phase errors in the sel ector are due t o (a) mismat ched switch r esist ances causing mismat ched phase shifts,smaller switch resistances reduce this and (b) quadrature signal feed-through in the off switches. Quadrature signal feed-through in the off switches is largely cancelled in this case since the MUX driving each output is connected to opposite phase quadrature signals from the QVCO.
[0052] The filtered dc is measured using a voltmeter and the phase error is computed offline. The PMC occu pi es 0.26mm x 0.16mm and consumes 3.2mA from 1.2V at 2.4GHz.I/Q phase errors were measured over the QVCO's tuning range of 2.35GHz to 2.55GHz on 5 chips. FIG. 6 shows phase errors measured with the proposed PMC versus that from the SSB mixer based method. The two agree well with each other with a maximum difference of 0.5o. This difference incl udes uncor rect ed mismatch-induced phase error in the SSB mixer which has a simulated σ of 0.15⁰. Phase errors in the proposed PMC are expected to be dominated by the selector and have a simulated σ of 0.15⁰. FIG. 6 also shows individual chip measurements over frequency and the performance summary. Below 80o, the edges come closer and systematic errors due to rise/fall profiles of QA and QB in the EPDs exceed 0.5. An on-chip technique for accurate measurement of quadrature phase errors in GHz speed signals down to a fraction of a degree is proposed. A low speed ADC and a small digital engine to compute the

relationship in Table. 1 are required for a completely on-chip implementation. A 0.13 μm prototype operates at 2.4 GHz while consuming 3.2mA from 1.2V. The operating frequency scales up with process similar to digital circuits. In a deep submicron process, most of the PMC except the input selector can be synthesized at GHz speeds.

WE CLAIM:
1. A method of measuring quadrature phase error (Δϕr1) in circuits involving two or
more signals comprising:
a. providing a first input signal to a first flip-flop of a phase detector and a
second input signal to a second flip-flop of the phase detector to obtain a first output
voltage V1, where
�1=���Q + ���1) + ��……………(1)
Where Kpd is the unknown gain and Ve is the offset voltage; wherein the first input signal leads the second input signal and thereby the flip-flops are configured to operate in a first mode;
b. interchanging the input signals between the flip-flops to obtain the second
output voltage V2,
�2 = ���(32�-���1) + ��……………(2)
wherein the flip-flops operate in the first mode;
c. providing the first input signal to the first flip-flop of the phase detector
and the second input signal to the second flip-flop of the phase detector to obtain the
third output voltage V3,
�3 = -���(32�-���1) + ��…………… (3)
wherein the second input signal leads the first input signal and thereby the flip-flops are configured to operate in a second mode;
d. interchanging the input signals between the flip-flops to obtain the fourth
output voltage V4,
�4 = -���(�2 + ���1)+��……………(4)
wherein the flip-flops operate in the second mode; and
e. combining the output voltages to eliminate the unknown gain Kpd and
offset voltage Ve and to determine the phase error (Δϕr1) given by
���1 = �(12 + (( ��11-+ ��2+- ��33-- ��44)))…………(6)

2. A phase error measurement circuit incorporating the method of claim 1.
3. The phase error measurement circuit of claim 2, wherein the circuit does not require a reference.
4. The phase error measurement circuit of claim 2, wherein the circuit is further configured to eliminate the phase error.
5. An error-compensating circuit architecture to eliminate phase errors between a first input signal and a second input signal comprising:
one or more phase detectors to measure the phase difference between the first
input signal and the second input signal, wherein
each phase detector comprises a first flip-flop receiving the first input signal and a second flip-flop receiving the second input signal wherein the flip-flops are configured to operate either in a first mode when the first input signal leads the second input signal or a second mode when the second input signal leads the first input signal; and
a first and a second auxiliary phase detector, wherein
the first auxiliary phase detector is configured to add a phase angle of integer multiples of π to the measured phase difference between the first input signal and the second input signal;
the second auxiliary phase detector configured to either initiate a reset command at a first predetermined time or to release the reset after a second predetermined time; and
on receiving the first input signal and the second input signal the circuit adds a
phase angle of integer multiples of π to the measured phase difference, initiates
the reset bit at the first predetermined time and releases the reset after the second
predetermined time to eliminate the phase error.

6. The circuit of claim 5, wherein the flip-flops comprise one or more control bits for operation in either the first mode or the second mode.
7. The circuit of claim 5 wherein the reset command is initiated at a first predetermined time when the outputs of both the flip-flops of the second auxiliary phase detector are in logic HIGH state.
8. The circuit of claim 5 wherein the reset command is released at a second predetermined time when the first input signal rises from its logic LOW state to a logic HIGH state.
9. An integrated circuit chip for measuring phase error between a first input signal and a second input signal comprising
an edge selector configured to receive a first input signal and a second
input signal;
a first enhanced phase error detector (EPD) configured to operate on the
rising edge of the input signals;
a second EPD configured to operate on the falling edge of the input
signals; wherein
the edge selector routes the appropriate edges to the first EPD and
the second EPD; an output selector to select the appropriate output from the first EPD or the second EPD; an analog to digital controller;
a digital engine incorporating the method of measuring quadrature phase error; wherein

on receiving the first input signal and the second input signal the integrated circuit chip computes the phase error.
10. The integrated circuit chip of claim 9 wherein the chip is implemented in system-on-chip applications for phase error diagnostic or phase correctional aid purposes.
11. An SSB up/down converter for a communication device incorporating the integrated circuit chip of claim 9 wherein the circuit detect s the phase error in the received input signals.
12. A phase modulator embodying the integrated circuit chip of claim 9 wherein the circuit compares the phase of the output signal with the phase of a reference signal to produce an error signal.