[DESCRIPTION]
[TITLE OF INVENTION]
PHASE LOCK LOOP WITH A MULTIPHASE OSCILLATOR
[TECHNICAL FIELD]
[0001]
The present invention relates to phase lock loops, and specifically to phase lock
loops using multiphase oscillators.
[BACKGROUND ART]
[0002]
Prior art techniques for phase determination in a phase lock loop are often difficult,
resource intensive, and not accurate enough. One such prior art system, disclosed in Staszewski
et al. (U.S. Patent No. 6,326,851), determines a digital fractional phase by passing a clock signal
from a 2.4 GHz voltage controlled oscillator through a chain of inverters. Each inverter
produces a clock pulse slightly delayed from the immediately previous inverter. The resulting
staggered clock phases are then sampled by a reference clock. The delay of inverters are
sensitive to process and temperature variations and is limited to a time resolution of 20 ps based
on the state of the technology. Since the phase resolution is dependent on the timing resolution,
the phase resolution is also limited.
[0003]
There is an unsolved need for a phase lock loop that has more accurate phase
resolution.
[SUMMARY OF INVENTION]
[0004]
The phase lock loop of the present invention includes a multiphase oscillator such as
a rotary traveling wave oscillator (RTWO) having a plurality of digital inputs, but instead of one
DQ flip-flop, a plurality of DQ flip-flops is used to clock the digital inputs. The plurality of
DQ flip-flops are offset in time from each other and drive the oscillator to generate a plurality of
multiphase signals. The plurality of DQ flip-flops activate the plurality of digital inputs in the
oscillator at zero crossing points of the traveling wave thereby eliminating perturbations in the
phase signals from the oscillator. A DQ flip-flop connected to the oscillator determines
direction of travel (clockwise or counterclockwise) of the traveling wave. A look-up table,
addressed by multiphase signals from the oscillator and the direction of the traveling wave,

determines the current fractional phase of the oscillator. The oscillator allows for higher ring
oscillation frequencies, thereby considerably increasing phase resolution. The increased phase
resolution is converted to digital form in the feedback path of the phase lock loop, permitting a
much finer phase resolution than heretofore possible while at the same time reducing phase
quantization noise. In a feed-forward path, frequency dividers divide an output signal of the
oscillator to a desired frequency increasing phase resolution in the transmitted signal.
[0005]
The exact nature of this invention, as well as the objects and advantages thereof, will
become readily apparent from consideration of the following specification in conjunction with
the accompanying drawings in which like reference numerals designate like parts throughout the
figures thereof and wherein:
[BRIEF DESCRIPTION OF DRAWINGS]
[0006]
[FIG 1]
FIG. 1 is a block diagram of a phase lock loop according the present invention;
[FIG. 2]
FIG. 2 is a pulse sequence showing clocking signals for the embodiment of FIG. 1;
[FIG. 3]
FIG. 3 is a schematic of a rotary traveling wave oscillator;
[FIG. 4]
FIG. 4 is a schematic of a variable capacitor circuit used in the rotary traveling wave
oscillator of FIG. 3;
[FIG. 5]
FIG. 5 is a graph of the phase signals of a rotary traveling wave oscillator;
[FIG. 6]
FIG. 6 is a plurality of pulse sequences representing multiple phase signals from a
rotary traveling wave oscillator;
[FIG. 7]
FIG. 7 is a series of waveforms showing the traveling wave at different points in a
rotary traveling wave oscillator according to the present invention;
[FIG. 8]
FIG. 8 is a conventional single DQ flip-flop rotary traveling wave oscillator;
[FIG. 9]
FIG. 9 is a series of waveforms showing the traveling wave at different points in a

prior art rotary traveling wave oscillator;
[FIG. 10]
FIG. 10 is a schematic symbol of a DQ flip-flop;
[FIG. 11]
FIG. 11 is a pulse sequence for the DQ flip-flop of FIG. 10;
[FIG. 12]
FIG. 12 is a pulse sequence for the DQ flip-flop of FIG. 10;
[FIG. 13]
FIG. 13 is a look-up table used in the embodiment of FIG. 1;
[FIG. 14]
FIG. 14 is a look-up table used in the embodiment of FIG. 1;
[FIG.15]
FIG. 15 is a plurality of pulse sequences in the embodiment of FIG. 1;
[FIG. 16]
FIG. 16 is a block diagram of a phase lock loop; and
[FIG. 17]
FIG. 17 is a frequency chart over time of the phase lock loop of the present
invention in operation.
[DESCRIPTION OF EMBODIMENTS]
[0007]
FIGURE 1, shows a phase lock loop according to the present invention. A phase
detector 11 receives a reference phase signal 41, a total phase signal 43, and a clock signal 45.
The reference phase signal 41 represents a carrier frequency to lock to. The phase detector 11
compares the reference phase signal 41 to the total phase signal 43 upon receipt of the clock
signal 45 and generates a control signal 47 which is proportional to the phase difference between
the reference phase signal 41 and the total phase signal 43. Ideally the phase difference is zero.
[0008]
A filter 13 receives the control signal 47 from the phase detector 11 and averages the
control signal 47, generating a filtered control signal 49. A AS modulator 15 receives the
filtered control signal 49 and performs a noise shaping function on the filtered control signal 49.
The AS modulator 15 oversamples the filtered control signal 49 to push any noise within the
filtered control signal 49 into a higher frequency range, producing the noise shaped or filtered
signal 51. Although the AE modulator 15 is used, it is contemplated that other types of noise
suppression filter could be used.

[0009]
A serial to parallel converter 17 separates the signal 51 into four separate signals 53,
55, 57, and 59 and slows down the clock speed. For example, if the clock frequency of the
signal 51 received by the serial to parallel converter 17 was 400 MHz, then each of the four
signals 53, 55, 57, and 59 would have a clock frequency equal to 400 MHz/4 or 100 MHz.
[0010]
The four signals 53, 55, 57, and 59 are transmitted to respective DQ flip-flops 19,21,
23, and 25. Although the serial to parallel converter 17 is shown as separating the high
frequency signal 51 into the four lower frequency signals 53, 55, 57, and 59, the serial to parallel
converter 17 could separate the high frequency signal 51 into any convenient number of lower
frequency signals.
[0011]
DQ flip-flops 19, 21, 23, and 25 receive the respective signals 53, 55, 57, and 59,
along with respective clock signals 61, 63, 65, and 67 and generate control signals 69, 71, 73,
and 75. The control signals 69, 71, 73, and 75 are phase-shifted from each other, according to
the clock signals 61, 63, 65, and 67.
[0012]
FIGURE 2 illustrates the clock signals 61, 63, 65, and 67. Frequency clock
(fclockl) corresponding to the clock signal 61, frequency clock (fclock2) corresponding to clock
signal 63, frequency clock (fclock3) corresponding to the clock signal 65, and frequency clock
(fclock4) corresponding to the clock signal 67. Each of the clock signals 61, 63, 65, and 67
may be generated by digital inputs within a multiphase oscillator 27, which can be a rotary
traveling wave oscillator as shown, or its equivalent. Each of the clock signals 61, 63, 65, and
67 are phase-shifted by different fixed amounts. The control signals 69, 71, 73, and 75
generated by the DQ flip-flops 19, 21, 23, and 25 respectively, are transmitted to various digital
inputs on the multiphase oscillator 27, and more specifically to capacitor control circuits
(FIGURES 3,4) used in the multiphase oscillator 27.
[0013]
In FIGURE 3, the multiphase oscillator 27 has a traveling wave 123 circling around
a loop past eight digital inputs 99, 101, 103, 105, 107, 109, 111, and 113. Although the
traveling wave 123 is shown circulating in a clockwise direction, it could also be circulating in a
counterclockwise direction. The four clock signals 61, 63, 65, and 67 are signals from four of
the eight digital inputs 99, 101, 103, 105, 107, 109, 111, and 113. For example, the clock signal
61 could be from the digital input 99, the clock signal 63 could be from the digital input 103, the
clock signal 65 could be from the digital input 107, and the clock signal 67 could be from the

digital input 111.
[0014]
As the traveling wave 123 circulates around the loop, each digital input in the loop
of the multiphase oscillator 27 produces a phase signal. A complete circumvention of the loop
by the traveling wave represents a 180° phase change. Two complete rotations represent a 360°
phase change. For example, if a digital input outputs a "1" when a point on a traveling wave
passes a first time, the digital input will output a "0" when the same point of the traveling wave
passes the digital input a second time. The oscillation 141 of the multiphase oscillator 27 of the
present invention is shown in FIGURE 5. The pulse outputs from each of the digital inputs
P(l) 99, P(2) 101, P(3) 103, P(4) 105, P(5) 107, P(6) 109, P(7) 111, and P(8) 113 is shown in
FIGURE 6. The phase signals from each digital input are phase-shifted from each other.
[0015]
Variable capacitor circuits 115, 117, 119, and 121 are connected to the multiphase
oscillator 27 (FIGURE 3). The variable capacitor circuits 115, 117, 119, and 121 receive the
control signals 69, 71, 73, and 75 from the lower frequency respective DQ flip-flops 19, 21, 23,
and 25. As shown in FIGURE 4, each of the variable capacitor circuits 115, 117, 119, and 121
include a first inverter 124, a second inverter 125, and a variable capacitor 127, which consists of
a plurality of small varactors connected in parallel. The control signals 69, 71, 73, and 75
trigger the varactors in each of the variable capacitor circuits 115, 117, 119, and 121. The
control signals 69, 71, 73, and 75 turn the varactors on/off and control oscillation frequency of
the multiphase oscillator 27.
[0016]
In FIGURE 7, by utilizing the control signals 69, 71, 73, and 75 (FIGURE 1), the
timing for switching the variable capacitor circuits 115, 117, 119, and 121 (FIGURE 3) can be
selected to be at zero crossings 142,144, 146, and 148 of the travelling wave, as indicated by the
waveforms for P(l), P(3), P(5), and P(7), respectively of FIGURE 7. By aligning the timing of
capacitor switching in this manner, perturbations due to capacitor switching present in prior art
devices is eliminated.
[0017]
A prior art conventional single DQ flip-flop digital controlled oscillator is shown in
FIGURE 8. It includes a A£ modulator 143, a single DQ flip-flop 145, and a RTWO 147.
The AZ modulator 143 receives and shapes a signal 149 to generate a signal 151 which is
transmitted to the single DQ flip-flop 145. The single DQ flip-flop 145 also receives a clock
signal 153 which is used, along with the signal 151, to generate control signals 155. The
RTWO 147 utilizes the control signals 155 to generate a multiphase signal 157.

[0018]
Referring to FIGURE 9 and assuming that the RTWO 147 utilizes the same digital
input structure as the multiphase oscillator 27 of FIGURE 3, the digital inputs 103 and 111, as
indicated by the signal wave for P(3) and P(7) will experience large perturbations due to
capacitor switching. This is because the single DQ flip-flop switches all digital inputs at the
same time, leaving no room for adjustment to match zero crossings of the traveling wave in the
RTWO 147. The perturbations created, as shown in FIGURE 9, increase phase noise
substantially.
[0019]
Referring again to FIGURE 1, the multiphase oscillator 27 transmits an output
signal 72 in a feed-forward path to a multiplexer 80, a frequency divider 74, and a frequency
divider 76. The output signal 72 is at the operating frequency of the multiphase oscillator 27.
If the multiphase oscillator 27 is operating at 4 GHz, then the output signal 72 has a frequency of
4 GHz. The frequency dividers 74 and 76 divide the frequency of the output signal 72 to
generate lower frequency signals 86 and 88, respectively, which are transmitted to the
multiplexer 80. The frequency divider 74 may divide the frequency of the output signal 72 by
two, while the frequency divider 76 may divide the frequency of the output signal 72 by four.
Thus, the signal 86 has a frequency of 2 GHz while the signal 88 has a frequency of 1 GHz.
The frequency dividers 74 and 76 are contemplated as capable of dividing the multiphase
oscillator frequency by any amount to generate a lower frequency, as required.
[0020]
The multiplexer 80 selects the output signal 72, the frequency divided signal 86, or
the frequency divided signal 88 to send to a transmitter (not shown). The multiplexer 80 selects
one of the signals based on the frequency of the signal which is used by the transmitter. For
example, if the transmitter is operating in a GSM mode where a 900 MHz frequency is used, the
multiplexer 80 selects the frequency divided signal 88. However, if the transmitter is operating
in a PCS mode where a 1900 MHz frequency is used, the multiplexer 80 selects the frequency
divided signal 86.
[0021]
The higher the frequency division of the output signal 72, the higher the phase
resolution of the resulting lower frequency signal. For example, assume the output signal 72
was at 4 GHz, and the multiphase oscillator 27 had 8 digital inputs, producing 8 phases for every
180 degrees, and 16 phases for every 360 degrees in the output signal 72. The phase resolution
would be 3607(8x2) = 22.5 degrees. If the output signal 72 is divided by two to produce the
frequency devided signal 86 at a frequency of 2 GHz, there are 16 phases for every 180 degrees,

and 32 phases for every 360 degrees. The phase resolution of the frequency devided signal 86
would be 360°/(8x2x2) =11.25 degrees. If the output signal 72 is divided by four to produce
the frequency devided signal 86 at a frequency of 1 GHz, there are 32 phases for every 180
degrees, and 64 phases for every 360 degrees. The phase resolution of the frequency divided
signal 88 is 360°/(8x2x2x2) = 5.625 degrees. Thus, phase resolution can be improved not only
by increasing the number of digital inputs on the multiphase oscillator 27, but also by frequency
division of the output signal 72.
[0022]
Referring now to FIGURE 1 and a phase to digital converter (feedback path) 7, a
direction determination unit and fractional phase look-up table 29 receives multiphase signals 77
from the multiphase oscillator 27 along with a clock reference signal 81. The direction
determination unit and fractional phase look-up table 29 determines the current fractional phase
of the multiphase oscillator 27, at the time indicated by the clock reference signal 81.
[0023]
The direction of the traveling wave is determined by a DQ flip-flop 131 (FIGURE
10) located in the direction determination unit and fractional phase look-up table 29. The DQ
flip-flop 131 is connected between any two digital inputs in the multiphase oscillator 27, such as
between the P(l) digital input 99 and the P(2) digital input 101 (not shown). The DQ flip-flop
131 receives a signal 133 from the P(l) digital input 99 and a signal 135 from the P(2) digital
input 101 and outputs a digital output 137.
[0024]
FIGURE 11 shows the pulse signal from the P(l) digital input 99, the P(2) digital
input 101, and the P(3) digital input 103 when the traveling wave 123 of the multiphase
oscillator 27 is circulating in a clockwise direction. As shown, P(l) and P(2) are both high
when P(3) is low.
[0025]
FIGURE 12 shows the pulse signals from the P(l) digital input 99, the P(2) digital
input 101, and the P(3) digital input 103 when the traveling wave 123 of the multiphase
oscillator 27 is circulating in a counterclockwise direction. In this case P(l) is low and P(2) is
high when P(3) is high. In both FIGURE 11 and FIGURE 12, the signal 133 from the P(l)
digital input 99 and the signal 135 from the P(2) digital input 101 can be taken at time 139. The
digital value of signal 133 and signal 135 determines the digital output 137 of the DQ flip-flop
131. The digital output 137 determines whether the traveling wave is traveling in a clockwise
direction or a counterclockwise direction.
[0026]

At time 139, if the traveling wave is rotating in a clockwise direction, traveling from
the P(l) digital input 99 to the P(2) digital input 101, the digital output 137 is high or "1." If the
traveling wave is rotating in a counterclockwise direction traveling from the digital input 101 to
the digital input 99 at time 139, the digital output 137 is low or "0."
[0027]
The direction determination unit and fractional phase look-up table 29 (FIGURE 1)
also includes a fractional phase look-up table to determine the phase of the traveling wave at any
given time. Once direction of the traveling wave has been determined, a clockwise or
counterclockwise look-up table is used to determine phase of the traveling wave. For example,
if the traveling wave is traveling clockwise, a clockwise fractional phase look-up table, such as
shown in FIGURE 13, is used. If the traveling wave is traveling counterclockwise, a
counterclockwise fractional phase look-up table, such as shown in FIGURE 14, is used.
[0028]
In FIGURE 13 and FIGURE 14, the eight digital inputs P(l) 99, P(2) 101, P(3) 103,
P(4) 105, P(5) 107, P(6) 109, P(7) 111, and P(8) 113 at any given time, determine the current
fractional phase of the traveling wave. For example, assuming the traveling wave is rotating
clockwise, and the digital inputs are P(l) = 1, P(2) - 1, P(3) = 1, P(4) = 0, P(5) = 0, P(6) = 0,
P(7) = 0, and P(8) = 0, from the clockwise table of FIGURE 13, the traveling wave has a current
fractional phase between 45 and 67.5 degrees. If the traveling wave is rotating
counterclockwise, and the digital inputs are P(l) = 1, P(2) = 1, P(3) = 1, P(4) = 0, P(5) = 0, P(6)
= 0, P(7) = 0, and P(8) = 0, from the counterclockwise table of FIGURE 14, the traveling wave
has a current fractional phase between 315 and 337.5 degrees.
[0029]
The fractional phase look-up tables of FIGURE 13 and FIGURE 14 assume that the
traveling wave starts at the digital input 99. However, the traveling wave can start at any digital
input and the fractional phase look-up tables will adjust accordingly. The fractional phase
look-up tables illustrated contain information for eight digital inputs. However, more digital
inputs could be used. If the number of digital inputs in the multiphase oscillator 27 is increased,
each phase range is reduced accordingly. The size of each phase range corresponds to 180
degrees divided by the number of digital inputs. In FIGURE 9 and FIGURE 10, the size of the
phase range is 22.5 degrees. If, however, there were 16 digital inputs, then the size of the phase
range would be 180 degrees divided by 16, or 11.25 degrees. Increasing the digital inputs
increases phase resolution of the multiphase oscillator 27. It is contemplated that .10,000 or
more digital inputs could be used in the multiphase oscillator 27. Advantageously, in the
present invention the phase resolution is not carrier frequency dependent thereby eliminating the

need for a calibration circuit. Furthermore, the phase resolution is not limited by inverter delay.
[0030]
The current fractional phase value of the traveling wave is determined by the
direction determination unit and fractional phase look-up table 29 and is provided as a fractional
phase signal 83 to a re-clock unit 79 (FIGURE 1).
[0031]
The phase to digital converter 7 embodiment of the multiphase oscillator 27 and the
direction determination unit and fractional phase look-up table 29 shown in FIGURE 1 provide a
system that reduces the operational frequency, size, and current consumption. Moreover,
design complexity of the phase to digital converter 7 is reduced.
[0032]
A divide by N circuit 9 (FIGURE 1) includes three D flip-flops 31, 33, and 35.
The D flip-flop 31 receives one of multiphase signals 78 from the multiphase oscillator 27 and a
feedback signal 85 from the D flip-flop 33. The D flip-flop 31 transmits a signal 87 to the D
flip-flop 33. The D flip-flop 33 receives the signal 87 and one of the multiphase signals 78
from the multiphase oscillator 27. The D flip-flop 33 transmits a digital phase indicating signal
89 (Dl of FIGURE 15) to the D flip-flop 35, an accumulator 39, and a fast count unit 37. The
D flip-flop 35 receives the digital phase indicating signal 89 and one of the multiphase signals 78
(PI of FIGURE 15) from the multiphase oscillator 27 and transmits a digital phase indicating
signal 91 (D2 of FIGURE 15) to the fast count unit 37. The divide by N circuit 9 may be a
divide by 4 circuit. Accordingly, the digital phase indicating signal 89 (Dl) is HIGH for two
periods and LOW for two periods. The digital phase indicating signal 91 (D2) is HIGH for two
periods and LOW for two periods, but is delayed by one period from the digital phase indicating
signal 89 (Dl). Thus, the digital phase indicating signal 89 (Dl) and the digital phase
indicating signal 91 (D2) can form N unique combinations, which in this case is four unique
combinations of HIGH and LOW signals. For example, the digital phase indicating signal 89
(Dl) and the digital phase indicating signal 91 (D2) can have the combinations HIGH-LOW,
HIGH-HIGH, LOW-HIGH, and LOW-LOW. The divide by N circuit 9 reduces operational
speed of the accumulator 39 by allowing the accumulator 39 to increment every Nth period
instead of every period.
[0033]
The fast count unit 37 receives the digital phase indicating signal 91 (D2) from the
D flip-flop 35, the digital phase indicating signal 89 (Dl) from the D flip-flop 33, along with one
of the multiphase signals 78 (PI) from the multiphase oscillator 27 and generates a fast count
signal 95 (FI of FIGURE 15). If the divide by N circuit 9 is a divide by 4 circuit, then the fast

count signal 95 would have a value of 0, 1, 2, 3, and repeat continuously. Every value of the
fast count signal 95 (FI) represents the time the traveling wave in the multiphase oscillator 27
has rotated 360 degrees. Each time one of the multiphase signals 78 (PI) from the multiphase
oscillator 27 switches from "0" to "1," or "1" to "0," the traveling wave has completed 180
degrees. When one of the multiphase signals 78 (PI) switches from "0" to "1" and back to "0,"
or from "1" to "0" and back to "1," the traveling wave has completed 360 degrees. The fast
count signal 95 (FI) is incremented when the traveling wave of the multiphase oscillator 27 has
completed 360 degrees.
[0034]
When the traveling wave of the multiphase oscillator 27 has rotated 450 degrees, the
fast count signal 95 (FI) would be 1, since the quotient of 450/360 is 1. When the traveling
wave of the multiphase oscillator 27 has rotated 900 degrees, then the fast count signal 95 (FI)
would be 2, since 900/360 has a quotient of 2. When the traveling wave of the multiphase
oscillator 27 has rotated 1620 degrees, the fast count signal 95 (FI) would be 0, since 1620/360
has a quotient of 4.
[0035]
The accumulator 39 receives and accumulates the digital phase indicating signals 89
(Dl) from the D flip-flop 33 in the divide by N circuit 9 to generate an accumulator signal 93 (AI
of FIGURE 15). The accumulator signal 93 (AI of FIGURE 15) is incremented once every
time the digital phase indicating signal 89 (Dl) rises. Thus, the accumulator signal 93 is
incremented for every Nth time the traveling wave of the multiphase oscillator 27 has completed
360 degrees. When the traveling wave of the multiphase oscillator 27 has rotated 450 degrees,
for example, the fast count signal 95 (FI) will be 1 and the accumulator signal 93 (AI) will be 0.
When the traveling wave of the multiphase oscillator 27 has traversed 900 degrees, the fast count
signal 95 (FI) will be 2, and the accumulator signal 93 (AI) will be 0. When the traveling wave
of the multiphase oscillator 27 has rotated 1620 degrees, the fast count signal 95 (FI) will be 0,
and the accumulator signal 93 (AI) will be 1. The accumulator signal 93 (AI) is sent to the
re-clock unit 79.
[0036]
The re-clock unit 79 receives the fractional phase signal 83, one of the multiphase
signals 78, the fast count signal 95, and the accumulator signal 93, and generates the total phase
signal 43. The total phase signal 43 is calculated according to the formula:
[(AI x N) + FI] x 360 + Frac
Where AI is the accumulator signal 93, N is the dividing factor in the divide by N circuit 9, FI is
the fast count signal 95, and Frac is the fractional phase signal 83. The total phase signal 43

and the clock signal 45 are transmitted to the phase detector 11.
[0037]
FIGURE 15 illustrates the pulse signals in the phase to digital converter 7 of
FIGURE 1. The ClkRef signal corresponds to the clock reference signal 81. P(l) corresponds
to one of the multiphase signals 78 supplied to the divide by N circuit 9. D(l) corresponds to
the digital phase indicating signal 89 from the D flip-flop 33. D(2) corresponds to the digital
phase indicating signal 91 from the D flip-flop 35. FI corresponds to the fast count signal 95
from the fast count unit 37. AI corresponds to the accumulator signal 93. The signals for P(l)
correspond to the output of digital input 99 in the multiphase oscillator 27 (FIGURE 1). The
period for P(l) corresponds to the time period that it takes for the traveling wave of the
multiphase oscillator 27 to rotate 360 degrees. That is, the P(l) signal switches between "1"
and "0" at each 180 degrees of the traveling wave in the multiphase oscillator 27. The signal
switches between "0" and "1" at each 360 degrees of the traveling wave in the multiphase
oscillator 27.
[0038]
The time when the signal for P(l) starts is indicated by timeline 163. The clock
reference ClkRef rises at timeline 161. A differential time period 159 therefore exists between
the clock reference ClkRef rise at timeline 161 and the starting time for the P(l) digital input of
the multiphase oscillator 27 at timeline 163. This time period 159 corresponds to the fractional
phase signal 83 sent by the direction determination unit and fractional phase look-up table 29 to
the re-clock unit 79.
[0039]
The value of FI is determined by the D(l) and D(2) flip-flops 33 and 35. The value
of FI which represents each 360° rotations of the travelling wave is stored in a look-up table in
the fast count unit 37.
[0040]
FIGURE 16 shows a simplified block diagram of a phase lock loop using a
multiphase oscillator within which the present invention could be used. The phase lock loop
includes a phase detector 165, a filter 167, and a multiphase oscillator 169. The phase detector
165 receives a reference phase signal 171, an M-bit integer phase signal 179, and an N-bit
fractional phase signal 177 to generate a control signal 173 which is transmitted to the filter 167.
The filter 167 averages the control signal 173 to generate a filtered signal 175 which is
transmitted to the multiphase oscillator 169. The multiphase oscillator 169 then generates the
N-bit fractional phase signal 177 and the M-bit integer phase signal 179 which are transmitted to
the phase detector 165. The N-bit fractional phase signal 177 mirrors the fractional phase

signal 83 disclosed above. The M-bit integer phase signal 179 can be calculated, for example,
using the formula AI x 4 + FI. The M-bit integer phase signal 179 is multiplied by 360 and the
result is added to the N-bit fractional phase signal to produce a total phase signal. The total
phase signal is then compared with the reference phase signal 171 to generate the control signal
173.
[0041]
FIGURE 17, shows the frequency response of a phase lock loop according to the
present invention, operating with a carrier frequency set to 820 MHz, voltage controlled
oscillator ("VCO") sensitivity set with Kv equal to 30 MHz/V, and the clock reference signal set
to 50 MHz. As seen from the graph, phase correction is performed within microseconds and
the circuit remains phase locked thereafter.
[INDUSTRIAL APPLICABILITY]
[0042]
The phase lock loop of the present invention is useful as a phase lock loop using a
multiphase oscillator or the like such as a rotary traveling wave oscillator (RTWO) having a
plurality of digital inputs.
[REFERENCE SIGNS LIST]
[0043]
11,165 phase detector
13, 167 filter
15,143 AE modulator
17 serial to paralle 1 converter
19, 21, 23, 25, 131, 145 DQ flip-flop
27, 169 multiphase oscillator
29 direction determination unit and fractional phase look-up table
31,33,35 D flip-flop
37 fast count unit
39 accumulator
74, 76 frequency divider
79 re-clock unit
80 multiplexer
115, 117, 119, 121 variable capacitor circuit
124, 125 inverter

127 variable capacitor
147 rotary traveling wave oscillator (RTWO)

We Claim:
[CLAIM 1]
A phase lock loop comprising:
a phase detector for generating a control signal indicating a difference between a
reference phase signal and a feedback phase signal;
an oscillator responsive to the control signal for generating a plurality of multiphase
signals; and
a fractional phase look-up table responsive to the plurality of multiphase signals for
generating a fractional phase signal.
[CLAIM 2]
The phase lock loop of claim 1 wherein the oscillator is a rotary traveling wave
oscillator (RTWO).
[CLAIM 3]
The phase lock loop of claim 2 wherein the fractional phase look-up table comprises
a first look-up table for a clockwise rotating wave in the RTWO and a second look-up table for a
counterclockwise rotating wave in the RTWO.
[CLAIM 4]
The phase lock loop of claim 3 further comprising a traveling wave direction
determining unit connected to the RTWO for determining whether a traveling wave in the
RTWO is traveling in a clockwise or counterclockwise direction.
[CLAIM 5]
The phase lock loop of claim 4 wherein the traveling wave direction determining
unit includes a DQ flip-flop receiving two of the plurality of multiphase signals from the RTWO.
[CLAIM 6]
The phase lock loop of claim 2 further comprising a plurality of DQ flip-flops
responsive to the control signal from the phase detector, each DQ flip-flop generating a reduced
clocked control signal at a fraction of the frequency of the control signal.
[CLAIM 7]
The phase lock loop of claim 6 wherein the RTWO is responsive to the reduced

clocked control signals.
[CLAIM 8]
The phase lock loop of claim 2 further comprising a divide by N circuit for receiving
one of the plurality of multiphase signals and generating a first digital phase indicating signal
and a second digital phase indicating signal.
[CLAIM 9]
The phase lock loop of claim 8 further comprising a fast count unit for receiving the
first digital phase indicating signal and the second digital phase indicating signal, and generating
a fast count signal.
[CLAIM 10]
The phase lock loop of claim 9 further comprising an accumulator for receiving the
second digital phase indicating signal and generating an accumulator signal.
[CLAIM 11]
The phase lock loop of claim 10 further comprising a re-clock unit for receiving the
fractional phase signal, the fast count signal, and the accumulator signal, and generating the
feedback phase signal.
[CLAIM 12]
The phase lock loop of claim 2 further comprising:
a frequency divider for receiving an output signal from the RTWO and frequency
dividing the output signal to generate a frequency divided signal; and
a multiplexer for receiving the output signal from the RTWO and the frequency
divided signal and selecting either the output signal or the frequency divided signal.
[CLAIM 13]
A method for locking onto a reference phase comprising the steps of:
generating a control signal indicating a difference between a reference phase signal
and a feedback phase signal;
generating a plurality of multiphase signals in response to the control signal; and
generating a fractional phase signal utilizing a fractional phase look-up table
responsive to the plurality of multiphase signals.

[CLAIM 14]
The method of claim 13 further comprising the step of determining whether a wave
in an oscillator is traveling in a clockwise or counterclockwise direction.
[CLAIM 15]
The method of claim 14 wherein the fractional phase look-up table comprises a first
look-up table for a clockwise rotating wave in the oscillator and a second look-up table for a
counterclockwise rotating wave in the oscillator.
[CLAIM 16]
A phase lock loop comprising:
a phase detector for generating a control signal indicating the difference between a
reference phase signal and a feedback phase signal;
a plurality of DQ flip-flops responsive to the control signal, each DQ flip-flop
generating a clock signal at a fraction of the frequency of the control signal; and
a multiphase oscillator responsive to the clock signals for generating a plurality of
multiphase signals that are used to provide a fractional phase signal.
[CLAIM 17]
The phase lock loop of claim 16 wherein the multiphase oscillator is a RTWO.
[CLAIM 18]
The phase lock loop of claim 17 wherein the RTWO includes a plurality of
capacitors, each of the plurality of capacitors being activated by one of the plurality of DQ
flip-flops at a zero crossing of the traveling wave in the RTWO.
[CLAIM 19]
The phase lock loop of claim 18 further comprising a serial to parallel unit for
receiving the control signal from the phase detector and generating a plurality of reduced
frequency signals, each of the plurality of reduced frequency signals being transmitted to one of
the plurality of DQ flip-flops.
[CLAIM 20]
The phase lock loop of claim 17 further comprising a fractional phase look-up table

including a first look-up table for a clockwise rotating wave in the RTWO and a second look-up
table for a counterclockwise rotating wave in the RTWO, the fractional phase look-up table
responsive to the plurality of multiphase signals for generating the fractional phase signal.
[CLAIM 21]
The phase lock loop of claim 18 further comprising a traveling wave direction
determining unit connected to the RTWO for determining whether the traveling wave in the
RTWO is rotating in a clockwise or counterclockwise direction.
[CLAIM 22]
The phase lock loop of claim 17 further comprising a divide by N circuit for
receiving one of the plurality of multiphase signals from the RTWO and generating a first digital
phase indicating signal and a second digital phase indicating signal.
[CLAIM 23]
The phase lock loop of claim 22 further comprising:
a fast count unit for receiving the first digital phase indicating signal and the second
digital phase indicating signal, and generating a fast count signal;
an accumulator for receiving the second digital phase indicating signal and
generating an accumulator signal; and
a re-clock unit for receiving the fractional phase signal, the fast count signal, and the
accumulator signal to generate the feedback phase signal.
[CLAIM 24]
The phase lock loop of claim 17 further comprising:
a frequency divider for receiving an output signal from the RTWO and frequency
dividing the output signal to generate a frequency divided signal; and
a multiplexer for receiving the output signal from the RTWO and the frequency
divided signal and selecting either the output signal or the frequency divided signal.
[CLAIM 25]
A method for locking onto a reference phase comprising the steps of:
generating a control signal indicating a difference between a reference phase signal
and a feedback phase signal;
generating a plurality of reduced frequency control signals in parallel from the

control signal;
generating a plurality of multiphase signals in an oscillator in response to the
plurality of reduced frequency control signals; and
generating a fractional phase signal utilizing a fractional phase look-up table
responsive to the plurality of multiphase digital signals.
[CLAIM 26]
The method of claim 25 further comprising the step of activating a plurality of
capacitors with the plurality of reduced frequency control signals at zero crossings of the
traveling wave in the oscillator.
[CLAIM 27]
A phase lock loop comprising:
a phase detector for generating a control signal indicating the difference between a
reference phase signal and a fractional phase signal; and
a multiphase oscillator responsive to the control signal for generating a plurality of
multiphase signals, the plurality of multiphase signals being used to generate a fractional phase
signal.
[CLAIM 28]
The phase lock loop of claim 27 wherein the multiphase oscillator is a RTWO.
[CLAIM 29]
The phase lock loop of claim 28 further comprising a divide by N circuit for
receiving one of the plurality of multiphase signals from the oscillator and generating a first
digital phase indicating signal and a second digital phase indicating signal.
[CLAIM 30]
The phase lock loop of claim 29 further comprising a fast count unit for receiving
the first digital phase indicating signal and the second digital phase indicating signal, and
generating a fast count signal.
[CLAIM 31]
The phase lock loop of claim 30 further comprising an accumulator for receiving the
second digital phase indicating signal and generating a an accumulator signal.

[CLAIM 32]
The phase lock loop of claim 31 further comprising a re-clock unit for receiving the
fractional phase signal, the fast count signal, and the accumulator signal to generate a feedback
phase signal.
[CLAIM 33]
The phase lock loop of claim 32 wherein the RTWO includes a plurality of
capacitors, each of the plurality of capacitors being activated at zero crossings of the traveling
wave in the RTWO.
[CLAIM 34]
The phase lock loop of claim 33 further comprising a plurality of DQ flip-flops,
each of the plurality of DQ flip-flops activating one of the plurality capacitors.
[CLAIM 35]
The phase lock loop of claim 34 further comprising a serial to parallel unit for
receiving the control signal from the phase detector and generating a plurality of reduced
frequency control signals in parallel for activating the plurality of DQ flip-flops.
[CLAIM 36]
The phase lock loop of claim 28 further comprising:
a frequency divider for receiving an output signal from the RTWO and frequency
dividing the output signal to generate a frequency divided signal; and
a multiplexer for receiving the output signal from the RTWO and the frequency
divided signal and selecting either the output signal or the frequency divided signal.
[CLAIM 37]
A phase to digital converter, comprising:
an oscillator generating a plurality of multiphase signals; and
a fractional phase look-up table responsive to the plurality of multiphase signals for
generating a fractional phase signal.
[CLAIM 38]
The phase to digital converter of claim 37 wherein the oscillator is a rotary traveling

wave oscillator (RTWO).
[CLAIM 39]
The phase to digital converter of claim 37 further comprising a divide by N circuit
for receiving one of the plurality of multiphase signals from the oscillator and generating a first
digital phase indicating signal and a second digital phase indicating signal.
[CLAIM 40]
The phase to digital converter of claim 39 further comprising a fast count unit for
receiving the first digital phase indicating signal, the second digital phase indicating signal, and a
multiphase signal from the oscillator, and generating a fast count signal for each 360° multiphase
signal from the oscillator.
[CLAIM 41]
The phase to digital converter of claim 40 further comprising an accumulator for
receiving the second digital phase indicating signal and generating a accumulator signal for each
Nth 360° multiphase signal from the oscillator.
[CLAIM 42]
The phase to digital converter of claim 38 wherein the fractional phase look-up table
comprises a first look-up table for a clockwise rotating wave in the RTWO and a second look-up
table for a counterclockwise rotating wave in the RTWO.
[CLAIM 43]
The phase to digital converter of claim 38 further comprising a traveling wave
direction determining unit connected to the RTWO for determining whether a traveling wave in
the RTWO is traveling in a clockwise or counterclockwise direction.
[CLAIM 44]
The phase to digital converter of claim 43 wherein the traveling wave direction
determining unit includes a DQ flip-flop receiving two of the plurality of multiphase signals
from the RTWO.

ABSTRACT

A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs,
A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals
to remove control phase information from the oscillator in digital form. A DQ flip-flop
connected between any two digital inputs on the oscillator determines direction of the traveling
wave. The direction and phase information address a look-up table to determine the current
fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator
frequency. A total phase indicator signal for the oscillator is determined using the current
fractional phase. The total phase is compared to a reference phase to produce a control signal
for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a
high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase
resolution.