Abstract: Abstract Phase Sequence Detection in Three Phase Power System According to embodiments of the invention, a phase sequence detection arrangement for a three phase three wire AC power system is disclosed. The disclosed system includes a first conductor (LI), a second conductor ( L2) and a third conductor (L3) such that each conductor (LI, L2, L3) carries alternating current (AC) of same frequency and voltage amplitude and with a phase difference, a single D flip flop circuit (210) connected to the first conductor (LI) and the second conductor ( L2) in series for detecting if phase in the conductors (LI, L2, L3) is in sequence or not; and a DC power supply for providing an input voltage to the D flip flop circuit (210); wherein the Output of the D flip flop (210) is a control signal that may detect phase sequence of the three phase three wire AC.
FIELD OF INVENTION
The invention relates to three phase power systems and, more particularly, to phase sequence detection in three phase power systems.
BACKGROUND
Incorrect phase sequence within a three-phase power system is called phase reversal. Phase reversal usually occurs due to mistakes made during equipment installation, maintenance, or modifications to the facility power system.
When the phase sequence of a three-phase system is incorrect, the connected three-phase motors and other rotating equipment runs in the opposite direction. In many cases, this can cause a hazardous condition that may destroy product, damage machinery, and injure personnel.
Existing solutions for phase sequence detection are either dependent on software or include more number of hardware components. Hence, there is a need for developing a method for phase sequence detection that is not dependent on software and includes minimum number of hardware components, thereby minimizing the cost.
The present invention is directed to overcoming one or more of the problems as set forth above.
SUMMARY OF THE INVENTION
Exemplary embodiments of the invention disclose a circuit for phase sequence detection pT a three phase three wire AC power system. The phase sequence detection circuit monitors a three phase AC sequence and provides an output indicative of phase sequence of the three
phases. According to an embodiment, the circuit includes a single D flip flop for detecting if phase is in sequence or not. Output of the D flip flop is a control signal that detects phase sequence of three phase AC. According to an embodiment, the control signal output may be low or high. According to an exemplary embodiment, the control signal maybe high if phases of the three phase AC input are in sequence and low if phases of the three phase AC input are not in sequence.
BRIEF DESCRIPTION OF DRAWINGS
Other objects, features, and advantages of the invention will be apparent from the following
description when read with reference to the accompanying drawings. In the drawings, wherein
like reference numerals denote corresponding parts throughout the several views:
Figure 1 illustrates pulse waveforms of a three phase AC power system, according to an
embodiment of the invention;
Figure 2 shows a phase sequence detection circuit of a three phase three wire AC power system,
according to an exemplary embodiment of the invention;
Figure 3 shows pulse waveforms of a phase sequence detector when three phases of a three
phase three wire AC power system are in phase, according to an exemplary embodiment of the
invention; and
Figure 4 shows pulse waveforms of a phase sequence detector when three phases of a three
phase three wire AC power system are out of phase, according to an exemplary embodiment
of the invention.
DETAILED DESCRIPTION OF DRAWINGS
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes
various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
According to embodiments of the invention, a circuit for a phase sensitive detector is disclosed.
Figure 1 illustrates a pulse waveform of a three-phase alternate current (AC) power system, according to an embodiment of the invention. The three phase AC power system includes three conductors and each conductor carries AC of same frequency and voltage amplitude relative to a common reference. However, the three conductors have a phase difference of one third of a cycle between each of the three conductors. Due to the phase difference, voltage on any conductor reaches its peak value at one third of a cycle after one of the other conductors and one third of a cycle before the remaining conductor.
The three AC lines namely Line 1 (L1 ), Line 2 (L2) and Line 3 (L3) shown in Figure 1 represent phase 1, phase 2 and phase 3 respectively. The phase difference between the three lines LI, L2 and L3 is uniform and each phase reaches peak value in one third of a cycle. The phase I (Line 1) reaches peak first, phase 2(Line 2) follows phase l(Line 1) and phase 3(Line 3) follows phase 2(Line 2).
Figure 2 shows a phase sequence detection arrangement/circuit of the three phase three wire AC power system, according to an embodiment of the invention. The phase sequence detection
arrangement/circuit monitors the three phase three wire AC sequence and provides an output indicative of the phase sequence of the three phases.
In Figure 2, Line 1 (L1), Line 2 (L2) and Line 3 (L3) correspond to phase 1, phase2 and phase3 respectively of the three phase three wire AC power system. According to an embodiment, the lines LI, L2 and L3 maybe identified by a predefined color code. The color codes of lines LI, L2 and L3 may vary depending on various factors such as legal requirements prescribed by a specific country.
A first capacitor (202) may be connected in series with a first resistor (206) to provide impedance for the Line 1 and a second capacitor (204) may be connected in series with a second resistor (208) to provide impedance for the Line2. The impedance for Linel and Line2 may be required to produce appropriate voltage for a single D flip flop (210) circuit connected to the Line 1 & Line 2. A voltage drop may occur across the capacitors (202, 204) and remaining voltage may be fed to a bridge rectifier comprising of plurality of a first diode (212), a second diode (214), a third diode (216) and a fourth diode (218).
According to an embodiment, the third diode (216) and the fourth diode (218) may be Zener diodes. The breakdown value of the third and fourth diodes (216, 218) depends on the voltage that needs to be provided as input to a DC power supply. The output of the DC power supply provides a supply voltage needed for the D flip flop (210). The D flip flop (210) may have a data input, a clock input and a logic output.
According to embodiments of the invention, the combination of the capacitors (202, 204), the resistors (206, 208) and the diodes (212, 214,216, 218) may be used to generate a wave shaped signal from the AC input and provide the wave shaped input to the D flip flop (210).
According to yet another embodiment, a DC to DC converter (220) may be used to convert the voltage generated from the Lines (LI, L2and L3) to appropriate voltage required for the D flip flop (210). According to an embodiment, an external voltage source may be used in place of a DC to DC converter.
According to an exemplary embodiment an another set of resistors (222, 224) and diodes (226 228) may be used to further reduce the voltage generated by the bridge rectifier. According to another exemplary embodiment, the resistor (222, 224), the diodes (226, 228) may not be required in the phase sequence detection circuit.
According to yet another embodiment, an another set of capacitors (230, 232) may be used for decoupling a high frequency noise such as, but not limited to, inductive noise. According to an embodiment, the capacitors (230, 232) may be of lower value as compared to first and second capacitors (202, 204). According to an exemplary embodiment, the capacitors (230, 232) may not be required in the phase sequence detection circuit.
According to an exemplary embodiment, the diode (226) may be connected to the clock input of the D flip flop (210) and the diode (228) may be connected to the data input of the D flip flop (210).
Output of the D flip flop (210) is a control signal that may detect phase sequence of the three phase three wire AC. According to an embodiment, the control signal output may be low or high. According to an exemplary embodiment, the control signal may be high if phases of the three phase AC input are in sequence and low if phases of the three phase AC input are not in sequence. According to another embodiment, the control signal may be directly proportional to the phase error in the desired phase relationship between the data pulses and the clock pulses.
According to an embodiment, the output of the D flip flop (210) may be fed as input to other circuits that require status of phase sequence to take further action.
Figure 3 shows pulse waveforms of a phase sequence detector when three phases of a three phase three wire AC power system are in phase, according to an exemplary embodiment of the invention.
LI, L2 and L3 may correspond to phase 1, phase2 and phase3 respectively of the three phase three wire system. The Data, Clock and Out correspond to data input, clock input and output of the D flip flop (210) of the phase sequence circuit shown in Figure 2. V+ represent the voltage supplied to the D flip flop (210). Figure 3 illustrates Out is high if LI, L2 and L3 are in phase. If LI, L2 and L3 are in phase, then data input of the D flip flop(210) is defined high during positive transition in clock input.
Out is high if lines LI, L2 and L3 are phased as below:
Figure 4 shows pulse waveforms of a phase sequence detector when three phases of a three phase three wire AC power system are out of phase, according to an exemplary embodiment of the invention. Figure 4 illustrates Out is low if LI, L2 and L3 are not in phase. If LI, L2 and L3 are not in phase, then data input of the D flip flop (210) is defined low during positive transition in clock input.
Out is low if lines LI, L2 and L3 are phased as below:
There are many advantages of the present invention over existing methods for phase sequence detection in a three phase three wire system. The present invention uses only a single flip flop for phase sequence detection. There is no software dependency to determine the phase sequence. The invention is a low cost and effective method for phase sequence detection.
In the drawings and specification there has been set forth preferred embodiments of the invention, and although specific terms are employed, these are used in a generic and descriptive sense only and not for purposes of limitation. Changes in the form and the proportion of parts, as well as in the substitution of equivalents, are contemplated as circumstances may suggest or render expedient without departing from the spirit or scope of the invention.
Throughout the various contexts described in this disclosure, the embodiments of the invention further encompass computer apparatus, computing systems and machine-readable media configured to carry out the foregoing systems and methods. In addition to an embodiment consisting of specifically designed integrated circuits or other electronics, the present invention may be conveniently implemented using a conventional general purpose or a specialized digital
computer or microprocessor programmed according to the teachings of the present disclosure, as will be apparent to those skilled in the computer art.
The embodiments of the present invention may be provided as a computer program product that may include a machine-readable medium, having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to the present invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, compact disc read-only memories (CD-ROMs), and magneto-optical disks, ROMs, random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. In addition to an embodiment consisting of specifically designed integrated circuits or other electronics, the present invention may be conveniently implemented using a conventional general purpose or a specialized digital computer or microprocessor programmed according to the teachings of the present disclosure, as will be apparent to those skilled in the computer art.
Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art. The invention may also be implemented by the preparation of application specific integrated circuits or by interconnecting an appropriate network of conventional component circuits, as will be readily apparent to those skilled in the art.
| # | Name | Date |
|---|---|---|
| 1 | 201941010609-IntimationOfGrant24-05-2024.pdf | 2024-05-24 |
| 1 | Form5_As Filed_19-03-2019.pdf | 2019-03-19 |
| 2 | 201941010609-PatentCertificate24-05-2024.pdf | 2024-05-24 |
| 2 | Form3_As Filed_19-03-2019.pdf | 2019-03-19 |
| 3 | Form2 Title Page_Provisional_19-03-2019.pdf | 2019-03-19 |
| 3 | 201941010609-Annexure [21-05-2024(online)].pdf | 2024-05-21 |
| 4 | Form1_As Filed_19-03-2019.pdf | 2019-03-19 |
| 4 | 201941010609-FORM 13 [21-05-2024(online)].pdf | 2024-05-21 |
| 5 | Drawing_As Filed_19-03-2019.pdf | 2019-03-19 |
| 5 | 201941010609-PETITION UNDER RULE 137 [21-05-2024(online)].pdf | 2024-05-21 |
| 6 | Description Provisional_As Filed_19-03-2019.pdf | 2019-03-19 |
| 6 | 201941010609-POA [21-05-2024(online)].pdf | 2024-05-21 |
| 7 | Correspondnce by Applicant_ As Filed_19-03-2019.pdf | 2019-03-19 |
| 7 | 201941010609-Written submissions and relevant documents [21-05-2024(online)].pdf | 2024-05-21 |
| 8 | Form 1_After Filing_21-06-2019.pdf | 2019-06-21 |
| 8 | 201941010609-Correspondence to notify the Controller [18-04-2024(online)].pdf | 2024-04-18 |
| 9 | 201941010609-US(14)-HearingNotice-(HearingDate-09-05-2024).pdf | 2024-04-17 |
| 9 | Correspondence by Applicant _Form 1_21-06-2019.pdf | 2019-06-21 |
| 10 | 201941010609-ABSTRACT [29-03-2023(online)].pdf | 2023-03-29 |
| 10 | 201941010609-Form2 Title Page Complete_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 11 | 201941010609-CLAIMS [29-03-2023(online)].pdf | 2023-03-29 |
| 11 | 201941010609-Form 1_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 12 | 201941010609-COMPLETE SPECIFICATION [29-03-2023(online)].pdf | 2023-03-29 |
| 12 | 201941010609-Drawings_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 13 | 201941010609-Description Complete_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 13 | 201941010609-FER_SER_REPLY [29-03-2023(online)].pdf | 2023-03-29 |
| 14 | 201941010609-Correspondence_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 14 | 201941010609-FORM-26 [29-03-2023(online)].pdf | 2023-03-29 |
| 15 | 201941010609-Claims_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 15 | 201941010609-OTHERS [29-03-2023(online)].pdf | 2023-03-29 |
| 16 | 201941010609-Abstract_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 16 | 201941010609-FER.pdf | 2022-10-07 |
| 17 | 201941010609-Correspondence_Form-18_22-06-2022.pdf | 2022-06-22 |
| 17 | 201941010609-Abstract_17-03-2020.jpg | 2020-03-17 |
| 18 | 201941010609-Correspondence_Amend the email addresses_14-12-2021.pdf | 2021-12-14 |
| 18 | 201941010609-Form18_Examination Request_22-06-2022.pdf | 2022-06-22 |
| 19 | 201941010609-Correspondence_Amend the email addresses_14-12-2021.pdf | 2021-12-14 |
| 19 | 201941010609-Form18_Examination Request_22-06-2022.pdf | 2022-06-22 |
| 20 | 201941010609-Abstract_17-03-2020.jpg | 2020-03-17 |
| 20 | 201941010609-Correspondence_Form-18_22-06-2022.pdf | 2022-06-22 |
| 21 | 201941010609-Abstract_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 21 | 201941010609-FER.pdf | 2022-10-07 |
| 22 | 201941010609-Claims_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 22 | 201941010609-OTHERS [29-03-2023(online)].pdf | 2023-03-29 |
| 23 | 201941010609-FORM-26 [29-03-2023(online)].pdf | 2023-03-29 |
| 23 | 201941010609-Correspondence_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 24 | 201941010609-Description Complete_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 24 | 201941010609-FER_SER_REPLY [29-03-2023(online)].pdf | 2023-03-29 |
| 25 | 201941010609-COMPLETE SPECIFICATION [29-03-2023(online)].pdf | 2023-03-29 |
| 25 | 201941010609-Drawings_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 26 | 201941010609-CLAIMS [29-03-2023(online)].pdf | 2023-03-29 |
| 26 | 201941010609-Form 1_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 27 | 201941010609-ABSTRACT [29-03-2023(online)].pdf | 2023-03-29 |
| 27 | 201941010609-Form2 Title Page Complete_After Provisional_17-03-2020.pdf | 2020-03-17 |
| 28 | 201941010609-US(14)-HearingNotice-(HearingDate-09-05-2024).pdf | 2024-04-17 |
| 28 | Correspondence by Applicant _Form 1_21-06-2019.pdf | 2019-06-21 |
| 29 | 201941010609-Correspondence to notify the Controller [18-04-2024(online)].pdf | 2024-04-18 |
| 29 | Form 1_After Filing_21-06-2019.pdf | 2019-06-21 |
| 30 | Correspondnce by Applicant_ As Filed_19-03-2019.pdf | 2019-03-19 |
| 30 | 201941010609-Written submissions and relevant documents [21-05-2024(online)].pdf | 2024-05-21 |
| 31 | Description Provisional_As Filed_19-03-2019.pdf | 2019-03-19 |
| 31 | 201941010609-POA [21-05-2024(online)].pdf | 2024-05-21 |
| 32 | Drawing_As Filed_19-03-2019.pdf | 2019-03-19 |
| 32 | 201941010609-PETITION UNDER RULE 137 [21-05-2024(online)].pdf | 2024-05-21 |
| 33 | Form1_As Filed_19-03-2019.pdf | 2019-03-19 |
| 33 | 201941010609-FORM 13 [21-05-2024(online)].pdf | 2024-05-21 |
| 34 | Form2 Title Page_Provisional_19-03-2019.pdf | 2019-03-19 |
| 34 | 201941010609-Annexure [21-05-2024(online)].pdf | 2024-05-21 |
| 35 | Form3_As Filed_19-03-2019.pdf | 2019-03-19 |
| 35 | 201941010609-PatentCertificate24-05-2024.pdf | 2024-05-24 |
| 36 | 201941010609-IntimationOfGrant24-05-2024.pdf | 2024-05-24 |
| 36 | Form5_As Filed_19-03-2019.pdf | 2019-03-19 |
| 1 | SearchHistory(29)E_07-10-2022.pdf |
| 2 | 201941010609AE_04-10-2023.pdf |