TOVOJ L - _L _ ®JET D OF MANUFACTURING THE SAME
ACKGROUND
1. Field of the Invention
[0001 ] One or more embodiments of the present invention relate to photovoltaic
devices and methods of manufacturing the same.
2. e cription
[0002] A solar cell is a photovoltaic device for converting light, such as sunlight, to
electric energy. Unlike other energy sources, solar energy is infinite and is an
environmentally friendly energy source, and thus is becoming more and more
important. The most basic structure of a solar cell is a diode formed of a PN junction
and is categorized according to materials constituting a light absorbing layer.
[0003] Solar cells having light absorbing layers formed of silicon may be
categorized into crystalline (for example, polycrystalline) wafer type solar cells and thinfilm
(amorphous, polycrystalline) type solar cells. The most popular examples of solar
cells include compound thin-film solar cells using CulnGa e2 (GIGS) or Odle, Group
Ill-V solar cells, dye-sensitized solar cells, and organic solar cells.
[0004] A hetero-junction solar cell, which is a crystalline solar cell, uses a crystalline
semiconductor substrate as a light absorbing layer, and a non-single crystal
semiconductor layer having crystallinity different from that of the semiconductor
substrate is formed on the crystalline semiconductor substrate to fabricate the hetero
junction solar cell.
[0005] A hetero-junction solar cell includes a positive electrode and a negative
electrode on a front sur I; I. a ^ ^ and a rear surface of a semiconductor substrate,
rL :.;1 ctively. In Such a structure, electrodes are arranged on a sr irlncn to which
sunlight is to be incident , thus interrupting incidence of sunlight.
[0000] Furthermore, a hetero-junction solar cell includes transparent conductive
layers on a front surface and a rear surface of a semiconductor substrate. Therefore,
there is a loss in a light transmitting ratio due to transparent conductive layers, and
thus efficiency of light incidence decreases . Furthermore, resistance of a transparent
conductive layer is greater than that of the electrodes , thus increasing overall
resistance of a solar cell.
SUMMARY
[0007] Additional aspects will be set forth in part in the description which follows
and, in part , will be apparent from the description.
X0008] According to one or more embodiments of the present invention, a
photovoltaic device includes a crystalline semiconductor layer; an amorphous first
conductive type semiconductor layer that is formed in a first region of a rear surface of
the semiconductor substrate and contains a first impurity ; an amorphous second
conductive type semiconductor layer that is formed in a second region of the rear
surface of the semiconductor substrate and contains second impurity; and a gap
passivation layer that is disposed between the first region and the second region on
the semiconductor substrate, wherein the first conductive type semiconductor layer is
disposed on the gap passivation layer.
E0001 the first conductive type semiconductor layer may completely cover the
passivation layer.
X0010] At least one of surfaces of the semiconductor substrate may be textured.
[0011] The photovoltaic device may further include a first amorphous silicon (ap
i)
layer interposed between the semiconductor substrate and the first conductive type
semiconductor layer; a first transparent conductive layer formed on the first conductive
type semiconductor layer; and a first metal electrode formed on the first transparent
conductive layer.
[001 2] A thickness of the gap passivation layer may be greater than a sum of
thicknesses of the first a-Si layer, the first conductive type semiconductor layer, and the
first transparent conductive layer.
[0013] The first a-Si layer, the first conductive type semiconductor layer, and the
first transparent conductive layer may completely cover the gap passivation layer.
[0014] The photovoltaic device may further include a second amorphous silicon (a-
Si) layer interposed between the semiconductor substrate and the second conductive
type semiconductor layer; a second transparent conductive layer formed on the second
conductive type semiconductor layer; and a second metal electrode fort-lied on the
second transparent conductive layer.
[0015] A thickness of the gap passivation layer may be greater than a sum of
thicknesses of the second a-Si layer, the second conductive type semiconductor layer,
and the second transparent conductive layer.
[0016] The photovoltaic device may further include a front surface protective layer
formed on a front surface of the semiconductor substrate; a front surface field layer
formed on the front surface of the semiconductor substrate ; and an anti-reflection layer
formed on the front surface protective layer and the front surface field layer.
[0017] The gap p, is ;iv: 4ion layer may include a double layer includih ^ : a SiOX layer
and a SiN,, layer or a double layer including a SO,, layer and a SiON layer.
[001 8] At least one of the first a-Si layer and the second a-Si layer may be formed
to have a thickness from about 20A to about 100A.
[0019] At least one of the first transparent conductive layer and the second
transparent conductive layer may be formed to have a thickn, from about 200A to
about 1000A.
[0020] At l(„one of the first conductive type semiconductor layer and the second
conductive type, semiconductor layer may be formed to have a thickness from about 30
A to about 100 A.
(00211 The first conductive type semiconductor layer may be p-type, and the second
conductive type semiconductor layer may be retype.
(00221 The first conductive type semiconductor layer may be retype, and the second
conductive type semiconductor layer may be p-type.
[®®] The first region and the second region may be apart from each other by
interposing the gap passivation layer therebetween and may be interspersed with each
other.
[®®] According to one or more embodiments of the present invention, a method of
manufacturing a photovoltaic device, the method includes a first patterning operation
for opening a first region in a passivation layer formed on a rear surface of a
semiconductor substrate; forming a first a-Si layer, a first conductive type
semiconductor layer, and a first transparent conductive layer in the order stated on the
rear surface of the semiconductor substrate including the passivation layer in which the
first region is opened; forming an etch resist to cover the first region and portions of the
passivation layer around the first region; a second patterning operation for opening a
second region in the passivation layer by etching the passivation layer, the first a, Si
layer, the first conductive type semiconductor layer, and the second transparent
conductive layer which are not protected by the etch resist; forming i : ^ )nd a-Si
layer, a second conductive type semiconductor layer, and a second transparent
conductive layer in the order stated on the rear surface of the semiconductor substrate
including the passivation layer in which the second region is opened; and removing the
etch resist.
(0 ^ The passivation layer may include a double layer including a Si®, layer and
a SiN,, layer or a double layer including a Siff,, layer and a SiON layer.
The first region and the second region may be apart from each other and
m y ^e alternately arranged.
I e J The method may further include texturing the semiconductor sub&r:
LION OF THE F !
[ 0Ao] These and/or other aspects will become apparent and more readily
appreciated from the following description of the embodiments, taken in conjunction
with the accompanying drawings of which:
[0029] FIG. 1 is a schematic sectional view of a photovoltaic device according to an
embodiment of the present invention;
[0030] FIGS. 2 thiuugh 10 are schematic sectional views showing steps of an
exemplary method of manufacturing the photovoltaic device of FIG. 1; and
[00311 FIG. 11 is a schematic sectional view of a photovoltaic device according to
another embodiment of the pr .nt invention.
DETAILED o l d C
[0032] The present invention will now be described more fully with reference to the
accompanying drawings, in which exemplary embodiments of the invention are shown.
The invention may, however , be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein; rather, these
embodiments are provided so that this disclosure will be thorough and, ^niplete. The
terms used in the present specification are merely used to describe particular,
embodiments , and are not intended to limit the present invention. An expression used
in the singular encompasses the expression of the plural , unless it has a clearly
different meaning in the context . In the present specification, it is to be understood that
the terms such as "including" or "having," etc., are intended to indicate the existence of
the features , numbers, steps, actions , components, parts, or combinations thereof
disclosed in the specification, and are not intended to preclude the possibility that one
or more other features , numbers , steps, actions, components , parts , or combinations
thereof may exist or may be added. V./hit tlch terms as "first," "second," etc., may be
used to describe various components, such components must not be limited to the
above terms. The above terms are used only to distinguish one component from
another.
[00331 It will also be understood that when a layer is referred to as being "on"
another layer or substrate , it can be directly on the other layer or substrate, or
intervening layers may also be present. However, when a layer is referred to as being
"directly on" another layer or substrate , no intervening layers may be present.
[0034] FIG. 1 is a schematic sectional view of a photovoltaic device according to an
embodiment of the present invention.
[0035] The photovoltaic device includes a semiconductor substrate 110 , and a front
surface protective layer 130, a front surface field layer 140, and an anti=reflection layer
150 that are formed on a front surface of the semiconductor substrate 110, and first
and second amorphous silicon (a- Si) layers 161 and 171, first and second conductive
type semiconductor layers 162 and 172, first and second transparent conductive layers
163 and 173, first and second metal electrodes 180 and 190, and a gap passivation
layer 120 that are formed on a rear surface of the semiconductor substrate 110.
[0036] The semiconductor substrate 110 is a light absorbing layer and may include
a crystalline silicon substrate . For example, the semiconductor substr ; a; , 110 may
include a single crystal silicon substrate or a polycrystalline silicon substrate. The
semicond-actor substrate 110 may be a single crystal silicon substrate or a
polycrystalline silicon substrate containing an natype impurity. The n-type impurity may
include group V chemical elements, such as phosphor (P) and arsenic (As).
[0037] Although a single crystal silicon substrate or a polycrystalline silicon
substrate containing an n-type impurity is used as the semiconductor substrate 110 in
the embodiment , the pr c,. ;c ,nt invention is not limited thereto. For example, a
single crystal Silicon substr,;ic it a polycrystalline silicon substrate containing a p-type
impurity may also be employed. The p-type impurity may include group III chemical
elements, such as boron (B), aluminum (AI), and gallium (Ga).
[0038] The front surface protective layer 130 is formed on the front surface of the
semiconductor substrate 1 10 to protect the semiconductor substrate 110 and may
contain intrinsic a-Si (i a-Si). Alternatively, the front surface protective layer 130 may
contain a-Si containing an n-type impurity (n a-Si) or the front surface protective layer
130 may be formed of an inorganic material containing combinations of Si, N, 0, and
1-I, e.g., silicon oxide (SiOx) or silicon nitride (SiNx).
I 039] The front surface field layer 140 may be formed on the front surface
protective layer 130 and may contain a-Si dopeet with an impurity or SiNx. If the front
surface field layer 140 contains a-Si doped with an impurity, the a-Si may be doped
with the same conductive impurity as the semiconductor substrate 110 at a higher
concentration than in the semiconductor substrate 110. Therefore, as a potential
barrier is formed due to a difference between impurity concentrations of the
semiconductor substrate 110 and the front surface field layer 140, movement of holes
to the front surface of the semiconductor substrate 11'0 is interLi ' with, and thus
holes and electrons may be prevented from being recombined with each other nearby
the front surface oithe , ^rniconductor substrate 110.
[0040] The anti-reflection layer 150 prevents loss of light absorption of the
photovoltic device due to reflection of Ii during incidence of sunlight, thus improving
efficiency of the photovoltaic device. The anti-reflection layer 150 may contain a
transparent material. For example, the anti-reflection layer 150 may contain Si x,
SiNx, silicon oxynitride (SiOxNy), etc. Alternatively, the anti-reflection layer 150 may
contain titanium oxide (TiOx), zinc oxide (ZnO), zinc sulfide (ZnS), etc. The antireflection
layer 150 may be formed to include a single layer or a plurality of layers.
[0041] Although a case in which the front surface protective layer 130, the front
surface field layer 140, and d v, ; r iti-reflection layer 150 are individually formed on the
front surface of the semiconductor substrate 110 is described in the present
embodiment, the present invention is not limited thereto. For example, after the front
surface protective layer 130 containing SiOx is formed, a film containing S1NX may be
formed to function as both the front surface field layer 140 and the anti-reflection layer
150. Alternatively, after the front surface protecting layer 130 containing i a-Si or a- Si
doped with an impurity is formed, a film containing SINX may be formed to function as
both the front surface field layer 140 and the anti-reflection layer 150.
[0042) The first i; y r 161, the first conductive type semiconductor layer 162,
the first transparent conductive layer 163, and the first metal electrode 180 may be
formed in a first region Al of the rear surface of the semiconductor substrate 110. The
first a-Si layer 161 may be formed in the first region Al of the rear surface of the
semiconductor substrate l 10 and may contain i a-Si. The first conductive type
semiconductor layer 162 may be formed on the first a- Si layer 161 and may contain a
first impurity. For example, the first conductive type semiconductor layer 162 may be
formed as a p± layer by using a pmtype impurity. The first transparent conductive layer..
163 may be formed on the first conductive type semiconductor layer 162 and includes
a transparent conductive film (TCO), such as I TO, IZO, and ZnO. The first metal
electrode 180 formed on the first transparent conductive layer 163 may contain silver
(Ag), gold (Au), copper (Cu), Al, or an alloy thereof.
[0 The first conductive type semiconductor layer 162 formed of a- Si containing
a p-type impurity forms a p-n junction with the semiconductor substrate 110. In this
case, to improve,the p-n junction property, the first a-i layer 161 is located between
the semiconductor substrate 110 and the first conductive tyh( ^ , ^( ^miconductor layer
162. The first conductive type semiconductor layer 162 and thu first a=Si layer 161
forms a hetero-junction with the semiconductor substrate 110, and thus an open circuit
voltage of the photovoltaic device may increase. The first conductive type
semiconductor layer 162 may be formed to have a thickness of between about 30A to
about 100A, whereas the first a-i layer 161 may be formed to have a thickness of
between about 20A to about 100A.
[0044] The first transparent conductive layer 163 may improve ohmic contact
between the first conductive type semiconductor layer 162 and the first metal electrode
180. The first transparent conductive layer 163 may be formed to have a thickness
from about 200A to about 1000A. The first metal electrode 180 may be connected to
an external device. According to the present embodiment, the first metal electrode 180
may be electrically cor ineacted to an external device as a positive electrode of the
photovoltaic device.
[0045] The second a-Si layer 171, the second conductiv ° type semiconductor layer
172, the second transparent conductive layer 173, and the icond metal electrode 190
may be formed in a second region A2 of the rear surface of the semiconductor
substrate 110.
[0046] The second a-Si layer 171 is formed in the second region A2 of the rear
surface of the semiconductor substrate 110 and may include i a-Si. The second
conductive type semiconductor layer 172 is formed on the secon=! ;i IE,h.yer 171, and
may include a second impurity. For example , the second conductive type
semiconductor layer 172 may be formed as an n+ layer by using an wi,(, impurity.
The second transparent conductive layer 173 includes a transparent conductive film
(TCO), such as [TO, IZO, and ZnO, and the second metal electrode 190 formed on the
second transparent conductive layer 173 may contain AG, An, Cu, Al, or an alloy
thereof.
[0047] The second conductive type semiconductor layer 172 containing a-Si
containing an n-type impurity may have a higher impurity concentration than in the
semiconductor substrate 110. The second conductive type semiconductor layer 172
may be formed to have a thickness from about 30A to about 100A and may form a rear
electric field together with the second a---Si layer 171 to prevent holes and electrons
10-
from being recombined with each other nearby the front surface of the semiconductor
substrate 110. The second a-i layer 171 may be formed to have a thickness from
about 20A to about 100A.
X04 The second transparent conductive layer 173 is formed to have a thickness
from about 200A to about 1000A and may enhance ohmic contact between the second
conductive type semiconductor layer 172 and the second metal electrode 190. The
second metal electrode 190 may be connected to an external device. According to the
present embod iment, th second metal electrode 190 may be electrically connected to
an external device as a negative electrode of the photovoltaic device.
[0049] A gap passivation layer 120 is arranged in a third region A3 of the rear
surface of the semiconductor substrate 110, and the first a=Si layer 161, the first
conductive type semiconductor layer 162, and the first transparent conductive layer
163 are stacked on the gap passivation layer 120 in the order stated. The gap
passivation layer 120 prevents the semiconductor substrate 110 from being exposed to
outside elements, so that holes and electrons may be prevented from being
recombined with each other.
[0050] The thickness of the gap passivation layer 120 may be greater than a sum of
thicknesses of layers arranged around the gap passivation layer 120. l-t)r example, the
thicknen: ; of the gap passivation layer 120 may be greater than a sum of the
thickn(,, : of the first a-Si layer 161, the first conductive type semiconductor layer
162, and the first transparent conductive layer 163 and greater than a sum of the
thicknesses of the second a=Si layer 171, the second conductive type semiconductor
layer 172, and the second transparent conductive layer 173. The thickness of the gap
passivation layer 120 may be from about 1000A to about 1500A.
[00,51] If the thickness of the gap passivation layer 120 is smaller than a sum of the
thicknc.n.nnn. of layers arranged around the gap passivation layer 120, efficiency of the
-11-
gap passivation layer 120 may be deteriorated . For example, electrons and holes may
not be effectively prevented from being recombined with each other.
x0052] The gap passivation layer 120 is formed directly on the semiconductor
substrate 110 and prevents the semiconductor substrate 110 from being exposed to
outside elements . The gap passivation layer 120 may be formed as a double layer
including a SiOx layer and a SiNX layer or a double layer including a SiOx layer and a
Si®XNy layer. Alternatively, the gap passivation layer 120 may be formed as a single
layer.
[0053] The gap passivation layer 120 is formed by forming a passivation layer in
which the first region Al is opened before the first a=Si layer 161 is formed and then
opening the second region A2 of the passivation layer before the second a-Si layer 171
is formed. According to such method, the width of the gap passivation layer 120 may
be minimized , and possible dnr ; i 4 ^s that occur during formation of the first conductive
type semiconductor layer 162 and the second conductive type semiconductor layer 172
may be minimized. The width of the gap passivation layer 120 may be smaller than or
equal to 100pm, e.g., the width of the gap passivation layer 120 may be from about
30pm to about 50pm. If the gap passivation layer 120 is formed to have an excessive
width, efficiency of the photovoltaic device may be significantly det Ui''l ; 'd.
00054] The first a-Si layer 161, the first conductive type semiconductor layer 162,
and the first transparent conductive layer 163 are formed on the gap passivation layer
120 in the order stated according to a method of manufacturing a photovoltaic device
as described above.
[0055] Hereinafter-, a method of manufacturing a photovoltaic device according to
an embodiment of the present invention will be described with reference to FIGS. 2 and
10.
[a0 1 Referring to FIG . 2, a passivation layer 120a is formed on the semiconductor
substrate 110 containing crystalline silicon . The passivation layer 120a may be formed
to have a thickness from about 1000A to about 1500A.
Q0057] The passivation layer 120a may be formed of a plurality of layers. For
example , the passivation layer 120a may be formed by forming a film containing SiOX
and forming a film containing SiNX. Alternatively, the passivation layer 120a may be
formed by forming a film containing SiOX and forming a film containing SiOXNY.
Alternatively, the passivation layer 120a may be formed of a single layer, if required.
x0058] Referring to FIG. 3, a patterning operation is formed to remove a portion of
the passivation layer 120a formed on the semiconductor substrate 110, that is, the first
region Al. The patterning operation may be an etching operation. For example, the
first region Al may be p^ atterned via we- t-ecthing. Here, only ' the first region Al is
removed from the passivation layer 120a formed on the rear surface of the
semiconductor substrate l 10, and a portion of the semiconductor substrate 110
corresponding to the first region Al may be exposed by the patterning operation. The
first region Al is a region in which the first a®i layer 161, the first conductive type
semiconductor layer 162, and the first transparent conductive layer 163 are formed in
operations described below. In one embodiment, the passivation layer i 20a formed on
the front and side surfaces of the semiconductor substrate 110 may be completely
removed.
x0059 Referring to FIG. 4, the front surface protective layer 130, the front surface
field layer 140, and the anti-reflection layer 150 are formed on the front surface of the
semiconductor substrate 110 in the order stated.
^O0 0] The front surface protective layer 130 may contain i a- Si, a-Si containing an
impurity, or an inorganic material, such as SiOx and SiNx, and is formed to completely
cover the front surface of the semiconductor substrate 110. The front surface
protective layer 130 may be formed via a chemical vapor deposition method, such as
-13-
plasma chemical vapor deposition (PECVD), a physical method, such as Sputtering or
spin coating , a chemical method, or a physical-chemical method.
[0061] The front surface field layer 140 may include a-Si doped with an impurity or
SiNX and is formed to completely cover the front surface protective layer 130. The front
surface field layer 140 may be formed via PECVD, where the a- Si doped with an
impurity may have a higher impurity concentration than the semiconductor substrate
110.
[0062] The anti-roiicction layer 150 may contain SiO, SiN,, SiOXNY, etc.
Alternatively, the anti-reflection layer 150 may contain Ti02, ZnO, ZnS, etc. The antireflection
layer 150 may be formed via a method such as CVD, sputtering, or spin
coating.
[00631 Although a case where the front surface protective layer 130, the front
surface field layer 140, and the anti-reflection layer 150 are individually formed is
described in the present embodiment, the present invention is not limited thereto. For
example, after the front surface protective layer 130 containing Si x is formed, a film
that contains SiNx and may function as both the front surface field layer 140 and the
anti-reflection layer 150 simultaneously may be formed, as described above.
[nO Referring to [FIG. 5, the first a- Si layer 161, the first conductive type
semiconductor layer 162, and the first transparent conductive layer 163 are formed in
the order tated on the rear surface of the semiconductor substrate 110 having the
passivation layer 120a in which the first region Al is opened.
[0065] The first a- Si layer 161 may contain i a- i. For example, the first a- Si layer
161 having a thickness from about 20A to about 100A may be formed via n n n r Jhod
such as PECVD. For example, the first conductive type semiconductor layer 162 may
be formed by injecting SiH/[, hydrogen (H), etc. into a vacuum chamber, injecting an
impurity containing a group III chemical element, and performing a chemical vapor
deposition method, stinh ; a- , V 'ECVD. The first transparent conductive layer 163 may
-14-
contain ITO, IZO, IWO, lGdO, IZrO, INdO, ZnO, etc. and may be formed via a method
such as sputtering, e-beam, evaporation, etc.
[0066] Since the first a- Si layer 161, the first conductive type semiconductor layer
162, and the first transparent conductive layer 163 are formed to completely cover the
rear surface of the semiconductor substrate 110 having the passivation layer 120a in
which the first region Al is opened, the first a-Si layer 161, the first conductive type
semiconductor layer 162, and the first transparent conductive layer 163 are formed not
only on the semiconductor substrate 110, but also on the passivation layer 120a.
[0067] Referring to FIG. 6, an etch resist 210 is formed. Here, the etch resist 210 is
formed to cover the first region Al and a portion of the passivation layer 120a formed
around the first region Al. The portion of the passivation layer 120a covered by the
etch resist 210 becomes the gap passivation layer 120 as shown in FIG. 10.
[0 ^ Referring to FIG. 7, the second region A2 of the passivation layer 120a is
opened by etching the passivation layer 120a, the first a=Si layer 161, the first
conductive type semiconductor layer 162, and the first transparent conductive layer
163, which are formed on the rear surface of the semiconductor substrate 110, by
using the etch resist 210 as a mask.
[0069] The passivation layer 120a, the first a- Si layer 161, the first conductive type
semiconductor layer 162, and the first transparent conductive layer 163 may be etched
via wet etching or dry=etching in regions not covered by the etch resist 210. In one
embodiment, the passivation layer 120a, the first a -Si layer 161, the first conductive
type semiconductor layer 162, and the first transparent conductive layer 163 in the
region covered by the etch resist 210 are protected during the etching operation.
[0070] A portion of the semiconductor substrate 110 corresponding to the second
region A2 is exposed through a second patterning operation as described above. The
second region A2 is a region in which the second a-Si layer 171, the second
1
conductive type semiconductor layer 172, and the second transparent conductive layer
173 are formed in operations described below.
[0071] Referring to FIG. 8, the second a-Si layer 171, the second conductive type
semiconductor layer 172, and the second transparent conductive layer 173 are formed
in the order stated on the rear surface of the semiconductor substrate 110 in which a
portion corresponding to the second region is opened.
[0072] The second a- Si layer 171 may contain i a-Si. For example, the second a-Si
layer 171 having a ti iicknooss from about 20A to about 100A may be formed via a
method such as PECVD. For example, the second conductive type semiconductor
layer 172 may be formed by injecting SiH4, hydrogen (H), etc. into a vacuum chamber,
injecting an impurity containing a group V chemical element, and performing a
chemical vapor deposition method, such as PEGVD. The second transparent
conductive layer 173 contains ITO, IZO, IWO, IGdO, lZrO, INdO, ZnO, etc. and may be
formed via a method such as sputtering, e-beam, evaporation, etc.
[0073] Since the second a- Si layer 171, the second conductive type semiconductor
layer 172, and the second transparent conductive layer 173 are iu, r iA to completely
cover the rear surface of the semiconductor substrate 110 having the passivation layer
120a in which the second region A2 is opened, the second a-Si layer 1./ I, the second
conductive type semiconductor layer 172, and the second transparent conductive layer
173 are formed not only on the semiconductor substrate 110, but also on the etch
resist 210. However, since the passivation layer 120a is covered by the etch resist
210, the second a-i layer 171, the second conductive type semiconductor layer 172,
and the second transl^, ii, ,iii conductive layer 173 are not formed directly on the
passivation layer 120a.
[0074] Referring to FIG. 9, the etch resist 210 is removed. When the etch resist 210
is removed, the second a-i layer 171, the second conductive type semiconductor
layer 172, and the second transparent conductive layer 173 formed on the ^ +;h resist
-16-
210 are also removed. As the etch resist 210 is removed, a stacked structure covered
by the etch resist 210 and including the first a- Si layer 161, the first conductive type
semiconductor layer 162, and the first transparent conductive layer 163 is exposed.
[0075] The first a-Si layer 161, the first conductive type semiconductor layer 162,
and the first transparent conductive layer 163 are arranged not only on the first region
Al, but also on the gap passivation layer 120.
[0076] According to such process, the first a ®Si layer 161, the first conductive type
semiconductor layer i U2, and the first transparent conductive layer 163 are formed in
the first region Al, whereas the second a®Si layer 171, the second conductive type
semiconductor layer 172, and the second transparent conductive layer 173 are formed
in the second region A2. Furthermore, the gap passivation layer 120 is formed
between the first region Al and the second region A2.
[0077] Referring to FIG. 10, the first metal electrode 180 and the second metal
electrode 190 are formed. The first metal electrode 180 is formed on the first
transparent conductive layer 163, whereas the second metal electrode 190 is formed
on the second transparent conductive layer 173. The first and second metal electrodes
180 and 190 may contain Ag, Au, Cu, Al, or an alloy thereof . For example , first and
second metal electrode '180 and 190 may be formed by using a cony lr± ;iv{ , paste
containing the above-stated element(s) via a coating method such as inkjet printing,
gravure printing, offset printing, screen printing, etc.
[0078] In a method of manufacturing a photovoltaic device according to a
comparative embodiment, the method may include two operations. In first operation, a
first a-i layer, a first conductive type semiconductor layer, and a first transparent
conductive layer are formed to completely cover a surface in which a passivation layer
is formed with a first and second regions are opened, and then the first a- Si layer, the
first conductive type semiconductor layer, and the first transparent conductive layer are
partially removed by etching such that the first a---Si layer, the first conductive type
--17e
semiconductor layer, and the first transparent conductive layer, which correspond to
the first region, remain. In second operation, a second a-Si layer, a second conductive
type semiconductor layer, and a second transparent conductive layer are formed to
completely cover the surface in which the passivation layer is formed, and then the
second a®Si layer, the second conductive type semiconductor layer, and the second
transparent conductive layer are partially removed by etching such that the second a-Si
layer, the second conductive type semiconductor layer, and the second transparent
conductive layer, whiei i correspond to the second region, remain.
L0D79 During the etching according to the comparative embodiment, since etching
selectivity of the first conductive semiconductor layer, which is a p+ layer, and etching
selectivity of the second conductive type semiconductor layer, which is an n+ layer,
with respect to each other is relatively low, damages to a rear surface of a photovoltaic
device may be induced. Furthermore, if the width of a gap passivation layer between
the first region and the second region is similar to that of the gap passivation layer 120
according to an embodiment of the present invention, it is difficult to calibrate alignment
during a printing operation, and thus quality of the photovoltaic device is deteriorated.
[0080] However, the method of manufacturing a photovoltaic device according to an
embodiment of the pry 1-i it invention includes relatively simple operation. And, since a
first conductive type semiconductor layer is formed after the first region Al is opened
and a second conductive type semiconductor layer is formed after the second region
A2 is opened, it is easy to calibrate alignment during a printing operation, and thus a
high quality photovoltaic device may be manufactured.
[001] FIG. 11 is a schematic sectional view of a photovoltaic device according to
another embodiment of the present invention.
[0 Referring to FIG. 11, the photovoltaic device according to the present
embodiment includes a semiconductor substrate 310, a front surface protective layer
330, a front surface field layer 340, and an anti-reflection layer 350 that are formed on
- 18-
a front surface of the semiconductor substrate 310, and first and second a-i layers
361 and 371, first and second conductive type semiconductor layers 362 and 372, first
and second transparent conductive layers 363 and 373 , first and second metal
electrodes 380 and 390, and a gap passivation layer 320 that are formed on a rear
surface of the semiconductor substrate 310.
[0083) In one embodiment , the photovoltaic device according to the present
embodiment is substantially similar to the photovoltaic device according to the previous
embodiment except ti iL-a the front surface of the semiconductor substrate 310 is
textured. Descriptions of configurations of the photovoltaic device according to the
present embodiment that are identical to the those of the photovoltaic device according
to the previous embodiment shown in FIG. I will be or-pitted, and descriptions below
will focus on differences between the previous embodiment and the present
embodiment.
[0084 The front surface of the semiconductor substrate 310, which is a light
absorbing layer , may be textured . A number of light paths for incident light may be
increased by texturing the front surface of the semiconductor : ;ul air, 310, and thus
light absorbing efficiency may be improved . As an example of a k xlurinq operation,
the semiconductor suba ra ite may be dipped into a mixture of a KOH or ` " afH solution
and isopropyl alcohol (IF="A). As a result,` pyi imidmtype texture may be formed.
[0085] Since the front surface of the semiconductor substrate 310 is textured, the
front surface protective layer 330, the front surface field layer 340, and the antireflection
layer 350 formed on the front surface of the semiconductor substrate 310
also include uneven sure. ^, in correspondence to the shape of the texture.
[0086] The method of m-, iufacturing a photovoltaic device according to the present
embodiment is identical to the method described above with reference to FIGS. 2
through 10, except that the semiconductor substrate 310 of which the front surface is
textured is employed in the pry,, ,nt embodiment.
-19-
Although the front surface of the semiconductor substrate 310 is textured in
a photovoltaic device according to the present embodiment, the present invention is
not limited thereto. For example, the rear surface of the semiconductor substrate 310
may also be textured. In this case, the first and second a®i layers 361 and 371, the
first and second conductive type semiconductor layers 362 and 372, and the first and
second transparent conductive layers 363 and 373 formed on the rear surface of the
semiconductor substrate 310 may or may not include uneven surfaces in
correspondence to the : ihcpe of the texture.
[0088] According to the embodiments as described above, after the first a-Si layers
161 and 361, the first conductive type semiconductor layer 162 and 362 which is p°type
semiconductor layer, and the first transparent conductive layer 163 and 363 are
formed, the second a-Si layers 171 and 371, the second conductive type
semiconductor layer 172 and 372 which is n-type semiconductor layer, and the second
transparent conductive layer 173 and 373 are formed. However, the present invention
is not limited thereto.
[0089] For example, after the second a-Si layers 1,71 and 371, the second
conductive type semiconductor layer 172 and 372 which is n-type semiconductor layer,
and the second transparent conductive layer 173 and 373 are formed, the first a-Si
layers 161 and 361, the first conductive type semiconductor layer 162 and 362 which is
p-type semiconductor layer, and the first transparent conductive layer 163 and 363
may be formed. In this case, a semiconductor layer formed to completely cover the
gap passivation layers 120 and 320 is the second conductive type semiconductor layer
172 and 372 which is an n-type semiconductor layer.
[0090] It should be understood that the exemplary embodiments described therein
should be considered in dc ^:;(,,riptive sense only and not for purpo^of limitation.
Descriptions of features or a .;pects within each embodiment should typically be
considered as available for other similar features or aspects in )ii r ^r ; ,mbodiments.

Claims:
1. A photovoltaic device comprising:
a semiconductor substrate;
an amorphous first conductive semiconductor layer on a first region of a first
surface of the semiconductor substrate and containing a first impurity;
an amorphous second conductive semiconductor layer on a second region of
the first surface of thu .-;(.,miconductor substrate and containing a second impurity; and
a gap passivation layer located between the first region and the second region
on the semiconductor substrate,
wherein the first conductive semiconductor layer is also on the gap passivation
layer.
2. The photovoltaic device as claimed in claim 1, wherein the fir
conductive semiconductor layer completely covers the gap passivation layer.
3. The photovoltaic device as claimed in claim 1, wherein at least one of
surfaces of the semiconductor substrate is textured.
4. ¢, The photovoltaic device as claimed in claim 1, further comprising:
a first amorphous silicon layer located between the semiconductor substrate and
the first conductive semiconductor layer;
a first transparent conductive layer on the first conductive semiconductor layer;
and
a first m(,i; kI c1ectrode on the first transparent conductive layer.
-,2 1 -,
5. The photovoltaic device as claimed in claim 4, wherein a thickness of the
gap passivation layer is greater than a sum of thicknesses of the first amorphous
silicon layer, the first conductive semiconductor layer, and the first transparent
conductive layer.
6. The photovoltaic device as claimed in claim 4, wherein the first
amorphous silicon layer, the first conductive semiconductor layer, and the first
transparent conductivu I;.iyer completely cover the gap passivation layer.
7. The photovoltaic device as claimed in claim 4, further comprising:
a second amorphous silicon layer located between the semiconductor substrate
and the second conductive semiconductor layer;
a second transparent conductive layer on the second conductive semiconductor
layer; and
a second metal electrode on the second transparent conductive layer.
8. The photovoltaic device as claimed in claim 7, wherein a thickness of the
gap passivation layer is greater than a sum of thicknesses of thc^ nd amorphous
silicon layer, the second conductive semiconductor layer, and the second transparent
conductive layer.
9. The photovoltaic device as claimed in claim 1, further comprising:
a second surface protective layer on a second surface of the semiconductor
substrate generally opposite to the first surface;
:;{ :land surface field layer formed on the second surface of the semiconductor
substrate; land
__22_-,
an anti=reflection layer formed on the second surface protective layer and the
second surface field layer.
10. The photovoltaic device as claimed in claim 1, wherein the gap
passivation layer comprises a double layer including a Sid,, layer and a SiN,, layer or a
double layer including a SiO,, Dyer and a SiON layer.
11. The photovoltaic device as claimed in claim 7, wherein at least one of the
first amorphous silicon layer and the second amorphous silicon layer h, a^ 1 thickness of
between about 20A to about 100A.
12. The photovoltaic device as claimed in claim 7, wherein at least one of the
first transparent conductive layer and the second transparent conductive layer has a
thickness between about 200A to about 1000A.
13. The photovoltaic device as claimed in claim 1, wherein at a_ine of the
first conductive semiconductor layer and the second conductive semiconductor layer
has a thickness betty(,, ,n : ;bout 30A to about 100A.
14.- The photovoltaic device as claimed in claim 1, wherein the first
conductive semiconductor layer is a p-type and the second conductive semiconductor
layer is an n-type.
15. The photovoltaic device as claimed in claim 1, wherein the first
conductive semiconductor layer is an n-type and the second conductive semiconductor
layer is a p-type.
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16. The photovoltaic device as claimed in claim 1, wherein the first region
and the second region are spaced from each other by the gap passivation layer
therebetween and are interspersed with each other.
17. A method of manufacturing a photovoltaic device, the method comprising:
performing a first patterning operation opening a first region in a passivation
layer formed on a first surface of a semiconductor substrate;
stacking a first uniorphous silicon layer, a first conductive semiconductor layer,
and a first transparent conductive layer in the order stated on the first surface of the
semiconductor substrate including the passivation layer in which the first region is
opened;
forming an etch resist to cover the first region and portions of the passivation
layer around the first region;
performing a second patterning operation opening a second region in the
passivation layer by etching the passivation layer, the first amorphous silicon layer, the
first conductive semiconductor layer, and the first transparent conductive layer which
are not protected by the etch resist;
stacking a second amorphous silicon layer, a second conductive ,miconductor
layer, and a second transparent conductive layer in the order stated on the first surface
of the semiconductor substrate including the passivation layer in which the second
region is opened; and
removing the etch resist.
18. The method as claimed in claim 17, wherein the passivation layer
comprises a double layer including a SiO, layer and a SiN,, layer or a double layer
including a aiO,< layer and a SiON layer.
19. The method as claimed in claim 17, wherein the first region and the
second region are spaced from each other and are alternately arranged.
20. The method as claimed in claim 17, further comprising texturing the
semiconductor substrate.