FIELD OF INVENTION
[0002] The invention disclosed herein relates, in general, to a photovoltaic device.
More specifically, the present invention relates to a method of manufacturing a
photovoltaic device.
BACKGROUND
[0003] A photoactive device makes use of the photovoltaic effect to convert solar
energy into electrical energy. There are certain photosensitive materials, for example,
doped semiconductor materials like silicon, that generate charge carriers, i.e., electrons
(e-) and holes (h+) upon absorbing solar radiation. When these carriers recombine
external to the cell usually after connecting to an external circuit they produce an
electric current.
[0004] These semiconductor materials are doped with impurities to form 'p type' or
'n type' extrinsic semiconductors. A junction formed between 'p type' or 'n type' extrinsic
semiconductors placed back to back, results in a strong electric field due to realignment
of positive and negative electric charges on either side of the junction. This causes an
inbuilt electric field across a p-n junction which sweeps the photo-generated charge
carriers across it. Electrically conducting layers provided on either side of these
photosensitive layers collect the charge carriers and utilize them in external electric
circuits in the form of current. This is usually the operating principle of a p-n junction
solar cell.
[0005] Typically, the layer of n type doped semiconductor material forms the top
surface that receives the solar radiation. The layer of n type doped semiconductor
material is formed by diffusing Phosphorous on one surface, i.e., the top surface, of a
substrate of p type-doped semiconductor material.
[0006] A 'shunt' is a local short circuit in the photovoltaic device, where the charge
carriers find a way to recombine across the p-n junction. Shunted devices are a
common problem in such processes of making photovoltaic devices, which thereby
reduce the average production yield and average production efficiency of such devices.
Shunts are commonly observed around the edge of the photovoltaic devices where the
3
n type doping agent species cause a local short circuit path to the p type substrate
forming a low resistance path between the front electrically conducting layer and the
rear electrically conducting layer.
[0007] To prevent shunts, various edge isolation techniques, including, for example
plasma edge isolation, laser edge isolation and wet chemical etching, are used to create
a groove in the n type doped semiconductor layer forming the top surface. The groove
interrupts the potential shunt path around the edge of the cell.
[0008] However, the edge isolation process removes a photoactive area of the top
surface where electron and holes can otherwise be generated. This decreases the
efficiency of photovoltaic device. Moreover, the edge isolation renders an increased
portion of active area available for the electron and holes to combine, and hence further
decreasing the efficiency of the photovoltaic device.
[0009] There is therefore a need for a photovoltaic device and/or a method of
manufacturing the photovoltaic device that eliminates or reduces the above limitations.
BRIEF DESCRIPTION OF FIGURES
[0010] The features of the present invention, which are believed to be novel, are set
forth with particularity in the appended claims. The invention may best be understood
by reference to the following description, taken in conjunction with the accompanying
drawings. These drawings and the associated description are provided to illustrate
some embodiments of the invention, and not to limit the scope of the invention.
[0011] FIG. 1 is a flow chart describing a method of manufacturing a photovoltaic
device, in accordance with an embodiment of the present invention;
[0012] FIG. 2 is a diagrammatic illustration depicting exemplary methods of
manufacturing the photovoltaic device, in accordance with some embodiments of the
present invention;
[0013] FIG. 3 is a diagrammatic illustration of a semiconductor substrate, in
accordance with an embodiment of the present invention;
[0014] FIG. 4 is a diagrammatic illustration of a semiconductor substrate and a
semiconductor layer, in accordance with an embodiment of the present invention;
4
[0015] FIG. 5 illustrates a sectional view of the semiconductor substrate and the
semiconductor layer across a section A-A, in accordance with an embodiment of the
present invention;
[0016] FIG. 6 is a diagrammatic illustration of an exemplary step of flipping involved
in an exemplary method of manufacturing the photovoltaic device, in accordance with
an embodiment of the present invention;
[0017] FIGs. 7a and 7b are diagrammatic illustrations of a sectional view and a rear
view of a photovoltaic device, in accordance with an embodiment of the present
invention;
[0018] FIGs. 8a and 8b are diagrammatic illustrations of a sectional view and a rear
view of a photovoltaic device, in accordance with another embodiment of the present
invention; and
[0019] FIGs. 9a and 9b illustrate the sectional views of a photovoltaic device, in
accordance with some embodiments of the present invention.
[0020] Those with ordinary skill in the art will appreciate that the elements in the
figures are illustrated for simplicity and clarity and are not necessarily drawn to scale.
For example, the dimensions of some of the elements in the figures may be
exaggerated, relative to other elements, in order to improve the understanding of the
present invention.
[0021] There may be additional structures described in the foregoing application that
are not depicted on one of the described drawings. In the event such a structure is
described, but not depicted in a drawing, the absence of such a drawing should not be
considered as an omission of such design from the specification.
5
SUMMARY
[0022] The instant exemplary embodiments provide a method of manufacturing a
photovoltaic device.
[0023] Some embodiments provide a method of manufacturing the photovoltaic
device having increased efficiency.
[0024] Some embodiments provide the photovoltaic device with an increased
efficiency, and/ or less chances of recombination centers.
[0025] In some embodiments, a method of manufacturing a photovoltaic cell is
provided. The method includes providing a semiconductor substrate of a first extrinsic
semiconductor material having a first planar surface, a second planar surface and one
or more edge surfaces. The first planar surface is a light-facing surface of the
photovoltaic cell and the second planar surface is substantially parallel to the first planar
surface, but faces opposite to it. The semiconductor substrate is defined by a first
doping polarity, which can either be a p type doping polarity or an n type doping polarity.
Thereafter, the method includes forming a semiconductor layer of at least a second
extrinsic semiconductor material on the semiconductor substrate such that a first portion
of the semiconductor layer is formed on the first planar surface, a second portion of the
semiconductor layer is formed on the second planar surface and an edge portion of the
semiconductor layer is formed on the one or more edge surfaces. The semiconductor
layer is defined by a second doping polarity, which is opposite to the first polarity and
can either be a p type doping polarity or an n type doping polarity.
[0026] Thereafter, a first electrically conducting layer is provided on the first portion
of said semiconductor layer and a second electrically conducting layer on the second
portion of the semiconductor layer. The first electrically conducting layer can be a layer
of a transparent conducting oxide (TCO) or a grid of an electrically conducting material.
[0027] After this, at least a fraction of the second portion of semiconductor layer is
removed to substantially isolate at least a portion of the second electrically conducting
layer from a portion of the semiconductor layer that is directly connected to the first
electrically conducting layer.
[0028] In some embodiments, removing at least a fraction of the second portion of
the semiconductor layer includes creating a groove on the second electrically
6
conducting layer through the second portion of semiconductor layer, such that the
groove is created substantially proximal to the one or more edge surfaces. Further, the
groove can be created using laser grooving, plasma etching, dry etching, wet etching
and/or paste etching.
[0029] In different embodiments of the method of the invention, the semiconductor
layer can be formed by diffusion of extrinsic impurities on the first planar surface, the
second planar surface and said one or more edge surfaces of the semiconductor
substrate, deposition of a melted layer of an intrinsic semiconductor material on the
semiconductor substrate followed by doping, thermal decomposition of a gaseous
precursor comprising the intrinsic semiconductor material on the semiconductor
substrate followed by doping or precipitation of the intrinsic semiconductor material on
the semiconductor substrate from a molten solution of the intrinsic semiconductor
material followed by doping.
[0030] In different implementations, the first extrinsic semiconductor material and
the second extrinsic semiconductor material can include a p type doped or an n type
doped Group IV semiconductor, e.g., Silicon, a p type doped or an n type doped Group
lll/V semiconductor, e.g., Gallium Arsenide (GaAs) or a p type doped or an n type
doped a Group II/VI semiconductor, e.g., Cadmium Telluride (CdTe).
[0031] In some embodiments of the present invention, a photovoltaic device is
provided. The photovoltaic device includes a semiconductor substrate, a semiconductor
layer, a first electrically conducting layer, a second electrically conducting layer and a
groove. The semiconductor substrate is made of a first extrinsic semiconductor material
having a first planar surface, a second planar surface and one or more edge surfaces.
The first planar surface is a light-facing surface of the photovoltaic cell and the second
planar surface is substantially parallel to the first planar surface, but faces opposite to it.
The semiconductor substrate is defined by a first doping polarity, which can either be a
p type doping polarity or an n type doping polarity.
[0032] The semiconductor layer of at least a second extrinsic semiconductor
material is formed on the semiconductor substrate, such that a first portion of the
semiconductor layer is formed on the first planar surface, a second portion of the
semiconductor layer is formed on the second planar surface and an edge portion of the
7
semiconductor layer is formed on the one or more edge surfaces. The semiconductor
layer is defined by a second doping polarity.
[0033] The first electrically conducting layer is provided on the first portion of the
semiconductor layer and the second electrically conducting layer is provided on the
second portion of the semiconductor layer.
[0034] The groove is made on the second electrically conducting layer and passing
through the second portion of semiconductor layer. The groove is substantially proximal
to the one or more edge surfaces such that the groove substantially isolates the second
portion of semiconductor layer from the edge portion of said semiconductor layer.
DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
[0035] Before describing the present invention in detail, it should be observed that
the present invention utilizes a combination of method steps and apparatus components
related to a method of manufacturing a photovoltaic device. Accordingly the apparatus
components and the method steps have been represented where appropriate by
conventional symbols in the drawings, showing only specific details that are pertinent for
an understanding of the present invention so as not to obscure the disclosure with
details that will be readily apparent to those with ordinary skill in the art having the
benefit of the description herein.
[0036] While the specification concludes with the claims defining the features of the
invention that are regarded as novel, it is believed that the invention will be better
understood from a consideration of the following description in conjunction with the
drawings, in which like reference numerals are carried forward.
[0037] As required, detailed embodiments of the present invention are disclosed
herein; however, it is to be understood that the disclosed embodiments are merely
exemplary of the invention, which can be embodied in various forms. Therefore,
specific structural and functional details disclosed herein are not to be interpreted as
limiting, but merely as a basis for the claims and as a representative basis for teaching
one skilled in the art to variously employ the present invention in virtually any
appropriately detailed structure. Further, the terms and phrases used herein are not
8
intended to be limiting but rather to provide an understandable description of the
invention.
[0038] The terms "a" or "an", as used herein, are defined as one or more than one.
The term "another", as used herein, is defined as at least a second or more. The terms
"including" and/or "having" as used herein, are defined as comprising (i.e. open
transition). The term "coupled" or "operatively coupled" as used herein, is defined as
connected, although not necessarily directly, and not necessarily mechanically.
GLOSSARY
[0039] Intrinsic Semiconductor: An intrinsic semiconductor, also called an undoped
semiconductor or an i-type semiconductor, is a pure semiconductor with no or
insignificant doping.
[0040] Extrinsic Semiconductor: An extrinsic semiconductor is formed by doping an
intrinsic semiconductor. It has different electrical properties than the intrinsic (pure)
semiconductor because of different electron and hole carrier concentrations.
[0041] First Extrinsic Semiconductor Material: With reference to the subsequent
specifications, first extrinsic semiconductor material is the material of the semiconductor
substrate. The first extrinsic semiconductor material can be a p type doped or an n type
doped Group IV semiconductor, a p type doped or an n type doped Group III/V
semiconductor and p type doped or an n type doped a Group II/VI semiconductor.
[0042] Second Extrinsic Semiconductor Material: With reference to the subsequent
specifications, second extrinsic semiconductor material is the material of the
semiconductor layer. The second extrinsic semiconductor material can be a p type
doped or an n type doped Group IV semiconductor, a p type doped or an n type doped
Group IIIA/ semiconductor and p type doped or an n type doped a Group II/VI
semiconductor.
[0043] Doping: Doping is the process of intentionally introducing extrinsic impurities
into an intrinsic semiconductor to change its electrical properties. The impurities
selected for doping are dependent upon the desired polarity of the semiconductor.
[0044] p type Doping Polarity: A semiconductor is said to have a p type Doping
Polarity when the number of holes in the semiconductor is greater than the number of
9
electrons. This can be achieved by doping an intrinsic semiconductor with a Group III
element, like, Boron.
[0045] n type Doping Polarity: A semiconductor is said to have a n type Doping
Polarity when the number of free electrons in the semiconductor is greater than the
number of holes. This can be achieved by doping an intrinsic semiconductor with a
Group V element, like, Phosphorous.
[0046] Semiconductor Substrate: With reference to the subsequent specifications,
semiconductor substrate is the substrate of an extrinsic semiconductor on which a
semiconductor layer is formed. Semiconductor substrate is one of the two
semiconductor components contributing to the generation of electricity in the
photovoltaic device.
[0047] Semiconductor Layer: With reference to the subsequent specifications,
semiconductor layer is the layer of an extrinsic semiconductor formed on the
semiconductor substrate. Semiconductor layer has a doping polarity opposite to the
doping polarity of the semiconductor substrate, and it is one of the two semiconductor
components contributing to the generation of electricity in the photovoltaic device.
[0048] Shunt: A 'shunt' is a local short circuit in the photovoltaic device which
renders it incapable of generating electricity.
[0049] Edge Isolation: Removing a portion of the semiconductor layer in a
photovoltaic device such that there is no electrical path between two electrically
conducting layers of a photovoltaic device that does not pass through both
semiconductor components responsible for generating electricity.
[0050] Chemical Vapour Deposition: It is a method of depositing a layer of an
intrinsic semiconductor material. With reference to the specifications, it is an exemplary
method for forming the semiconductor layer. In this method a gaseous or vapour-phase
precursor of the intrinsic semiconductor material, for example, Silicon, is thermally
decomposed on the semiconductor substrate.
[0051] Melt Growth Technique: It is a method of depositing a layer of an intrinsic
semiconductor material. With reference to the specifications, it is an exemplary method
for forming the semiconductor layer. In this method a melted layer of an intrinsic
10
semiconductor material, for example, Silicon, is deposited on the semiconductor
substrate.
[0052] Liquid State Epitaxy: It is a method of depositing a layer of an intrinsic
semiconductor material. With reference to the specifications, it is an exemplary method
for forming the semiconductor layer. In this method, the intrinsic semiconductor material
is precipitated on the semiconductor substrate from a molten solution of the intrinsic
semiconductor material. Such precipitation is done in a temperature range of around
600°C to 1200°C Celsius.
[0053] Referring now to the drawings, FIG. 1 is a flow chart describing a method 100
of manufacturing a photovoltaic device, in accordance with an embodiment of the
present invention.
[0054] In the subsequent description of the method 100, reference will be made to
FIGs. 2, 3, 4, 5, 6, 7a, 7b, 8a, 8b, 9a and 9b to elaborate on structural information
pertaining to various embodiments of the photovoltaic device and the method 100.
[0055] For the purpose of this description, different embodiments of the method 100
are explained for manufacturing of a photovoltaic device 200a, 200b, 900a or 900b
(Refer FIGs. 2, 7a, 7b, 8a, 8b, 9a and 9b). However, it will be readily apparent to those
ordinarily skilled in the art that the method 100 can be used for manufacturing of other
photovoltaic devices having one or more additional layers than the photovoltaic device
200a, 200b, 900a or 900b.
[0056] Additionally, the general description of method 100 is provided with reference
to the photovoltaic device 200a, however, different embodiments of the method 100 that
can be used to manufacture the photovoltaic device 200b, 900a or 900b, are
accordingly described with reference to the corresponding embodiment of the
photovoltaic device.
[0057] The method 100 is initiated at step 102. At step 104, a semiconductor
substrate 202 of a first extrinsic semiconductor material is provided. The semiconductor
substrate 202 is defined by a first doping polarity, based on the doping polarity of the
first extrinsic semiconductor material. For example, the doping polarity of semiconductor
substrate 202 can be a p type doping polarity or an n type doping polarity depending
upon the doping polarity of the first extrinsic semiconductor material.
11
[0058] The first extrinsic semiconductor material can be a p type doped or an n type
doped Group IV semiconductor, a p type doped or an n type doped Group IMA/
semiconductor and p type doped or an n type doped a Group ll/VI semiconductor. For
example, the first extrinsic semiconductor material can be a p type doped or an n type
doped Silicon, a p type doped or an n type doped Gallium Arsenide (GaAs), and a p
type doped or an n type doped Cadmium Telluride (CdTe).
[0059] The invention can be practiced with the semiconductor substrate 202 of
either a doping polarity of p type or a doping polarity of n-type. For the purpose of this
description, the semiconductor substrate 202 is explained as a p type doped
semiconductor substrate and shown to have a doping polarity of p type.
[0060] For the purpose of this description the semiconductor substrate 202 is shown
to be a rectangular planar substrate having a first planar surface 300 (refer FIG. 3), a
second planar surface 302 substantially parallel to the first planar surface 300, and four
edge surfaces 304, 306, 308, and 310. It will be readily apparent to those with ordinary
skill in the art that the semiconductor substrate 202 can be of any other shape, for
example, but not limited to, circular, triangular and hexagonal without deviating from the
scope of the present invention. Accordingly, the semiconductor substrate 202 can have
a different number of the edge surfaces than shown in the FIG. 3. For example, when
the semiconductor substrate 202 is circular in shape there is only one edge surface, and
when the semiconductor substrate 202 is hexagonal in shape then number of the edge
surfaces is six.
[0061] Further, the first planar surface 300 is a light-facing surface and the second
planar surface 302 is at the back of the first planar surface 300, i.e., parallel to the first
planar surface but facing opposite to it. For example, when the photovoltaic device 200a
is put to an application, it is kept in such an orientation that the first planar surface 300
faces the incoming solar light.
[0062] In an exemplary manufacturing set up, the semiconductor substrate 202 can
be provided by cutting an ingot of the first extrinsic semiconductor material, for example,
p type doped Silicon. The examples of such a cutting process include, but are not
limited to, a wire cutting process, a laser cutting process, and the like. The cutting
process may generate damages on the first planar surface 300, the second planar
12
surface 302, and/or the edge surfaces 304, 306, 308, and 310 of the semiconductor
substrate 202. Therefore, the semiconductor substrate 202 obtained after the cutting
process is cleaned prior to performing further processing steps. The cleaning can be
performed using various known techniques such as a wet etching process, a dry etching
process, and the like.
[0063] In some exemplary manufacturing set ups, after cleaning of the
semiconductor substrate 202, texturing is performed on the first planar surface 300.
Texturing is performed to roughen the first planar surface 300 in a predefined manner
so that the light rays falling on the first planar surface 300 undergo reduced reflection,
increased absorption and increased travel within the semiconductor substrate 202.
Preferably, texturing is done to ensure minimum reflection, maximum absorption and
maximum travel of light rays. The texturing can be performed by a wet etching or a dry
etching process. For example, the texturing on the first planar surface 300 can be
performed by etching in an acid solution of Hydrogen Fluoride and Nitric acid.
[0064] Thereafter, at step 106 the semiconductor layer 204 is formed on each of the
first planar surface 300, the second planar surface 302 and the edge surfaces 304, 306,
308, and 310. A sectional view 203 illustrates a work-in-progress structure of the
photovoltaic device 200a after step 106.
[0065] In an embodiment, the semiconductor layer 204 may be formed only on the
first planar surface 300 and the second planar surface 302. In a real life scenario, the
semiconductor layer 204 is intended to be formed only on the first planar surface 300,
however, during the process it gets formed on the edge surfaces 304, 306, 308, 310
and the second planar surface 302 as well.
[0066] The portion of the semiconductor layer 204 formed on the first planar surface
300 of the semiconductor substrate 202 is a first portion 502 (See FIGs. 4 and 5) of the
semiconductor layer 204, the portion of the semiconductor layer 204 formed on the
second planar surface 302 of the semiconductor substrate 202 is a second portion 504
of the semiconductor layer 204, and the portion of the semiconductor layer 204 formed
on the edge surfaces 304, 306, 308 and 310 of the semiconductor substrate 202 is an
edge portion of the semiconductor layer 204.
13
[0067] The doping polarity of the semiconductor layer 204 is opposite to the doping
polarity of the semiconductor substrate 202. For example, when the doping polarity of
the semiconductor substrate 202 is p type, then the doping polarity of the
semiconductor layer 204 is n- type. Similarly, when the doping polarity of the
semiconductor substrate 202 is of n-type, the doping polarity of the semiconductor layer
204 is of p- type. For the purpose of this description, the semiconductor substrate has a
doping polarity of p type and the semiconductor layer has a doping polarity of n type.
[0068] The semiconductor layer 204 can be formed by a number of processes
known in the art, or other processes that may be readily apparent to persons with
ordinary skill in the art, without deviating from the scope of the present invention. For
example, the semiconductor layer 204 can be formed by diffusion, melt growth or melt
coating, chemical vapour deposition and liquid state epitaxy.
[0069] When the n-type semiconductor layer 204 is formed by diffusion of
Phosphorous into the semiconductor substrate 202. The diffusion takes place by
uniformly distributing a thin layer of Phosphoric Acid on the first planar surface 300, the
second planar surface 302 and the edge surfaces 304, 306, 308, and 310. Phosphorous
atoms are diffused in the semiconductor substrate 202 by heating the substrate to a
temperature of about 900°C. Thereby, the semiconductor substrate 202 gets
encapsulated in a thin n-type semiconductor layer 204. In another embodiment, the ntype
semiconductor layer 204 can also be formed by diffusion of any other Group V
element. In an exemplary scenario, when oxide impurities are present in the
semiconductor substrate 202, then these oxide impurities can form an insulating layer
during the heating process. In such a scenario, the insulating layer can be removed by
an etching process.
[0070] When the semiconductor layer 204 is formed using melt growth or melt
coating, a melted layer of an intrinsic semiconductor material, for example, Silicon, is
deposited on the semiconductor substrate 202 and then doped with extrinsic impurities
to provide the doping polarity of n type. In an exemplary case, the semiconductor
substrate 202 is drawn through a bath of molten intrinsic semiconductor material, which
then solidifies as a layer of the intrinsic semiconductor material. Thereafter, the layer of
14
the intrinsic semiconductor material can be doped with a Group V element using
diffusion to obtain the semiconductor layer 204.
[0071] When the semiconductor layer 204 is formed using chemical vapour
deposition process; a gaseous or vapour-phase precursor of the intrinsic semiconductor
material, for example, Silicon, is thermally decomposed on the semiconductor substrate
202. Some examples of the precursors include, but are not limited to, gaseous silane
(SiH4) or trichlorosilane (SiHC13). The layer of intrinsic semiconductor thus formed is
doped with a Group V element, for example, Phosphorous to obtain the n type
semiconductor layer 204.
[0072] When the semiconductor layer 204 is formed using liquid state epitaxy, the
intrinsic semiconductor material is precipitated on the semiconductor substrate 202 from
a molten solution of the intrinsic semiconductor material. Such precipitation is done in a
temperature range of around 600°C to 1200°C Celsius. The layer of intrinsic
semiconductor formed after precipitation is doped with a Group V element, for example,
Phosphorous to obtain the n type semiconductor layer 204.
[0073] Although some exemplary processes of forming the semiconductor layer 204
have been described above to aid in understanding the context of the invention, it will
be readily apparent to those skilled in the art that the invention can be practiced
irrespective of the process used to form the semiconductor layer 204.
[0074] Further, in an embodiment, a thin layer of an antireflective coating is
deposited on the first planar surface 300 above the semiconductor layer 204. The
antireflective coating minimizes the reflection of ttie solar radiation falling on the first
planar surface 300. In an example, the material of antireflective coating is silicon nitride.
However, it can be appreciated that any suitable antireflective coating material known in
the art can be used.
[0075] At step 108, a first electrically conducting layer 206 is formed on the first
portion 502 of the semiconductor layer 204, i.e., the portion of the semiconductor layer
204 formed above the first planar surface 300. The first electrically conducting layer 206
acts as an electrode in the photovoltaic device .200 to enable connecting the
photovoltaic device 200 to an electrical circuit. A sectional view 205 illustrates the workin-
progress structure of the photovoltaic device 200a after step 108.
15
[0076] In an embodiment, the first electrically conducting layer 206 is a grid of an
electrically conducting material. The first electrically conducting layer 206 can be formed
as a grid by using screen printing process. The screen printing process involves
pressing a paste of an electrically conducting substance through a pattern mask.
Thereafter, the semiconductor substrate 202 is heated to cure the paste of the
electrically conducting substance thereby forming the first electrically conducting layer
206 in the grid form. The examples of electrically conducting substance include, but not
limited to, copper, aluminum, silver, gold and the like. The photovoltaic device 900a and
900b in FIGs. 9a and 9b depict the first electrically conducting layer 206 in the form of a
grid 206a.
[0077] In another embodiment, the first electrically conducting layer 206 is a layer of
a transparent conducting oxide (TCO). TCOs are doped metal oxides, fabricated with
polycrystalline or amorphous microstructures. Some examples of the TCO include, but
are not limited to, tin-doped indium-oxide or Indium Tin Oxide (ITO), Aluminum-doped
Zinc-Oxide (AZO) and Indium-doped Cadmium-Oxide.
[0078] In a scenario when the photovoltaic device 200 includes the antireflective
coating over the semiconductor layer 204, the first electrically conducting layer 206 is
formed above the antireflective coating and is not in direct contact with the
semiconductor layer 204. The, contact between the first electrically conducting layer 206
and the semiconductor layer 204 is provided by rapid heating of the first electrically
conducting layer 206 at a temperature of about 900°C. The rapid heating causes the
first electrically conducting layer 206 to etch through the antireflective coating thereby
forming the contact between the electrical conducting grid 206 and the semiconductor
layer 204.
[0079] At step 110, a second electrically conducting layer 208 is provided on the
second portion 504 of the semiconducting layer 204, i.e., the portion of the
semiconductor layer 204 formed on the second planar surface 302, the back surface of
the photovoltaic cell that does not face the solar radiation. The second electrically
conducting layer 208 also acts as an electrode in the photovoltaic device 200 to enable
connecting the photovoltaic device 200 to an electrical circuit. In an example, the
16
second electrically conducting layer 208 is formed by depositing the electrically
conducting substance.
[0080] Thereafter, second electrically conducting layer 208 is dried, for example, by
heating in a furnace. The examples of electrically conducting substance include, but are
not limited to, copper, aluminum, silver, gold and the like. A sectional view 207
illustrates a work-in-progress structure of the photovoltaic device 200a after step 110.
[0081] In the existing art, formation of shunted photovoltaic devices is a common
problem. A 'shunt' is a local short circuit in the photovoltaic device which renders it
incapable of generating electricity. For example, with reference to FIG. 6, there is a
possibility that the electrical current may flow from the first electrically conducting layer
206 through the first portion 502, the edge portion 506 and the second portion 504 to
the second electrically conducting layer 208, i.e., without passing through the
semiconductor substrate 202 and thereby creating a short circuit in the photovoltaic
device.
[0082] Accordingly, manufacturing of the shunted photovoltaic devices reduces the
average production yield and average production efficiency of a manufacturing set up
for photovoltaic devices.
[0083] In view of the above problem of shunting, at step 112, at least a fraction of
the second portion 504 of the semiconductor layer 204 is removed to substantially
isolate at least a portion of the second electrically conducting layer 208 from a portion of
the semiconductor layer 204, which is directly connected to the first electrically
conducting layer 206. Accordingly, the electrical path provided by the at least portion of
the second electrically conducting layer 208 always includes both semiconductor layer
204 and the semiconductor substrate 202, thereby eliminating any short circuit.
[0084] By removing the at least fraction from the second portion 504, in accordance
with the present invention, instead of the first portion 502, the efficiency of the
photovoltaic device can be increased as illustrated in the subsequent description.
[0085] Those skilled in the art will appreciate that the at least fraction can be
removed from the second portion 504 in multiple ways, without deviating from the scope
of the invention. Without intending to limit the scope of the invention, an exemplary
embodiment of removing the at least fraction from the second portion 504 can include
17
creating a groove on the second electrically conducting layer 208 through the second
portion 504 of the semiconductor layer 204, such that the groove is created substantially
proximal to the edge surfaces 304, 306, 308 and 310. Thereafter, the portion of the
second electrically conducting layer which is encompassed by the groove acts as the at
least portion of the second electrically conducting layer and does not provide a short
circuit path to the current.
[0086] In an exemplary manufacturing set up, the groove embodiment of the step
112 can be implemented by flipping the work-in-progress structure 207 so that the
second electrically conducting layer is visible at the top, and then creating a groove. As
shown in FIG. 6 the work-in-progress structure 207 is flipped to obtain the work-inprogress
structure 601, and then the groove can be cut to get the photovoltaic device
200a.
[0087] The processes that can be used to create the groove 210 include, but are not
limited to, a laser .grooving, a plasma etching, a dry etching, a wet etching, a paste
etching, a reactive ion etching etc. In a preferred embodiment, the groove 210 is
created by laser etching using a laser, for example, a Helium - Cadmium (He-Cd) laser.
[0088] FIG. 7a illustrates an enlarged sectional view of the photovoltaic device 200a
and FIG. 7b illustrates the back view of the photovoltaic device 200a. As shown in FIG.
7b the groove 210 isolates the second electrically conducting layer 208 from any portion
of the semiconductor layer 204 that is in contact with the first electrically conducting
layer 206. FIG. 7a and 7b illustrate the embodiment where the first electrically
conducting layer 206 is a continuous layer, for example, of a TCO. FIG. 9a illustrates
the sectional view of a photovoltaic device 900a in which the first electrically conducting
layer is a grid and the groove 210 prevents the shunting problem.
[0089] In another exemplary embodiment, whole of the second portion 504 can be
removed, thereby leaving the second electrically conducting layer 208 to come in
contact with the semiconductor substrate 202 directly. Additionally, it eliminates any
contact between the second electrically conducting layer 208 and the semiconductor
layer 204, thereby eliminating any short circuit (Refer 200b in FIGs. 2, 8a and 8b and
900b in FIG. 9b). Although those with ordinary skill in the art will appreciate that the
entire second portion can be removed by using various processes, one exemplary
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process includes rapidly heating the second electrically conducting layer to a
temperature substantially close to 900 degree Celsius thereby depleting the second
portion of semiconductor layer.
[0090] FIG. 8a illustrates an enlarged sectional view of the photovoltaic device 200b
and FIG. 8b illustrates the back view of the photovoltaic device 200b. As shown in
FIGs. 8a and 8b, the second electrically conducting layer 208 is directly in contact with
the semiconductor -substrate 202 and at the same time, there is not contact between the
second electrically conducting layer 208 and the semiconductor layer 204, thereby the
chances of a short circuit are eliminated. FIGs. 8a and 8b illustrate the embodiment
where the first electrically conducting layer 206 is a continuous layer, for example, of a
TCO. FIG. 9b illustrates the sectional view of a photovoltaic device 900b in which the
first electrically conducting layer is a grid and removal of the second portion 504
prevents the shunting problem.
[0091] Thereafter, the method 100 of manufacturing the photovoltaic cell 200
terminates at step 114.
[0092] Various embodiments of the present invention, as described above, provide a
method for manufacturing a photovoltaic device, which has several advantages. One of
the several advantages of some embodiments of this method is that the efficiency of the
photovoltaic devices manufactured using this method is good, since, the active surface
area of the photovoltaic device has increased as the edge isolation is not performed
over the sun facing surface.
[0093] For example, if the dimensions of the first planar surface of the extrinsic
semiconductor substrate are 156 mm X 156 mm and a laser groove of 30 urn is cut at a
distance of 250 urn from the edge, then the effective surface area that is active, i.e.,
receives light rays is [156 - (2 X. 250) - (2 X .03)]2 mm2, i.e., 24161.6 mm2. However,
when the groove is cut on the second planar surface, i.e., the rear surface that is not
active, then there is no reduction in the effective surface area that is active, and the
active surface area remains 156 X 156 mm2, i.e., 24336 mm2. Similarly, when the entire
second portion is removed, the photoactive area is not reduced. Accordingly, the
present invention leads to an increase in the active surface area by 0.72%.
19
[0094] Further, typically a photovoltaic device with the dimensions mentioned in the
above example and having'an efficiency of 15% generates 3.65 Watts of power.
Therefore, with the increase in area with .72%, the power also such a device increases
3.676 Watts.
[0095] The energy conversion efficiency of photovoltaic devices is defined as the
percentage of power converted (from absorbed light to electrical energy) and collected,
when a photovoltaic device is connected to an electrical circuit, and calculated by the
formula below:
Efficiency = Pm / (E X A);
Where:
Pm = Maximum power point of the photovoltaic device (W)
E = Input light irradiance under standard test conditions, STC (W/m2). STC
specifies a temperature of 25°C and an irradiance of 1000 W/m2 with an air mass 1.5
(AM1.5) spectrum.
A = Surface area of the photovoltaic device (m2)
[0096] Therefore, the efficiency of the photovoltaic device in accordance with the
present invention can be calculated as:
Efficiency,Invention = 3.676/(1000 X .024336) X 100 = 15.105 %
[0097] The present invention, therefore, increases the efficiency of the photovoltaic
device by more than 0.1 %.
[0098] Moreover, the there are lesser chances of generation of recombination
centers over the photoactive area as no groove is created on the active surface, for
example, the groove is made at the back surface. The recombination centers are the
areas where the electron and hole combine each other thereby reducing the number of
charge carriers. Therefore, the efficiency of the photovoltaic device is further enhanced.
[0099] While the invention has been disclosed in connection with the preferred
embodiments shown and described in detail, various modifications and improvements
thereon will become readily apparent to those ordinarily skilled in the art. Accordingly,
the spirit and scope of the present invention is not to be limited by the foregoing
examples, but is to be understood in the broadest sense allowable by law.
[00100] All documents referenced herein are hereby incorporated by reference.

CLAIMS
What is claimed is:
1. A method of manufacturing a photovoltaic cell, the method comprising:
providing a semiconductor substrate of a first extrinsic semiconductor material,
said semiconductor substrate having a first planar surface, a second planar surface and
one or more edge surfaces, wherein said first planar surface is a light-facing surface of
said photovoltaic cell, said second planar surface is substantially parallel and facing
opposite to said first planar surface, and wherein said semiconductor substrate is
defined by a first doping polarity;
forming a semiconductor layer of at least a second extrinsic semiconductor
material on said semiconductor substrate, wherein a first portion of said semiconductor
layer is formed on said first planar surface, a second portion of said semiconductor layer
is formed on said 'second planar surface and an edge portion of said semiconductor
layer is formed on said one or more edge surfaces; and wherein said semiconductor
layer is defined by a second doping polarity;
providing a first electrically conducting layer on said first portion of said
semiconductor layer;
providing a second electrically conducting layer on said second portion of said
semiconductor layer; and
removing at least a fraction of said second portion of semiconductor layer to
substantially isolate at least a portion of said second electrically conducting layer from a
portion of said semiconductor layer that is directly connected to said first electrically
conducting layer.
2. The method according to claim 1, wherein said removing at least a fraction of
said second portion of semiconductor layer comprises creating a groove on said second
electrically conducting layer through said second portion of semiconductor layer,
wherein said groove being created substantially proximal to said one or more edge
surfaces.
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3. The method according to claim 2, wherein said creating of said groove comprises
one of laser grooving, plasma etching, dry etching, wet etching and paste etching.
4. The method according to claim 1, wherein said first polarity is opposite to said
second polarity, and wherein said each of said first polarity and said second polarity is
one of an n type polarity and a p type polarity.
5. The method according to claim 1, wherein said forming of said semiconductor
layer on said semiconductor substrate comprises at least one of:
diffusion of extrinsic impurities on each of said first planar surface, said second
planar surface and said one or more edge surfaces of said semiconductor substrate;
deposition of a melted layer of an intrinsic semiconductor material on said
semiconductor substrate and doping said intrinsic semiconductor material based on
said second polarity;
thermal decomposition of a gaseous precursor comprising said intrinsic
semiconductor material on said semiconductor substrate and doping said intrinsic
semiconductor material based on said second polarity; and
precipitation of said intrinsic semiconductor material on said semiconductor
substrate from a molten solution of said intrinsic semiconductor material and doping
said intrinsic semiconductor material based on said second polarity.
6. The method according to claim 1, wherein said first extrinsic semiconductor
material and said second extrinsic semiconductor material are selected from the group
comprising a p type doped or an n type doped Group IV semiconductor, a p type doped
or an n type doped Group IMA/ semiconductor and p type doped or an n type doped a
Group ll/VI semiconductor.
7. The method according to claim 1, wherein said first extrinsic semiconductor
material and said second extrinsic semiconductor material are selected from the group
comprising a p type doped or an n type doped Silicon, a p type doped or an n type
22
doped Gallium Arsenide (GaAs), and a p type doped or an n type doped Cadmium
Telluride (CdTe).
8. The method according to claim 1, wherein said first electrically conducting layer
comprises a grid of an electrically conducting material.
9. The method according to claim 1, wherein said first electrically conducting layer
comprises a layer of a transparent conducting oxide (TCO).
10. A photovoltaic device comprising:
providing a semiconductor substrate of a first extrinsic semiconductor material,
said semiconductor substrate having a first planar surface, a second planar surface and
one or more edge surfaces, wherein said first planar surface is a light-facing surface of
said photovoltaic cell, said second planar surface is substantially parallel and facing
opposite to said first planar surface, and wherein said semiconductor substrate is
defined by a first doping polarity;
a semiconductor layer of at least a second extrinsic semiconductor material
formed on said semiconductor substrate, wherein a first portion of said semiconductor
layer is formed on said first planar surface, a second portion of said semiconductor layer
is formed on said second planar surface and an edge portion of said semiconductor
layer is formed on said one or more edge surfaces; and wherein said semiconductor
layer is defined by a second doping polarity;
a first electrically conducting layer provided on said first portion of said
semiconductor layer;
a second electrically conducting layer provided on said second portion of said
semiconductor layer; and
a groove on said second electrically conducting layer passing through said second
portion of semiconductor layer, said groove being created substantially proximal to said
one or more edge surfaces, wherein said groove substantially isolating said second
portion of semiconductor layer from said edge portion of said semiconductor layer.