Claims: 1. A memory device structure, comprising:
a transistor, comprising:
a channel between a source and a drain, the channel along a longitudinal axis of the transistor;
a gate electrode along a first direction orthogonal to the longitudinal axis; and
a gate dielectric layer between the gate electrode and the channel;
a first interconnect coupled with the source or the drain, the first interconnect colinear with the channel;
a pair of second interconnects along a second direction orthogonal to both the longitudinal axis and the first direction; and
a pair of memory cells, wherein individual ones of the pair of memory cells comprises a selector element and a memory element, wherein a first terminal of the individual ones of the pair of memory cells is coupled to the first interconnect and wherein a second terminal of the individual ones of the pair of memory cells is coupled to individual ones of the pair of second interconnects.

2. The memory device structure of claim 1, wherein:
the pair of memory cells is a first pair of memory cells within a first tier;
the memory device structure further comprises a second pair of memory cells above the first pair of memory cells within a second tier;
individual ones of the second pair of memory cells comprises a selector and a memory element;
a first terminal of the individual ones of the second pair of memory cells is coupled to a portion of the first interconnect within the second tier; and
a second terminal of the individual ones of the second pair of memory cells is coupled to individual ones of a pair of third interconnects, wherein the pair of third interconnects is parallel to and above the pair of second interconnects.

3. The memory device structure of claim 2, wherein:
the memory element and the selector element in the first pair of memory cells and in the second pair of memory cells are connected in series; and
either the memory elements or the selector elements of the individual ones of the first pair of memory cells and of the second pair of memory cells are each coupled to the first interconnect.

4. The memory device structure of claim 1, wherein the channel comprises a polycrystalline or amorphous material.

5. The memory device structure of claim 4, wherein the polycrystalline or amorphous material comprises In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, ZnRh2O4 or CuOx, where x is 1 or 2.

6. The memory device structure of any one of claims 1-5, wherein the channel surrounds a core comprising a dielectric material, wherein the gate dielectric layer surrounds the channel and wherein the gate electrode surrounds the gate dielectric layer.

7. The memory device structure of claim 6, wherein the drain is above the source and the core, wherein the drain is between portions of the channel adjacent to the gate dielectric layer, wherein the source is adjacent to the gate dielectric layer and a portion of the channel extending along the first direction.

8. The memory device structure of claim 7, wherein the drain and the core each have a substantially same lateral thickness along the first direction.

9. The memory device structure of claim 6, wherein the drain is above the source, wherein the core is directly between the source and the drain, and wherein the source and the drain each have a substantially same lateral thickness along the first direction.

10. The memory device structure of any one of claims2-3, wherein the source or the drain has a first lateral thickness along the first direction, wherein the individual ones of the memory cells in the first pair of memory cells and in the second pair of memory cells each have a second lateral thickness along the first direction and wherein the first lateral thickness is less than two times the second lateral thickness.

11. The memory device structure of claim 2-3, wherein the first interconnect has a first lateral thickness along the first direction, wherein individual ones of the memory cell in the first pair of memory cells and in the second pair of memory cells each have a second lateral thickness along the first direction, wherein the first lateral thickness is less than the second lateral thickness.

12. The memory device structure of any one of claims 1-5, wherein the transistor is in an array of transistors along the first direction and wherein the gate electrodes of the individual ones of the transistor in the array of transistors are coupled in electrical parallel.

13. The memory device structure of any one of claims 1-5, wherein the first interconnect has a first lateral thickness along the first direction wherein the first lateral thickness is between 50 nm and 70 nm, wherein individual ones of the pair of second interconnects has a second lateral thickness and wherein the second lateral thickness is between 35nm and 50 nm.

14. A method of fabricating a vertical transistor, comprising:
forming a first electrode structure above a substrate;
forming a material layer stack on the first electrode structure, wherein
forming the structure comprises depositing a gate electrode material on a first dielectric above the first electrode, and depositing a second dielectric on the gate electrode material;
forming an opening in the material layer stack and exposing the first electrode;
forming a gate dielectric layer in the opening adjacent the gate electrode material;
forming a channel layer in the opening adjacent the gate dielectric layer;
forming a second dielectric in the opening adjacent the channel layer, wherein the dielectric partially fills the opening; and
forming a second electrode in the opening.

15. The method of claim 14, wherein forming the first electrode comprises patterning a first electrode material above a substrate and forming a dielectric material on the first electrode and planarizing the dielectric material to conceal the first electrode.

16. The method of any one of claims 14-15, wherein forming the opening comprises etching the second dielectric and etching the gate electrode material to form an opening.

17. The method of any one of claims 14-15, wherein forming the gate dielectric layer comprises:
depositing a gate dielectric layer material in the opening and on the first electrode; and
etching the gate dielectric layer in contact with the first electrode to expose the first electrode.

18. The method of any one of claims 14-15, wherein forming the second dielectric comprises blanket depositing the second dielectric to fill the opening and recessing the second dielectric to a level that is substantially coplanar with a top surface of the gate electrode material.

19. A system comprising:
a battery to power the system; and
a memory device structure, comprising:
a transistor, comprising:
a channel between a source and a drain, the channel along a longitudinal axis of the transistor;
a gate electrode along a first direction orthogonal to the longitudinal axis; and
a gate dielectric layer between the gate electrode and the channel;
a first interconnect coupled with the source or the drain, the first interconnect colinear with the channel;
a pair of second interconnects along a second direction orthogonal to both the longitudinal axis and the first direction; and
a pair of memory cells, wherein individual ones of the pair of memory cells comprises a selector element and a memory element, wherein a first terminal of the individual ones of the pair of memory cells is coupled to the first interconnect and wherein a second terminal of the individual ones of the pair of memory cells is coupled to individual ones of the pair of second interconnects.

20. The system of claim 19, further comprises a memory controller coupled with the memory device structure.
, Description:This application claims priority to U.S. Non-Provisional Patent No. 17/118,385, filed on December 10, 2020, entitled PILLAR SELECT TRANSISTOR FOR 3-DIMENSIONAL CROSS POINT MEMORY, the disclosure of which is hereby incorporated by reference.

BACKGROUND
A three-dimensional (3-D) cross point memory array may have tiers, or decks, of memory cells. However, increasing a total number of memory cells in this manner may proportionately increase the number of decoder transistors needed, thereby increasing an overall footprint of the decoder transistors. As such, solutions are required to increase memory density while minimizing decoder transistor footprint.

BRIEF DESCRIPTION OF THE DRAWINGS
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified “ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
Figure 1A is a cross-sectional illustration of a memory device structure including a vertical transistor coupled with a tiered memory array.
Figure 1B is a plan-view illustration of a line segment through mid plane of the transistor in Figure 1A.
Figure 1C is a cross-sectional illustration of a memory cell, in accordance with an embodiment of the present disclosure.
Figure 1D is a cross-sectional illustration of a memory cell, in accordance with an embodiment of the present disclosure.
Figure 2A is a cross-sectional illustration of a memory element, in accordance with an embodiment of the present disclosure.
Figure 2B is a cross-sectional illustration of a memory element, in accordance with an embodiment of the present disclosure.
Figure 2C is a cross-sectional illustration of a selector element, in accordance with an embodiment of the present disclosure.
Figure 2D is a cross-sectional illustration of a built-in memory selector cell, where an insulator layer exhibits memory element and selector element characteristics.
Figure 2E is a cross-sectional illustration of a switching layer adjacent to an insulator layer, in accordance with an embodiment of the present disclosure.
Figure 3A is an isometric illustration of memory device structure including a vertical transistor array coupled with a tiered memory array, in accordance with an embodiment of the present disclosure.
Figure 3B is a plan view of a portion of a tier of the memory device structure in Figure 3A.
Figure 3C is a plan view of a portion of a tier of the memory device structure in Figure 3A.
Figure 4A illustrates a material layer stack formed above a substrate.
Figure 4B is a cross-sectional illustration of the structure in Figure 4A following the process to mask and etch to form a staircase structure.
Figure 4C is a cross-sectional illustration of a portion of the material layer stack in Figure 4B, following the process to etch and form plurality of openings.
Figure 4D illustrates the structure of Figure 4C following a process to selectively laterally recess portions of a dielectric to form a plurality of recesses.
Figure 4E illustrates the structure of Figure 4D following the formation of an electrode material in the plurality of lateral recesses.
Figure 4F illustrates the structure of Figure 4E following the process to etch and remove portions of the electrode material from the plurality of openings and from portions of lateral recesses.
Figure 4G illustrates the structure of Figure 4F following the deposition of a selector material in the plurality of recesses adjacent to the electrode material.
Figure 4H illustrates the structure of Figure 4G following the process to etch and remove portions of the selector material from portions of lateral recesses adjacent to the electrode material.
Figure 4I illustrates the structure of Figure 4H following the formation of electrode material adjacent to the selector material.
Figure 4J illustrates the structure of Figure 4I following the deposition of one or more layers of memory material in the plurality of recesses adjacent to the electrode material.
Figure 4K illustrates the structure of Figure 4J following the process to etch and remove portions of the memory material and from portions of lateral recesses adjacent to electrode material.
Figure 4L illustrates the structure of Figure 4K following the formation of electrode material adjacent to the memory material.
Figure 5A illustrates the structure of Figure 4L following the formation of a dielectric in the plurality of openings.
Figure 5B is an isometric illustration of the structure in Figure 5A through the line A-A’.
Figure 6A is cross sectional illustration of a cut mask implementation to form individual memory cells.
Figure 6B is a plan view illustration of a portion of the mask over structure of Figure 5A.
Figure 7 is an isometric illustration of the structure in Figure 5A post a cut etch process.
Figure 8A is a cross sectional illustration of the structure in Figure 7 through the line A-A’, following the process to form electrodes.
Figure 8B illustrates the structure of Figure 8A following the formation of a first set of conductors and a second set of conductors in three levels of memory array.
Figure 9 is a method to fabricate a transistor described in association with Figures 1A-1B, in accordance with an embodiment of the present disclosure.
Figure 10A is a cross-sectional illustration of an electrode formed above a substrate.
Figure 10B illustrates the structure of Figure10C following the process to form a material layer stack on a first dielectric above the electrode.
Figure 10C illustrates the structure of Figure 10C following the formation of an opening in the material layer stack.
Figure 10D illustrates the structure of Figure 10C following the formation of a gate dielectric layer in the opening.
Figure 10E illustrates the structure of Figure 10D following the process to etch and remove portions of the gate dielectric layer from above the electrode.
Figure10F illustrates the structure of Figure 10E following the formation of a material for channel layer in the opening on the electrode, and on the gate dielectric layer.
Figure 10G illustrates the structure of Figure 10F following the formation of a second dielectric in the opening.
Figure 10H illustrates the structure of Figure 10G following the process to selectively recess the second dielectric with respect to the gate dielectric layer and channel layer.
Figure 10I illustrates the structure of Figure 10H following the formation of a top electrode.
Figure 11 is a cross-sectional illustration of a transistor structure where the source structure and drain structure each have a same lateral thickness.
Figure 12A is a cross-sectional illustration of an array of transistors.
Figure 12B is a cross-sectional illustration of a tiered memory array on a logic transistor array, in accordance with an embodiment of the present disclosure.
Figure 13 is a block diagram of an example of a computing system that includes a pillar select transistor array coupled with a memory device array to enable decoder transistor footprint scaling.
Figure 14 is a block diagram of an example of a system, where a memory that includes pillar select transistor array coupled with a memory device array to enable decoder transistor footprint scaling.

DESCRIPTION OF THE EMBODIMENTS
Pillar select transistors for 3-D cross point and methods of fabrication are described below. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as operations associated with field effect transistors (FETs) and memory or selector elements, are described in lesser detail to not obscure embodiments of the present disclosure. Furthermore, the various embodiments shown in the Figures are illustrative representations but are not necessarily drawn to scale.
In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical or in magnetic contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.
The term “adjacent” here generally refers to a position of a thing being laterally next to (e.g., immediately next to with one or more things between them) or adjoining another thing (e.g., abutting it).
The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references.
The term “device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.
As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.
Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/-10% of a predetermined target value.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in the context of a figure provided herein may also be “under” the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.
The term “between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.
Memory cells are used in conjunction with large arrays of decoder transistors for a variety of 3-D cross point memory applications. A 3-D cross point memory array often includes a series of word lines on a first plane and series of bit lines on a second plane above the first plane, where the word lines orthogonally cross over the bit lines (or vice versa). A memory cell is located at each point of cross over (cross-point) between the word line and the bit line, where the memory cell couples a word line with a corresponding bit line to form a single memory array deck, or herein deck.
In embodiments, an effective cell size of a cross point memory cell is equal to a cell pitch squared divided by a number of decks.In some embodiments, a number of memory decks is approximately 6 or less. Memory scaling may be limited by a certain memory pitch (lateral spacing between memory cells) when an upper limit for the number of memory decks is reached. Memory density may be increased in conventional 3-D cross point memoryby pitch scaling and stacking layers (increasing number of decks). However, production cost may increase significantly with more decks as a function of the number of process operations needed to fabricate each deck.
However, the inventors have devised an arrangement that can increase the number of stacks in a memory device structure without concomitantly increasing memory device production costs. In accordance with an embodiment of the present disclosure, the memory device structure includes memory cells where a memory element is laterally coupled with a selector element in each memory cell. In further embodiments, the memory device structure may include a plurality of memory cells in an array extending in two orthogonal directions on a plane to form a tier, or deck. The memory device structure may include a plurality of decks that are stacked. During operation, the memory device structure may permit the selection of a unique set of word line, bitline and tier/deck address to access a pair of memory cells.
The memory device structures described herein may advantageously reduce a number of decoder or programming transistors, providing a reduction in chip area. A decoder transistor may be individually coupled with each word line and a bit line to address a particular memory cell in a tier. When the number of memory cells are increased, the number of bit lines and word lines increase in proportion as does the number of decoder transistors required to address each memory cell (bit cell). To accommodate a larger number of decoder transistors in a vicinity of a cross point array, such as, for example below the cross-point memory array, relative lengths of a word line and bit line may be increased. Alternatively, decoder transistors may occupy a region laterally adjacent to the memory array. In either example a larger chip area may be utilized.
Increasing number of layers (tiers) of memory cells to form a 3-dimensional array can increase memory density per unit area. However, increasing the number of memory cells also proportionately increases the number of decoder transistors required. In some examples a single tier may include 4K bit lines and 4K word lines. Thus, a single 4K by 4K tier can require 8K decoder transistors. Because the number of decoder transistors increases proportionally with the number of tiers, enabling a high-density memory array for a given die size can be highly challenging.
In accordance with some embodiments, multiple (e.g., two) memory cells in a tier are coupled through a common electrode to reduce the number of decoder transistors. The common electrode may be further coupled to a source or a drain of a decoder transistor directly below. In addition to coupling multiple memory cells by a common electrode to reduce the total number of decoder transistors, confining the decoder transistors to within a footprint of a memory cell is also advantageous for reducing device footprint.
Another advantage of the memory device structures in accordance with embodiments is that memory cells in various tiers may be concurrently fabricated, which may significantly reduce fabrication costs per memory cell.
Figure 1A is a cross sectional illustration of a memory device structure 100 including a vertical pillar select transistor 102 coupled with a tiered memory structure 103.As shown, pillar select transistor 102includes a channel layer 104between a source structure106 and a drain structure 108. As shown, the channel layer 104is directed along a longitudinal axis of the pillar select transistor 102(along y-axis in Figure). The pillar select transistor 102 also includes a gate electrode 110 adjacent to the channel layer 104 . The gate electrode 110 has a length in a direction orthogonal to longitudinal axis (along x-axis).A gate dielectric layer 111 is between the gate electrode 110 and the channel layer 104 . The memory device structure 100 further includes an interconnect 112, where the interconnect 112 is colinear with the longitudinal axis of pillar select transistor 102. In the illustrative embodiment, terminal 112A of the interconnect 112 is coupled with the drain structure108. In an exemplary embodiment, interconnect 112 is coupled to an interconnect 113 through the pillar select transistor 102. interconnect 113 is representative of a bit line in memory device structure 100. In the illustrative embodiment, interconnect 113 is below and coupled to the source structure 106.
As shown, pillar select transistor 102is a thin film transistor. In the illustrative embodiment, the channel layer 104includes a horizontal channel portion 104Aand vertical channel portions104B. Horizontal portion 104A is adjacent to source structure 106 and vertical portions 104B are adjacent to gate dielectric layer 111.The channel layer 104may laterally overlap with drain structure 108.In the illustrative embodiment, vertical channel portions 104B laterally confines drain structure 108. In other embodiments, vertical channel portions 104B is under drain structure 108. The channel layer 104is also adjacent to a dielectric 124. Dielectric 124 has a vertical thickness along the longitudinal axis that modulates a gate length, LG, of the pillar select transistor 102.An electrical gate length of pillar select transistor 102 is determined by a thickness of the gate electrode 110 along the longitudinal axis. In an embodiment, LG, is between 50 nm and 500 nm.A desired LG further depends on a maximum operating voltage of the pillar select transistor 102.
In the cross-sectional illustration, the gate electrode 110 is spatially distant, along the longitudinal axis (e.g., y-axis) from source structure 106. However, gate electrode 110 may overlap drain structure 108along the longitudinal axis.In some embodiments, gate electrode 110 may laterally overlap drain structure 108 with an intervening dielectric 124 between the channel layer 104and gate electrode 110.
Figure 1B is a plan view illustration through a line A-A’ in Figure 1A. As shown, various layers in pillar select transistor 102 are substantially conformal cladding layers around the dielectric 124. As shown, channel layer 104clads dielectric 124, gate dielectric layer 111 clads channel layer 104and the gate electrode 110 clads the gate dielectric layer 111. Dielectric 124 has a lateral thickness WDE, that is substantially greater than lateral thicknesses, WC of the channel layer 104and lateral thickness, WGDL, of gate dielectric layer 111. In embodiments, channel layer 104has a lateral thickness WC that is between 5 nm and 20 nm. In some embodiments, the gate dielectric layer 111 has a lateral thickness WG that is between 1 nm and 3 nm.
The gate electrode 110 has a length, LGE, in a direction orthogonal to the longitudinal axis of the channel layer 104 . LGE is distinct from LG, or transistor gate length illustrated in Figure 1A. The gate electrode 110 has a width, WGE. WGE is measured along the z-axis in a direction along the interconnect 114or 116 (not shown in the Figure). In an exemplary embodiment, WGEis less than 150 nm.
Referring again to Figure 1A, drain structure 108 has a lateral thickness, WD, and source structure 106 has a lateral thickness, WS, along the x-axis. In the illustrative embodiment, WD is less than WS. In the illustrative embodiment, the source structure 106 has a lateral thickness that is equal to combined sum of lateral thicknesses of the drain structure 108, twice a lateral thickness of the gate dielectric layer 111 and twice a lateral thickness of the channel layer 104.
The transistor 102 is coupled with tiered memory structure 103 through interconnect 112.
The tiered memory structure 103 includes a plurality of tiers. In the illustrative embodiment, two tiers are shown, for example a tier 132 and a tier 134 directly above tier 132. As shown, tier 132includes a pair of memory cells 118 and 120 and a pair of interconnects such as interconnect 114 and interconnect 116 that extend orthogonal to the interconnect 112(e.g., z-axis). Interconnects 116 and 114 are examples of word lines of the memory device structure 100.As shown,each memory cell 118 and 120 is symmetrically coupled to a portion of the interconnect 112 laterally between respective interconnects 114 and116.
In the illustrative embodiment, each of the memory cells 118 and 120 include a terminal 121 and a terminal 122 at an opposite end of terminal 121. One of the terminals 121 or 122 of each memory cell is coupled to the transistor 102 (through the interconnect 112) and a second of the terminals 121 or 122 is coupled with either interconnect 114 or 116.As shown terminal 121 of each memory cell is coupled to interconnect 112 and terminal 122 of each memory cell is coupled to interconnect 114 or interconnect 116.In the illustrative embodiment, terminal 121 of each memory cell 118 and 120 is coupled to a terminal 112B and 112C, respectively, of interconnect 112, within tier 132. Also as shown, a terminal 122 of memory cell 118 is coupled with an interconnect 114 and terminal 122 of memory cell 120 is coupled with an interconnect 116.
In the illustrative embodiment, the tiered memory structure 103 further includes an additional pair of memory cells 136 and 138 that are symmetrically coupled to a portion of the interconnect 112 within tier 134. In exemplary embodiments, memory cells 136 and 138 are directly above memory cells 118 and 120, respectively. Tier 134 further includes a pair of interconnects, such as interconnect 140 and interconnect 142 that are above and parallel to interconnects 114 and 116, respectively. Interconnects 140 and 142 are examples of word lines of memory device structure 100. In the illustrative embodiment, a terminal 121 of each memory cell 136 and 138 is coupled to a terminal 112D and 112E, respectively of interconnect 112. As shown, a terminal 122 of memory cell 136 is coupled with interconnect 140 and terminal 122 of memory cell 138 is coupled with interconnect 142.
It is to be appreciated that interconnects 114, 116, 140 and 142 can be independently voltage biased to program any of the four memory cells 118, 120, 136 or 138 in memory device structure 100.
Tier 134 is spaced apart from tier 132 along the longitudinal axis of the channel layer 104, (e.g., y-axis), by a distance, STT. In embodiments, STT is between 5 nm and 30 nm. Tier 132 and tier 134 each have a vertical thickness, TT, measured along the longitudinal axis of the channel layer 104. In embodiments TT is between 5 nm and 20 nm.
As shown, interconnect structure 112 has a lateral thickness, WI, where WI, is measured along the x-direction. As shown, each memory cell 118 and 120 has a lateral thickness, WMC, that is between 100 nm and 120 nm. In the illustrative embodiment, the interconnects 140 and 142 are spaced apart by a lateral thickness, WEE, along the x-axis, that is equal to a combined lateral thickness of the memory cells 118 and 120 and the lateral thickness, WI of the interconnect structure 112, as given by equation [1]:
WEE = WI + 2* WMC [1]
where, WMC is a lateral thicknesses, of each of the memory cells 118, 120, 136 and 138. In an exemplary embodiment, WMC is the same or substantially the same for each memory cell 118, 120, 136 and 138. WI may be increased or decreased in proportion to WMC to keep WEE fixed.
Lateral thickness of features of pillar select transistor 102 are related to dimensions of the memory cells 118 and 120 and interconnect 112 in tier 132. WEE may be greater than or comparable to WS. However, for functionality it is advantageous for WS to be compared to another lateral dimension of the memory array. To prevent gate dielectric layers of adjacent transistors (in an array) from connecting, the source contact has a lateral thickness WS, that is related to a lateral thickness, WMU, of a memory unit described by equations [2] and [3] below:
WS