PLDs PROVIDING READBACK OF CONFIGURATION DATA
Field of the invention
This invention relates to a system and method for providing read-back of configuration data stored in the configuration memory of Programmable Logic Devices (PLDs).
Background of the invention
Programmable Logic Devices incorporate a configuration memory for storing configuration data that defines the functional behaviour of the device in a given application. The Configuration Memory typically consists of an array of data latches arranged in a matrix. There are several methods known in the prior art for the programming of the data latches of the Configuration Memory, however none of the known methods provides for readback of Configuration data. The data readback is desirable as it provides an accurate verification of the programming of the Configuration memory.
US Patent 5,237,219 describes a popular method for programming the data latches in the Configuration Memory of a PLD. This invention describes an arrangement in which the configuration data is stored in an array of data latches connected in series as shown in figure 1. The arrangement includes a Data Register 114, an Address Register 116, and Test Register 118. Configuration data for one Row of the Configuration Memory is serially shifted into Data Register 114 and a bit pattern corresponding to the row to be programmed is serially shifted into Address Register 116. The addressing scheme is such that for programming a particular Row all the Rows above that Row have to be selected while the Rows below the Row to be programmed are deselected. This arrangement cascades the
configuration data down through all the upper rows upto the row to be programmed. The configuration data is thus copied into all the selected rows without disturbing the data in the deselected rows. The configuration process accordingly begins with the lowermost row and proceeds upwards with the uppermost row being programmed last. The data is serially shifted to the registers 114, until all the registers are loaded with the data. To start the configuration all access lines 137/1 to 137/n are enabled, and data is shifted from register 114 through rows 1 to n to test register 118. Correct loading of data in test register 118 signifies that the latches series is defect free.
The data is now configured for the last row of data latches i.e. elements 130A/n, 130B/n etc. For this all the row enable line from 137/1 to 137/n is enabled and configuration data is shifted from register 114 through rows 1 to n to latches 130/n. Thereafter, the next set of data is shifted to the register 114 and row n-1 is configured by disabling line 137/n. The remaining data latches are configured in a similar manner consecutively by shifting data into register 114 and disabling the connection of the configured data latch row from rest of the circuitry. This invention does not have any provision for readback of Configuration data.
US Patent No. 6,011,406 describes an improvement over the method of US patent 5,237,219 for speeding-up the programming of the configuration memory. In this method the rows of the Configuration memory matrix are split into 2 interleaved banks with adjacent rows assigned to different banks. A set of AND gates 260 selects either one of the 2 banks at a time and cascades the data down from the row of one bank to the adjacent row of the other bank. The data is transferred simultaneously across each pair of rows. The data propagation delay therefore corresponds to only one latch delay, unlike the previous arrangement in which the
data had to propagate across multiple rows. Each of the AND gates 260 has one input connected to one of the two row enable lines 272, 274 alternately with the other input coming from the outputs of shift registers 216. The data is made to 'walk down' to its target programmable elements in a repeated sequence of substeps. In the first substep the data from the data source is loaded into the first programmable elements. Then the data from the even numbered programmable elements is loaded into succeeding odd-numbered programmable elements in the series. The sequence is repeated until the data reaches the final data latch, after which the last data latch is disconnected and the remaining data latches are configured in reverse sequence upto the first row. This invention also suffers from the limitation that it does not provide any mechanism for readback of the configuration data.
Object and summary of the invention
The object of the invention is to enable readback of Configuration Data of PLDs.
To achieve this objective, this invention provides a Programmable Logic Device (PLD) and Programmable Gate Array (PGA) comprising an input data selector having one input connected to the output of the configuration memory, the output of the input data selector being connected to an input data register supplying data to the matrix of data latches storing the configuration data with the output from each row except the last row being selectively connected to the inputs of the next row, with the last row providing the output from the configuration memory, and a row selector that sequentially enables the interconnection of one or more rows of the matrix such that the data from the input data register is stored in the desired row.
The invehtion also provides for a method for enabling readback of configuration data stored in a configuration memory constructed of a matrix of data storage elements arranged in row and column format with the outputs from each row of data latches except the last row selectably connected to the data inputs of the next row and the last row providing the output from the configuration memory. The method operates by selecting the input data source of the configuration memory as either the configuration data source during normal mode or the data from the output of the configuration memory during readback mode. After registering the input data the connection of one or more rows of the configuration data storage element matrix are enabled for storing the registered data in the desired row, and the sequence of receiving and storing input data and sequentially enabling rows of the configuration memory is repeated, until the entire data has been written into the configuration memory.
During readback the data is sequentially read out from the output of the configuration memory and made available as the readback data while it is simultaneously fedback as input data for writing back into the configuration memory.
Brief description of the drawings:
The invention will now be described with reference to the accompanying drawings.
Figure 1 shows a configurable memory according to the prior art described in US patent 5237219.
Figure 2 shows an improved configuration memory according to the prior art of US patent 6011406.
Figure 3 shows a configuration memory according to the proposed invention. Detailed description of the drawings
Figure 1 and figure 2 have already been described in the background to the invention.
Figure 3 shows a preferred implementation in accordance with the proposed invention applied to the method disclosed in the US patent number 5237219. An average person in the art will understand that this method can be easily applied to other methods of configuration as well.
Multiplexer 340 is inserted in between the normal data input 344 and the input data register 314. The output of the test or readback register 318 is connected as the second input 348 of the multiplexer 340. Select line 342 of the multiplexer selects either normal data input 344 or data from output line 348 i.e. during configuration it selects data from the configuration data input 344 and during readback it selects data from test register output line 348.
When the select line 342 is low then the configuration is operating in normal mode, and the data latches are configured, otherwise the readback mode is selected.
hi the normal mode of operation the data is first serially shifted into input register 314. To start the configuration access lines 337/1 to 337/n are enabled, and data is shifted from input register 314 through 330A/1, 330B/1 etc. and 330A/n, 330B/n
etc to test register 318. If the data is correctly loaded in register 318 it implies that the latch series is defect free.
The data is then loaded upto the last row of the data latches i.e. elements 330A/n, 330B/n etc. after which line 337/n is disabled leaving the configured latches disconnected from the rest of the circuitry. The remaining rows are sequentially loaded in a similar manner.
In the readback mode select line 342 is set high, hi this mode the input multiplexer

selects the input line connected to the output of the Test Register 318. The data from the row connected to the Test Register 318 is therefore fedback to the input data register 314 through the multiplexer 340. At the same time select register 316
sequentially enables select lines 337/n, 337/n-l to 337/1 resulting in the
shifting of data from each data latch row or register to the subsequent data latch row or register. With this action data that was configured in the last row of data latches 330A/n, 330B/n etc. is brought into the first row of data latches 330A/1, 330B/1 etc. and the data in the second and each subsequent row of data latches is shifted down by one row. The data fedback from Test Register 318 is simultaneously available as readback data while it is fedback to Data register 314.
This process is repeated for each row thereby providing readback operation for each row of data latches. After the complete data has been readback, original configuration data is restored in their respective latches and the multiplexer select line is reset low to restore normal operation.

We-claim:
1. A Programmable Logic Device (PLD) containing a configuration memory
providing readback of configuration data, comprising:
an input data selector having one input connected to a configuration
data source and another input connected to the output of the
configuration memory,
an input data register connected to the output of the input data
selector,
a matrix of data latches storing the configuration arranged in row and
column format with the final row of the matrix providing the output
from the configuration memory,
an interconnecting element capable of connecting the outputs from the
data latches of each row except the last row to the inputs of the data
latches of the next row, and
a row selector selectively enabling the interconnection of one or more
rows of the matrix of data latches when storing configuration data or
performing readback of configuration data.
2. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the
input data selector is a multiplexer.
3. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the
input data register is a shift register.
4. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the
interconnecting element is a switch.
5. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the row
selector is a selection register.
6. A Programmable Logic Device (PLD) as claimed in claim 1 including a test
register at the output of the configuration memory for enabling verification
of the connection between data latches in the data latch matrix.
7. A Programmable Gate Array (PGA) containing a configuration memory
providing readback of configuration data, comprising:
an input data register connected to the output of the input data selector,
a matrix of data latches storing the configuration arranged in row and column format with the final row of the matrix providing the output from the configuration memory,
an interconnecting element capable of connecting the outputs from the data latches of each row except the last row to the inputs of the data latches of the next row, and
a row selector selectively enabling the interconnection of one or more rows of the matrix of data latches when storing configuration data or performing readback of configuration data.
8. A Programmable Gate Array (PGA) as claimed in claim 7 wherein the input
data selector is a multiplexer.
9. A Programmable Gate Array (PGA) as claimed in claim 7 wherein the input
data register is a shift register.
10. A Programmable Gate Array (PGA) as claimed in claim 7 wherein the
interconnecting element is a switch.
11. A Programmable Gate Array (PGA) as claimed in claim 7 wherein the row
selector is a selection register.
12. A Programmable Gate Array (PGA) as claimed in claim 7 including a test
register at the output of the configuration memory for enabling verification
of the connection between data latches in the data latch matrix.
13. A method for enabling readback of configuration data stored in a
configuration memory constructed of a matrix of data storage elements
arranged in row and column format with the outputs from each row of data
latches except the last row selectably connected to the data inputs of the next
row and the last row providing the output from the configuration memory,
comprising the steps of:
selecting the input data source of the configuration memory as either the configuration data source during normal mode or the data from the output of the configuration memory during readback mode, registering the data from the selected input data source, sequentially enabling the interconnection of one or more rows of the configuration data storage element matrix for storing the registered data in the desired row,
providing the data from the output of the configuration memory as the readback data during readback mode, and
repeating the sequence of receiving and storing input data and sequentially enabling rows of the configuration memory, until the entire data has been written into the configuration memory.
14. A method as claimed in claim 13 wherein the selection of input data source
is achieved by multiplexing.
15. A Programmable Logic Device (PLD) containing a configuration memory
providing readback of configuration data substantially as herein described

with reference to the accompanying drawings.
16. A Programmable Gate Array (PGA) containing a configuration memory
providing readback of configuration data substantially as herein described
with reference to the accompanying drawings.
17. A Programmable Gate Array (PGA) containing a configuration memory
providing readback of configuration data substantially as herein described
with reference to the accompanying drawings.