PLDs PROVIDING REDUCED DELAYS IN CASCADE CHAIN CIRCUITS BACKGROUND OF THE INVENTION
1. Field Of The Invention:
This invention relates to Programmable Logic Devices providing reduced delays in cascade chain circuits,
2. Description Of The Prior Art:
Programmable Logic Devices (PLD) are general purpose logic devices that are configured to provide the functionality required for a particular application. The PLD is internally structured as multiple Configurable Logic Blocks (CLBs) each containing a Look-Up Table (LUT) that provides a configurable logic function. The CLBs are may be interconnected through programmable connection matrices that are provided between them. Multiple CLBs are interconnected to implement the desired logic functions. PLDs are often used in applications that require evaluation of functions involving a large number of inputs being processed in parallel. This requirement leads to the need for cascading of several CLBs, to provide the desired number of inputs and / or outputs. The intermediate outputs from each CLB are connected serially using gates to get the desired output. Use of the LUT to perform the desired logic function generally involves considerable propagation delay. Such delay is generally unacceptable for simple logic functions. To overcome the problem of delay most PLDs incorporate special "Cascade Logic" that facilitates the formation of a chain of logic providing minimal delays using special circuitry generally in the form of multiplexers or particular logic gates.
Figure-1 shows a generic Cascade Logic architecture. 2-input AND gates are included at the output of the LUT in each CLB. One input of the 2-input AND gate receives the output from the LUT while the second input forms the Cascade Logic input that is connected to the Cascade Logic Output from the previous CLB stage. This implementation is very inefficient for implementing Cascade Logic functions that are not simple AND gates. The delay in generating the final output is equal to the sum of the propagation delays of all the AND gates in the Cascade chain + the delay of the first LUT in the chain.

F^gure-2 shows the Cascade Chain implementation in Virtex II (reference: Data Sheet DS031 -J(vl.5) April 2, 2001) by Xilinx. MLJXCY 201 is used to implement AND, NAND, NOR, OR gate cascade chains. MUX 204 is used to select between signal BX and CASCADE_IN (which is also carry_in in Virtex II), for providing the input to the chain from the outside. Mux 203 is used to initialize the other input to MUXCY as either "0" or "1". LUTOUT is selected using Mux 302. MUXCY works as an AND, OR, NAND, NOR gate depending on the polarity of the inputs. This implementation does not have delay on the LUT output but the additional outputs for the LUT and for CASCADE_OUT increase the number of routing resources needed. This cascade logic is capable of implementing several logic functions including AND, OR, NOR, and NAND.
Figure 3 shows another example of cascade chain implementation in FPGAs (Used By Altera Inc. Ref APEX 20K Programmable Logic Device Family Data Sheet Ver. 3.7 May 2001). The output of LUT 301 and cascade input signal are logically ANDed by AND gate 302. The output of gate 302 is the LUT output. The Cascade chain output (if chain is terminated) as well as the cascade input for the next stage depending on the value of configuration bit PI. When the cascade chain is not used, configuration bit PI is set to "0" and the output of multiplexer 303 is "1" enabling AND gate 302 which passes the output of LUT 301 to LUT_OUT. When PI is set to "1" the output of LUT 301 and cascade input CASCADEJN are logically ANDed. The output of gate 302 is the final cascade chain output for the last stage of the chain and is the cascade input for next stage for the first and the intermediate stages. The same circuit can be used for other gate functions by applying Demorgan's Laws, inverting inputs to LUT where necessary and absorbing the final inverters in other LUT's or IO blocks where possible. This implementation reduces the number of output but introduces delay in LUT output path. The cascade circuitry is not very versatile and is difficult to use for implementing other 2-uiput functions.
SUMMARY OF THE INVENTION
The object of this invention is to facilitate the implementation of Cascade Logic functions with minimal delay from any input to output.
Another object of the invention is to provide the implementation of Cascade Logic functions requiring minimum area for implementation

to achieve these objectives the invention provides a Programmable Logic Device (PLD) incorporating a 2-input multiplexer providing the Cascade Logic output and having the Cascade Logic input coupled to its select line with a 2-input multiplexer providing the desired configurable Cascade Logic function, and an initialization circuit that sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer providing the Cascade Logic output also provides the desired configurable Cascade Logic function using the LUT and configuration bits. The initialization circuit is another 2-input multiplexer connected to one input or the select line of the output multiplexer, and providing selectable initialization based on the value of a configuration bit when initialization mode is enabled by another configuration bit. The LUT and a configuration bit provide any desired cascade logic function using the output 2-input multiplexer.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and advantages of the invention will become more apparent in reference to the following description and the accompanying drawings, wherein:
Fig. 1 shows schematic diagram of a typical cascade logic architecture.
Fig. 2 shows a prior art for cascade logic architecture according to Vertex II by Xilinx.
Fig. 3 shows another prior art for cascade logic architecture.
Fig. 4 shows the first embodiment of Cascade logic according to the present invention.
Fig. 5 shows the proposed invention incorporating initialization circuitry.
Fig. 6 shows another embodiment of the proposed invention for cascading of circuits.
Fig. 7 shows a modification of the second embodiment including an arrangement for sharing
the output between the cascade logic and normal LUT function.
DETAILED DESCRIPTION
The implementation of Figure-4 makes it possible for CASCADE_IN and LUT_OUT to be ANDed, ORed, NORed, NANDed together to give CASCADE_OUT depending on the programming bit PI. The input-output delay is the minimum possible as it corresponds only to the delay from the select input to the output of the 2-input MUX. This arrangement also minimizes the loading on the CASCADE_IN line a& the multiplexer select input offers the

minimum Capacitive loading. The minimal Capacitive loading further reduces the delay of the Cascade Logic stage as well as the power dissipation of the circuit. However this basic circuit requires some means of initialization. For initialization of the Cascade Logic CASCADE_OUT is required to be independent of CASCADE_EV. To achieve this it is necessary to initialize CASCADE_OUT to "0" or "1", after which the cascade chain can commence from the next LUT. To achieve this it is necessary to replicate either "0" or "1" on both the inputs of CACSCADE Mux at the time of initialization.
Figure-5 shows an circuit that provides initialization for the basic circuit of Figure-4.CASCADE_IN is routed thru an additional multiplexer havings its select input controlled by an additional configuration bit P2. Setting P2 to "1" allows CASCADEjOUT to be initialized to the desired value using configuration bit PI. CASCADE_OUT and LUT_OUT are a single output. However this arrangement loses some of the minimum delay advantage of the basic circuit as the initialization Mux adds an input-output propagation delay for the CASCADEJN signal.
Figure-6 shows an alternative circuit arrangement that provides initialization while retaining the minimal select-output delay of a Mux. The CASCADE_IN input is routed through an additional 2-input multiplexer that selects either configuration bit P2 or CASCADE_IN depending on the value of configuration bit PI. Configuration bit PI selects Cascade Logic operation when it is set to "1". Setting PI to "0" enables initialization based on the value of configuration bit P2.. When PI is "0" Cascade Logic operation is enabled while when PI is "1" normal LUT operation is enabled. In this arrangement setting Px to "0" replicates P2 on both the inputs of the Cascade logic Mux thus initializing CASCADE_OUT to either "0" or "l".Configuration bit P2 also operates in conjunction with LUTOUT to provide various possible logic functions. This arrangement however, requires separate output lines for normal and Cascade Logic operations, and hence requires a higher I/O count.
Figure-7 shows an arrangement for reducing the I/O count while retaining the advantage of minimal delay with built-in initialization circuitry. The arrangement uses 2 muxes (701 and 702) for cascade chain implementation. A third Mux 703 is added for tapping either LUTOUT or CASCADEOUT as the final output. CASCADEOUT can be initialized as "1" or "0" for the cascade chain starting from the next LUT. When the programmable bit PI is set to "0" then the Cascade circuitry is in initializing mode depending on P2. When PI is set to

"1" then cascade circuitry is in cascade mode and LUTOUT is selected as input to mux 702. "'The normal working mode of LUT requires PI to be "0". In this mode the cirucit can either initialize the cascade chain starting from next LE or keep the cascade circuitry in non switching mode. If P2 is set to "0", then the cascade circuitry works like an effective AND chain with initial cascade input equal to "0". Thus the cascade circuitry does not unnecessarily switch and power is not wasted.
The delay from CASCADE_EV to CASCADE_OUT is the minimal possible, as the CASCADE_IN signal is the select pin of the multiplexer where the load is less than the driving pin of the multiplexer. This implementation does not require buffers to improve signal integrity as the CASCADE_OUT output is driven by lightly loaded signals. Thus the circuitry is performance efficient. The circuitry is flexible enough to implement many 2-input function besides AND, OR, NOR, NAND gates. Minimal number of components makes the circuitry area efficient. The detailed functionality is shown in two tables below:
TRUTH TABLE

(Table Removed)
FUNCTIONALITY

(Table Removed)
It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the above invention.
Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.

WHAT IS CLAIMED IS:
1. A Programmable Logic Device (PLD) configurable for providing minimal delay and minimal circuit area for Cascade logic functions in addition to normal Look Up Table (LUT) based configurable logic' functions, comprising a plurality of Configurable Logic Blocks (CLB) incorporating:
a 2-input multiplexer providing the Cascade Logic output and having the
Cascade Logic input coupled to its select line and,
a 2-input multiplexer providing the desired configurable Cascade Logic
function, and
an initialization circuit that sets the initial value for the Cascade logic under
control of an initialization configuration bit.
2. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the multiplexer
providing the Cascade Logic output also provides the desired configurable Cascade
Logic function using the LUT and configuration bits.
3. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the initialization
circuit is another 2-input multiplexer connected to one input or the select line of the
output multiplexer, and providing selectable initialization based on the value of a
configuration bit when initialization mode is enabled by another configuration bit.
4. A Programmable Logic Device (PLD) as claimed in claim 1 wherein the LUT and a
configuration bit provide any desired cascade logic function using the output 2-input
multiplexer.
5. A Programmable Logic Device (PLD) as claimed in claim 4 wherein the configurable
Cascade logic functions include AND, OR, NOR and NAND functions.
6. A Programmable Gate Array (PGA) configurable for providing minimal delay and
minimal circuit area for Cascade logic functions in addition to normal Look Up Table
(LUT) based configurable logic functions, comprising a plurality of Configurable
Logic Blocks (CLB) incorporating :

a 2-input multiplexer providing the Cascade Logic output and having the
Cascade Logic input coupled to its select line and,
a 2-input multiplexer providing the desired configurable Cascade Logic
function, and
an initialization circuit that sets the initial value for the Cascade logic under
control of an initialization configuration bit.
7. A Programmable Gate Array (PGA) as claimed in claim 1 wherein the multiplexer
providing the Cascade Logic output also provides the desired configurable Cascade
Logic function using the LUT and configuration bits.
8. A Programmable Gate Array (PGA) as claimed in claim 1 wherein the initialization
circuit is another 2-input multiplexer connected to one input or the select line of the
output multiplexer, and providing selectable initialization based on the value of a
configuration bit when initialization mode is enabled by another configuration bit.
9. A Programmable Gate Array (PGA) as claimed in claim 1 wherein the LUT and a
configuration bit provide any desired cascade logic function using the output 2-input
multiplexer.
10. A Programmable Gate Array (PGA) as claimed in claim 4 wherein the configurable
Cascade logic functions include AND, OR, NOR and NAND functions.
11. A method for providing minimal delay and minimal circuit area for Cascade logic
functions in a Programmable Logic Device (PLD), comprising the steps of:
configuring a desired cascade logic function using a 2-input multiplexer at the output of the LUT, in conjunction with a configuration bit, receiving the Cascade Logic input at the select input of the multiplexer to provide minimal loading and delay for the cascade logic function, and initializing the inputs for the Cascade logic using an initialization configuration bit that sets the Cascade Output to the desired value.
12. A Programmable Logic Device (PLD) configurable for providing minimal delay and
minimal circuit area for Cascade logic functions in addition to normal Look Up Table

» (LUT) based configurable logic functions substantially as herein described with reference to and as illustrated in figures 4 to 7 of the accompanying drawings.
13. A Programmable Gate Array (PGA) configurable for providing minimal delay and
minimal circuit area for Cascade logic functions in addition to normal Look Up Table
(LUT) based configurable logic functions substantially as herein described with
reference to and as illustrated in figures 4 to 7 of the accompanying drawings.
14. A method for providing minimal delay and minimal circuit area for Cascade logic
functions in a Programmable Logic Device (PLD) substantially as herein described
with reference to and as illustrated in figures 4 to 7 of the accompanying drawings.