Claims:1. An apparatus, comprising:
a hardware accelerator to perform a three-dimensional (3D) point cloud data access operation; and
first circuitry coupled to the hardware accelerator to control the hardware accelerator to perform the 3D point cloud data access operation in response to a request.
, Description:BACKGROUND
1. Technical Field
[0001] This disclosure generally relates to accelerator technology, and more particularly to an instruction set for a hardware accelerator.
2. Background Art
[0002] Understanding three-dimensional (3D) geometry and semantics of a scene is essential to many real-world systems including but not limited to autonomous driving, robotics, remote sensing, augmented reality (AR)/virtual reality (VR), medical treatment, etc. Also, advancements in 3D sensing technologies, such as radar, light detection and ranging (LiDAR), depth cameras, etc., enable high-quality 3D data generation at affordable cost and in desirable form-factors. 3D data is usually represented in various formats such as point clouds, meshes, depth maps and volumetric grids. Deep learning (DL) techniques have found application in domains such as computer vision, speech processing and machine translation that operate over images, videos, audio, text and other forms of data.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
[0004] FIG. 1 is a block diagram of an example of an apparatus according to an embodiment;
[0005] FIG. 2 is a block diagram of another example of an apparatus according to an embodiment;
[0006] FIG. 3 is a block diagram of an example of a hardware accelerator according to an embodiment;
[0007] FIG. 4 is a block diagram of an example of a voxel storage structure according to an embodiment;
[0008] FIG. 5A is a block diagram of an example of a memory data layout according to an embodiment;
[0009] FIG. 5B is a block diagram of an example of a data buffer arrangement according to an embodiment;
[0010] FIG. 6 is a block diagram of an example of hardware according to an embodiment;
[0011] FIGs. 7A to 7B are flow diagrams of an example of a method according to an embodiment;
[0012] FIGs. 7C to 7D are flow diagrams of another example of a method according to an embodiment;
[0013] FIG. 8A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention;
[0014] FIG. 8B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention;
[0015] FIGs. 9A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip;
[0016] FIG. 10 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention;
[0017] FIGs. 11-14 are block diagrams of exemplary computer architectures; and
[0018] FIG. 15 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.

DETAILED DESCRIPTION
[0019] Embodiments discussed herein variously provide techniques and mechanisms for a microarchitecture and instruction set for point cloud adjacency-map and hash-map creation. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including integrated circuitry which is operable to provide a point cloud adjacency-map and hash-map creation accelerator. Example applications for embodiments include drones, autonomous driving, AR/VR headsets, etc.