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I
f AN IMPROVED THIN FILM TRANSISTOR HAVING REDUCED OFFSTATE
LEAKAGE CURRENT
Field of the Invention
The instant invention relates to an improved thin film transistor having reduced offstate
leakage current
Background of the Invention
Poly-Silicon Thin Film Transistors {TFTs) have been studied extensively in recent
years for their application in flat panel Active Matrix Liquid Crystal Displays
(AMLCD). In the articles "An LCD addressed by a-Si:H TFTs with peripheral poly-Si
TFT circuits" by T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, and N. Konishi &
"Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels
with peripheral driver circuit integration" by T. Aoyama, K. Ogawa, Y. Mochizuki,
and N. Konishi, Poly-Silicon thin film transistors have been elaborated. For certain
applications scaled-down poly-Si TFTs with high performance and high reliability are
required. One application using poly-Si TFT is described in "High performance polySi
TFTs on a glass by a stable scanning CW laser lateral crystallization" by A. Hara,
Y. Mishima, T. Kakehi, F. Takeuchi, M. Takei, K. Yoshino, K. Suga, M. Chida, and
N. Sasaki. One of the problems of poly-Si TFT is the large OFF state leakage current
due to the presence of the grain boundaries in the channel resulting in poor switching
characteristics. Various solutions such as the offset gate, the p-n-p gate and Lightly
Doped Drain (LDD) poly-Si TFT structures have been proposed to reduce the OFF
state leakage currents.
In keeping with the general trends of the CMOS technology, the channel lengths of
the poly-Si TFTs are now aggressively scaled down to sub-micron lengths. Also, by
scaling the channel of the device down to a length comparable to the poly-Si grain
size, using modem Metal-Induced Lateral Crystallization (MILC) or Excimer Laser
Annealed (ELA) methods to control the grain growth, it is possible to create devices
where only a single or small number of discrete grain boundaries exist in the channel
1
of the poly-Si TFT. This ability to control the grain size to form the well-arranged
grains in the channel has resulted in high performance poly-Si TFTs typically with
one or fewer grain boundaries in the channel. However, the off-state leakage currents
in these advanced poly-Si TFTs are orders of magnitude larger than those observed in
conventional single-crystal SOl MOSFETs.
The conventional SOl MOSFET exhibits a steep sub-threshold slope and a clear tumon
region in its transfer characteristic. The dominant conduction mechanism is due to
the Inversion Charge Density Modulated By The Gate (ICMG). On the other hand,
there are two regions in the transfer characteristic of a poly-Si TFT as shown in Fig.l.
The region below threshold and the tum-on condition (V condition (Vt) is called the
sub-threshold region and the region between Vt ON) is called the pseudo-sub-threshold
region. Unlike in the case of SOl MOSFETs, in which the log (10
)-Vas curve is very
sharp and quickly becomes linear, in the case of poly-TFTs, the transition from the
exponential to the linear region is much more gradual. The dominant conduction
mechanism below the tum-on region (VON) is due to the Gate-Induced Grain Barrier
Lowering (GIGBL) and is not controlled by the Accumulation Charge Density
Modulation by the gate (ACMG).
The instant invention therefore converts the dominant conduction mechanism in a
poly-Si TFT with fewer grain boundaries, from gate-induced grain barrier lowering to
accumulation charge density modulation by the gate so that the pseudo-sub-threshold
region is significantly diminished in the transfer characteristic. One and three grain
boundaries in the channel of the poly-Si TFT are considered. The poly-Si TFT
behaves almost like the conventional single-crystal SOl MOSFET with a steep subthreshold
slope resulting in a significant reduction in the OFF state leakage current.
2
Object and Summary of the Invention
To obviate the aforesaid drawbacks, the object of the instant invention is to provide a
novel Triple Gate poly-Si TFT (TG-TFT) in which the front gate consists of two side
gates on both sides of the main gate.
Another object of the invention is to provide dominant conduction mechanism based
upon accumulation charge density modulation by the gate to enable pseudo-subthreshold
region to be significantly reduced in the transfer characteristic.
To achieve said objects, the instant invention provides an improved thin film transistor
having reduced off-state leakage current comprising:
a source region;
a drain region;
a channel connecting said source region and said drain region; and
a gate region formed on said channel;
characterized in that said gate region comprises
a main gate; and
two or more side gates connected to said main gate for controlling the
dominant conduction mechanism of said thin film transistor based upon
accumulation charge density modulation by the gate.
In another aspect of the invention, a method of manufacturing an improved thin film
transistor having reduced off-state leakage current is provided comprising the steps of:
providing source and drain regions;
providing a channel connecting said source region and said drain region; and
providing a gate region characterized in that
providing main gate and two or more side gates in said gate region for controlling the
dominant conduction mechanism of said thin film transistor based upon accumulation
charge density modulation by the gate.
3
The work function of the side gates is different as compared to the main gate that
results in a modified channel potential. Using two-dimensional simulation "MEDICI
4.0, Technology Modeling Associates, Palo Alto, CA, 1997", the instant invention
leads to highly diminished pseudo-sub-threshold region in the transfer characteristics
of the TG-TFT resulting in a significantly reduced OFF state leakage current
compared to the conventional poly-Si TFT (C-TFT). The effects of varying the side
gate parameters, trap density at the grain boundaries, the number of grain boundaries
in the channel and temperature of the device are investigated. The proposed TG-TFT
exhibits significantly reduced leakage current thus making it a more reliable device
configuration than the C-TFT for high performance poly-Si TFT circuit applications.
Brief Description of the Accompanying Drawings
Figure 1 shows typical transfer characteristic of a conventional poly-Si TFT operated
in linear region.
Figure 2 shows the cross-sectional vtew of the TG-TFT m accordance with the
invention.
Figure 3 shows conduction band potential distribution for a) C-TFT (VGS = 0 V), b)
TG-TFT (VGS= 0 V), and c) TG-TFT (VGS= 0.52 V) with VDS= 0 V.
Figure 4 shows a comparison of the transfer characteristics of TG-TFT, C-TFT, and
C-SOI structures.
Figure 5 shows transfer characteristic of TG-TFT structure for different work
functions of side gates.
Figure 6 shows transfer characteristics of TG-TFT and C-TFT for different channel
lengths.
4
Figure 7 shows transfer characteristics of TG-TFT and C-TFT for different grain
boundary trap densities.
Figure 8 shows transfer characteristics of TG-TFT and C-TFT for different
temperatures.
Figure 9 shows transfer characteristics of TG-TFT for different side gate lengths. LM
and LS are the main and side gate lengths, respectively.
Figure 10 shows transfer characteristics of TG-TFT and C-TFT for three gram
boundaries in the channel with all three grain boundaries present under the main gate.
Figure 11 shows transfer characteristics of TG-TFT and C-TFT for three grain
boundaries in the channel with one grain boundary present under each side gate.
Detailed Description of the Invention
In relation to the drawings, exemplary embodiments of the present invention are
described in the following detailed description. However, it will be apparent to a
person skilled in the art that numerous other equivalent embodiments or ways of
practicing the present invention exist.
Fig.2 shows a schematic cross-sectional view of the TG-TFT implemented in the 2-D
+ +
device simulator MEDICI. The gate region consists of p -poly-Si 20 & 21 and n -
poly-Si 22 for the side gates and the main gate, respectively. The channel 24 of the
device is undoped poly-Si with a single Grain Boundary (GB) 23 in the center. The
regions on both sides of grain boundary are assumed to be completely defect-free
meaning all the defect states are localized in the grain boundary. The capture and
emission processes are handled by the simulator using Shockley-Read-Hall
recombination model and a conventional drift-diffusion method is used to model the
carrier transport. Also, the Caughey-Thomas model is employed for the mobility
based on the work of Kitahara, Takagi, and N. Sano, "Statistical study of sub-
5
threshold characteristics in polycrystalline silicon thin-film transistors," J. Appl.
Phys., vol. 94, pp. 7789-7795, Dec. 2003. The aforesaid models & method are
exemplary and other relevant models can be used.
+ 19 ~
The doping in the n source/drain regions 25 & 26 is kept at 1 x 10 em . The effective
13 -2
trapping density at the grain boundary 23 is taken to be 1 x 1 0 em and the trap
energy relative to the conduction and valence bands are 0.51 eV and 0.51 eV for
electron and hole traps, respectively. The capture rate for electrons and holes are
-8 3
identical and equal to 1 x 10 em /sec. It is assumed that the trap density of the
acceptor-like states and donor-like states are identical. The donor-like state is defined
as a trap state that is positively charged when holes are captured and the acceptor-like
state is negatively charged when electrons are captured. The width of the grain
boundary 23 (i.e. distance between the two grains) is 10 nm. The Silicon thin film and
the gate oxide thickness are 50 and 10 nm, respectively. The main gate and the side
gate lengths (LM and L8
) are identical and the channel length L (=2L8 +LM) is kept
+ +
constant at 0.4 p,m in the simulations. The work functions of the p -poly and the n -
poly gates are chosen as 5.25 eV and 4.17 eV, respectively. All the device parameters
of the TG-TFT are equivalent to those of the C-TFT unless mentioned. However the
invention aforesaid values of main gate and the side gate lengths and the work
function are exemplary and a person skilled in the art can vary the values as per the
requirement.
The polarity between source and drain in poly-Si TFTs in AMLCD applications is
required to be altered to reduce the DC stress of liquid crystals. Therefore, for such
applications it is advantageous to have a symmetrical Poly-Si TFT structure by having
identical side gates on both sides of the main gate as suggested in the proposed TGTFT.
In other applications asymmetrical Poly-Si TFT structure can be used.
Modifying Channel Potential Distribution:
6
TG-TFT operation modifies the channel potential so that the channel conduction is
controlled by the ACMG and not by GIGBL. A typical MEDICI simulated 2-D
conduction band potential distribution for TG-TFT and C-TFT structures for the drain
to source voltage V ns = 0 V is shown in Fig. 3. It can be seen from Fig. 3(a) that a
potential barrier (central barrier 29) is formed at the grain boundary 23 because the
carriers are immobilized by the traps due to the strain and the dangling bonds located
at the grain boundary. Therefore, the dominant conduction mechanism of the C-TFT is
determined by GIGBL.
But, in the proposed TG-TFT due to its triple-gate structure, in addition to the central
barrier 32, two extra barriers (side barriers 30 & 31) are created in the side gate
regions 20 & 21 due to the work function difference between the side gate 20 or 21
and the main gate 22 as shown in Fig. 3(b) in which the side and central barriers 30,
31 & 32 respectively not only differ in their height but also in their shape. Therefore,
the dominant conduction mechanism of the TG-TFT is controlled by the side barriers
30 & 31 since the central barrier 32 does not play any significant role. In that case, a
steep sub-threshold slope in the transfer characteristic of the device is observed as in a
typical single crystal SOl MOSFET. With increasing gate voltage, however, the height
of the side barrier decreases and at some critical gate voltage (V cos), the side barrier
height becomes equal to the central barrier height as shown in Fig. 3 (c) for Vas= 0.52
V. After this critical gate voltage (V cos) condition is reached, the channel conduction
mechanism is determined by GIGBL.
Diminished Pseudo-Sub-threshold Region:
In Fig. 4, the transfer characteristics of the TG-TFT are compared with that of the CTFT
and the single crystal SOl MOSFET. As speculated above, for all gate voltages
less than the critical gate voltage V cos(= 0.52 V), the sub-threshold slope of the TGTFT
is very steep similar to that commonly observed in SOl MOSFETs. For gate
voltages greater than V cos' the transfer characteristic of the TG-TFT matches with
7
that of the C-TFT as the height of the central barrier 33 is larger than that of the side
barriers 34 & 35. Thus because of the steep sub-threshold slope, the TG-TFT has
several orders of magnitude lesser off-state leakage current when compared to the CTFT.
This has become possible by nullifying the effect of the central barrier
associated with the grain boundary on the channel conduction mechanism so that the
pseudo-sub-threshold region is almost eliminated.
Effect of Side Gate Work Function on Yeas:
The value of critical gate voltage V cas at which the central barrier height becomes
equal to the side barrier height is very important in controlling the pseudo-subthreshold
region and hence the reduction in the off-state leakage current. If the critical
gate voltage V cas is near to zero or negative, the TG-TFT structure is not very useful
in improving leakage current and will behave like the C-TFT. An important parameter
that determines the value of V cas is the work function of the side gate.
Fig.5 shows the transfer characteristic of the TG-TFT for different work functions of
the side gate region. It can be seen from the figure that as the work function of the side
gate decreases, the critical gate voltage V cas reduces forcing the behavior of TG-TFT
device to be similar to the C-TFT. This is because if the work function of the side gate
decreases for a given work function of the main gate, the height of the side barriers
will also decrease. Therefore, it is very important to choose appropriate work function
fot the side gate for given main gate work function.
Effect of Channel Length:
Fig. 6 shows the transfer characteristics of the TG-TFT compared with that of the CTFT
for channel lengths ranging from 0.3 J.Lm to 1.0 J.Lm. Just as is commonly
observed in the case ofthe single crystal SOI-MOSFET, the slope of the sub-threshold
region improves as the channel length increases. There is no significant change in the
8
critical voltage V cos with increase in the channel length because the interaction
between side and central barriers reduces as the channel length increases.
Effect of Trap Density:
The conductivity in polycrystalline TFT is strongly dependent on the trap density at
the grain boundaries and has been described in many publications. A publication by
G. Baccarani, B. Ricco, and G. Spadini, "Transport properties of polycrystalline
silicon films," describes the same. Fig. 7 shows the transfer characteristics of TG-TFT
and C-TFT structures for different trap densities. It can be seen from the figure that
the pseudo-sub-threshold region is more gradual with increasing trap density at the
grain boundary and V cas· However, the sub-threshold slope of the TG-TFT remains
unchanged giving rise to a substantial reduction in the off-state current even if the trap
density is large.
Effect of Temperature:
One of the important concerns in the operation of poly-Si TFTs is the dependence of
its performance on temperature. Due to the gradual sub-threshold slope, the C-TFTs
show stronger temperature dependence compared to the conventional SOl MOSFETs.
Fig. 8 shows the temperature dependence of the TG-TFT and the C-TFT structures.
Even at 400 K, the off-state current of the TG-TFT is much smaller and the subthreshold
slope is steeper than that of the C-TFT. This is an important advantage of
the TG-TFT over that of the C-TFT at higher ambient temperatures.
Generally it is difficult to control the position of the grain boundary relative to the
source and drain in a device and therefore the position dependence of the grain
boundary in the channel is very important in conventional poly-Si TFTs. However, the
simulation results suggest that there is no significant change in the transfer
characteristic of TG-TFT even if there is a 20 percent shift in the position of the grain
boundary with respect to the center of the channel.
9
DESIGN ISSUES OF TG-TFT
Choice of Side Gate Length:
In all the simulations above, the main gate length LM is equal to the side gate length Ls
for the Dual Material Gate (DMG) SOl MOSFET. To examine the effect of the side
gate length on the leakage current, the transfer characteristic of the TG-TFT for
different side gate lengths are compared as shown in Fig. 9. As can be seen from the
figure, there is no significant change in the critical gate voltage V cas when the side
gate length is reduced with respect to the main gate length. However, it can be
concluded that the sub-threshold slope is steeper and the leakage current is the lowest
when the side gate length is equal to the main gate length for the fixed channel length.
Effect of Multiple Grain Boundaries:
To examine the behavior of the TG-TFT in the presence of multiple grain boundaries
in the channel, the performance of the TG-TFT structure with three-grain boundaries
in the channel is investigated. Fig. 10 shows a comparison of the transfer
characteristic of the TG-TFT with the C-TFT with three-grain boundaries present in
the main channel and for different distances between these grains. The graph
illustrates that the TG-TFT structure works very well even in the presence of multiple
grain boundaries in the channel. When the distance between the grain boundaries is
large, due to an increase in the interaction between the side barriers and the trap
barriers, the slope of transfer characteristic of the TG-TFT increases. However, even
in this case, the transfer characteristic of the TG-TFT is significantly better than that
of the C-TFT. Further in the presence of multiple grain boundaries in the channel, the
pseudo-sub-threshold slope in the C-TFT further deteriorates.
For the chosen Ls and LM values, if the distance between grain boundaries further
increases, it is quite possible that grain boundaries may appear under the side gates as
shown in Fig. 11. Even in this case, it is observed that by choosing appropriate Ls and
10
LM values, diminished pseudo-sub-threshold region in the TG-TFT making its subthreshold
slope very steep can be realized as supported by the transfer characteristic
shown in Fig. 11.
Thus it is concluded that to reduce the leakage current and for improving the
performance of poly-Si TFT in AMLCD or other applications, a novel Triple-Gate
poly-Si TFT (TG-TFT) is proposed. In this structure, two side gates on either side of
the main gate whose work functions are different from the main gate are used so that
the dominant conduction mechanism in the channel is controlled by the accumulation
charge density modulation by the gate (ACMG) and not by the gate-induced grain
barrier lowering (GIGBL). The performance of the proposed TG-TFT has been
evaluated using two-dimensional simulation and compared with that of a conventional
poly-Si TFT. Based on the simulation results, due to the presence of side barriers
which are more dominant than the central potential barrier associated with the grain
boundaries, the pseudo-sub-threshold region is significantly diminished resulting in
several orders of magnitude reduction in the OFF state leakage current with no
detectable change in the ON voltage. The different aspects of the device design such
as the effect of varying the channel length, number of grain boundaries, trap density at
the grain boundaries, temperature and the work function of the gate material, and the
reasons for the improved performance are proposed. The significantly reduced leakage
current in the TG-TFT due to the diminished pseudo-sub-threshold region is expected
to provide the incentive for experimental verification.
Any variations in the parameters, different relationship of the main gate length and
side gate length and formation of multiple gates TFT fall within the spirit of the
invention.

We claim:
1. An improved thin film transistor having reduced off-state leakage current
comprising:
a source region;
a drain region;
a channel connecting said source region and said drain region; and
a gate region formed on said channel;
characterized in that said gate region comprises
a main gate; and
two or more side gates connected to said main gate for controlling the
dominant conduction mechanism of said thin film transistor based upon
accumulation charge density modulation by the gate.
2. The thin film transistor as claimed in claim 1 wherein said channel comprises
of a single grain boundary.
3. The thin film transistor as claimed in claim 1 wherein said channel comprises
of multiple grain boundaries.
4. The thin film transistor as claimed in claim 1 wherein the work function of said
side gates is different from the work function of the main gate.
5. The thin film transistor as claimed in claim 1 wherein said thin film transistor is
a poly Silicon thin film transistor.
6. The thin film transistor as claimed in claim 1 wherein said channel is made of
undoped poly-Si.
7. The thin film transistor as claimed in claim 1 wherein said side gates are made
+
of p -poly-Si.
12
8. The thin film transistor as claimed in claim 1 wherein said main gate is made of
+
n -poly-Si.
9. The thin film transistor as claimed in claim 1 wherein the total length of said
side gates is equal to the length of said main gate for a fixed channel length.
10. A method of manufacturing an improved thin film transistor having reduced
off-state leakage current comprising the steps of:
providing source and drain regions;
providing a channel connecting said source region and said drain region;
and
providing a gate region characterized in that
providing main gate and two or more side gates in said gate regiOn for
controlling the dominant conduction mechanism of said thin film transistor
based upon accumulation charge density modulation by the gate.