Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/480,536 filed on 21 September 2021 and titled “POST-QUANTUM SECURE LIGHTEIGHT INTEGRITY AND REPLAY PROTECTION FOR MULTI-DIE CONNECTIONS” the entire disclosure of which is hereby incorporated by reference.

BACKGROUND OF THE DESCRIPTION
[0002] Semiconductor devices are increasingly being manufactured in the form of a package which includes multiple different integrated circuits disposed on multiple dies that are communicatively coupled by an interconnect structure. Signal transmission on the interconnect structure may present a security risk for such semiconductor package devices.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope, for this disclosure may admit to other equally effective embodiments.
[0004] Fig. 1 is a schematic illustration of a semiconductor device, according to embodiments.
[0005] Fig. 2 is a schematic illustration of a semiconductor device, according to embodiments.
[0006] Fig. 3 is a schematic illustration of components of an integrity and replay protection circuitry, according to embodiments.
[0007] Fig. 4 is a schematic illustration of a cryptographic permutation, according to embodiments.
[0008] Fig. 5 is a flowchart illustrating operations in a method to implement integrity and replay protection, according to embodiments.
[0009] Fig. 6 is a flowchart illustrating operations in a method to implement integrity and replay protection, according to embodiments.
[0010] Figs. 7A-7B are schematic illustrations of a cryptographic permutation, according to embodiments.
[0011] Figs. 8A-8B are schematic illustrations of a cryptographic permutation, according to embodiments.
[0012] Fig. 9 is a chart illustrating various design options of an integrity and replay protection circuitry, according to embodiments.
[0013] Fig. 10 is a schematic illustration of an electronic device which may be adapted to implement integrity and replay protection circuitry, according to embodiments.

DETAILED DESCRIPTION
[0014] In the following description, numerous specific details are set forth to provide a more thorough understanding of various embodiments. However, it will be apparent to one of skill in the art that various embodiments may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring any of the embodiments.
, Claims:1. An apparatus comprising:
a first die comprising a first integrated circuit;
a second die comprising a second integrated circuit;
an interconnect to provide a communication connection between the first die and the second die;
the first die comprising a processing circuitry to:
generate a first message authentication code (MAC) tag using a first message data to be communicated from the first die to the second die and a first cryptographic key; and
transmit the first message data and the first MAC tag to the second die via the interconnect.