1. A computing device with power aware packet distribution, comprising:
a central processing unit (CPU) comprising a plurality of cores; and
an interface controller communicatively coupled to the CPU, the
interface controller to:
receive a data packet to be sent to a targeted core of the plurality of cores;
identify a power state of the targeted core; and
redirect the data packet to an alternate core based on the power state of the targeted core.
2. The computing device of claim 1, wherein the interface controller comprises a power state configuration table, wherein information to be stored to the power state configuration table identifies power states of each of the plurality of cores.
3. The computing device of claim 2, wherein the information in the power state configuration table is maintained by the CPU.
4. The computing device of claim 2, wherein the interface controller comprises a flow redirector that identifies the power state of the targeted core by accessing the power state configuration table.
5. The computing device of claim 2, wherein the power state configuration table identifies the alternate core that can accept the data packet.
6. The computing device of any one of claims 1 to 5, wherein the targeted core is associated with a targeted queue, wherein to redirect the data packet to an alternate core based on the power state, the interface controller is to identify a first

alternate queue associated with the targeted queue and a second alternate queue associated with the targeted queue.
7. The computing device of claim 6, wherein the interface controller is to send the data packet to the first alternate queue or the second alternate queue depending, at least in part, on a first power state associated with the first alternate queue.
8. The computing device of claim 6, wherein the interface controller comprises:
a flow controller that identifies the targeted queue based on information contained in the data packet; and
a flow redirector that identifies alternate queues associated with the targeted queue.
9. The computing device of any one of claims 1 to 5, wherein the power
state is a P state.
10. The computing device of any one of claims 1 to 5, wherein the power
state is a C state.
11. An interface controller with power aware packet distribution comprising
logic to:
receive a data packet to be sent to a targeted core of a plurality of
cores of a central processing unit (CPU);
identify a power state of the targeted core; and
redirect the data packet to an alternate core of the plurality of cores
based on the power state of the targeted core.

12. The interface controller of claim 11, comprising a power state configuration table, wherein information to be stored to the power state configuration table identifies power states of each of the plurality of cores.
13. The interface controller of claim 12, wherein the information in the power state configuration table is maintained by the CPU.
14. The interface controller of claim 12, comprising a flow redirector that identifies the power state of the targeted core by accessing the power state configuration table.
15. A method of distributing packets to cores of a central processing unit (CPU) based in part on the power states of the cores, comprising:
receiving a data packet to be sent to a targeted queue, wherein the targeted queue is associated with two or more alternate queues, and wherein each of the two or more alternate queues is associated with a core of a central processing unit (CPU);
identifying the two or more alternate queues;
identifying a power state of the core associated with each alternative queue;and
sending the data packet to one of the two or more alternate queues based on the power states.
16. The method of claim 15, wherein identifying the power state of the core associated with each alternative queue comprises looking up the power state in a power state configuration table maintained by the CPU.
17. The method of and one of claims 15 to 16, wherein sending the data packet to one of the two or more alternate queues based on the power states comprises sending the data packet to the alternate queue that is not in a power saving state.

18. A non-transitory computer-readable medium comprising instructions
that, when executed by a processor, distribute packets to cores of a central
processing unit (CPU) based in part on the power states of the cores, the
instructions to direct the processor to:
receive a data packet to be sent to a targeted queue, wherein the targeted queue is associated with two or more alternate queues, and wherein each of the two or more alternate queues is associated with a core of a central processing unit (CPU);
identify the two or more alternate queues;
identify a power state of the core associated with each alternative queue;and
send the data packet to one of the two or more alternate queues based on the power states.
19. The computer-readable medium of claim 18, wherein the instructions to identify the power state of the core associated with each alternative queue comprise instructions that direct the processor to look up the power state in a power state configuration table maintained by the CPU.
20. The computer-readable medium of claim 19, wherein the instructions to identify the two or more alternate queues comprise instructions that direct the processor to look up the targeted queue in the power state configuration table.
21. The computer-readable medium of any one of claims 18 to 20, wherein the instructions to send the data packet to one of the two or more alternate queues based on the power states comprises instructions to send the data packet to the alternate queue that is not in a power saving state.
22. An apparatus with power aware packet distribution, comprising:

means for receiving a data packet to be sent to a targeted queue, wherein the targeted queue is associated with two or more alternate queues, and wherein each of the two or more alternate queues is associated with a core of a central processing unit (CPU);
means for identifying the two or more alternate queues;
means for identifying a power state of the core associated with each alternative queue; and
means for sending the data packet to one of the two or more alternate queues based on the power states.
23. The apparatus of claim 22, wherein the means for identifying the power state of the core associated with each alternative queue comprises means for looking up the power state in a power state configuration table maintained by the CPU.
24. The apparatus of any one of claims 22 to 23, wherein the power state is a P state.
25. The apparatus of any one of claims 22 to 23, wherein the power state
is a C state.