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Power Control Of A Memory Device In Connected Standby State

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
18 November 2021
Publication Number
25/2022
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
ipo@iphorizons.com
Parent Application

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California 95054, USA

Inventors

1. AISWARYA M. PIOUS
B.M. Ramayya Reddy Building # 135/20/11, 11th Cross, Bangalore, Karnataka 560103 India
2. RAJI JAMES
104, GM Reddy's Royale Apt Bangalore, Karnataka 560103 India
3. PHANI K. ALAPARTHI
#8, 2nd Flr, Peekayam Layout, Hosaplaya, Bommanhalli, Bangalore, Karnataka 560068 India
4. GEORGE VERGIS
2420 NW Birkendene Street Portland, OR 97229 USA
5. BILL NALE
370 Fontonett Avenue Livermore, CA 94550 USA
6. KONIKA GANGULY
3698 Lansbrook Terrace Portland, OR 97229 USA

Specification

Claims:1. An apparatus comprising:
a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller;
a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU), wherein:
the second power rail is separate from the first power rail,
during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and
during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
, Description:DESCRIPTION
[0002] Microprocessors and central processing units (CPUs) are increasing in transistor density and frequency of operation. Computer designers and manufacturers are faced with corresponding increases in power and energy consumption. Particularly in mobile devices, such as laptop computers, wireless handsets, smart phones, smart watches, tablet computers, etc., increased power consumption can lead to overheating or reduce battery life. Because batteries typically have a limited capacity, running the processor of a mobile device more than necessary could drain the capacity more quickly than desired.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 depicts an example system.
[0004] FIG. 2 depicts an example system.
[0005] FIGs. 3A and 3B depict example systems
[0006] FIGs. 4A and 4B depict example systems
[0007] FIG. 5 depicts an example process.
[0008] FIG. 6 depicts a system.
[0009] FIG. 7 depicts an example environment.

DETAILED DESCRIPTION
[0010] To manage power consumption, today's high end CPUs have two distinct power-down modes, e.g., C-states and S-states. In C-states the CPU is put into sleep mode while maintaining context and appearing architecturally active to the system, also referred to as an idle state. In S-states the CPU is powered off and a boot process is required to restart it. Operating systems typically support a built-in power management software interface such as Advanced Configuration and Power Interface (ACPI) an open industry specification standard first published in 1996, in which the CPU is placed into lower power sleep states based on reduced activity or demand. Among other aspects, the ACPI defines the lower power sleep states as a progression of C-states that can be supported by processors and/or chipsets.

Documents

Application Documents

# Name Date
1 202144053149-FORM 1 [18-11-2021(online)].pdf 2021-11-18
2 202144053149-DRAWINGS [18-11-2021(online)].pdf 2021-11-18
3 202144053149-DECLARATION OF INVENTORSHIP (FORM 5) [18-11-2021(online)].pdf 2021-11-18
4 202144053149-COMPLETE SPECIFICATION [18-11-2021(online)].pdf 2021-11-18
5 202144053149-FORM-26 [18-02-2022(online)].pdf 2022-02-18
6 202144053149-FORM 3 [18-05-2022(online)].pdf 2022-05-18
7 202144053149-FORM 3 [18-11-2022(online)].pdf 2022-11-18
8 202144053149-FORM 18 [02-12-2024(online)].pdf 2024-12-02