1
FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
POWER CONVERSION DEVICE
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED AND
EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED
2
DESCRIPTION
TECHNICAL FIELD
[0001] The present disclosure relates to a power
conversion device for converting AC power to DC power by
5 switching control.
BACKGROUND ART
[0002] A power conversion device that includes a circuit
having a plurality of semiconductor switching elements
10 connected in series, a DC capacitor for energy transfer, and
a reactor, and that outputs multi-level DC power by utilizing
charging and discharging of the DC capacitor, has been known.
A conventional power conversion device disclosed in
Patent Document 1 includes an inverter circuit having a
15 plurality of semiconductor switching elements and a DC
capacitor, and a converter circuit having a plurality of
semiconductor switching elements. A control unit controls
the inverter circuit and the converter circuit such that a
voltage of the DC capacitor of the inverter circuit is caused
20 to follow a target DC voltage and a power factor of input
current from an AC power supply is one. Furthermore, the
control unit performs control such that the power factor of
the input current is one by providing a period in which the
converter circuit is switched so as to be PWM (pulse width
25 modulation) controlled according to a preset voltage
3
condition, and adds a voltage correction value to the voltage
condition to determine switching to PWM-control of the
converter circuit.
[0003] A conventional power conversion device disclosed in
5 Patent Document 2 includes a reactor connected to a rectifier
circuit, a leg portion, and a DC capacitor. The leg portion
is structured such that two diodes, and first and second
switching elements are connected in series between positive
and negative terminals of a smoothing capacitor. A control
10 circuit performs high-frequency PWM control of the first and
the second switching elements by shifting a reference phase
by half a cycle at a regular driving cycle, controls the sum
of and a ratio between on-periods of the first and the second
switching elements in one cycle, and achieves both high power
15 factor control of an AC input and voltage control for the DC
capacitor.
CITATION LIST
PATENT DOCUMENT
20 [0004] Patent Document 1: Japanese Laid-Open Patent
Publication No. 2017-85691
Patent Document 2: International Publication No.
WO2015/045485
SUMMARY OF THE INVENTION
25 PROBLEMS TO BE SOLVED BY THE INVENTION
4
[0005] In the conventional power conversion device
disclosed in Patent Document 1, since control is switched at
a cycle of the AC power supply, a charging/discharging time
constant of the DC capacitor is greater than or equal to 1/4
5 of the cycle of the AC power supply. Therefore, it has been
difficult to reduce the capacitance and size of the DC
capacitor.
In the conventional power conversion device
disclosed in Patent Document 2, although the charging period
10 and the discharging period of the DC capacitor are adjusted
within a switching cycle, the voltage control for the DC
capacitor interferes with high power factor control of input
current. Therefore, it has been difficult to reduce the
capacitance of the DC capacitor while maintaining accuracy
15 for control of input current.
[0006] The present disclosure discloses a technique for
solving the aforementioned problems, and an object of the
present disclosure is to provide a power conversion device
that can suppress interference between control of input
20 current from an AC power supply and voltage control for a DC
capacitor to perform both the controls with high accuracy,
and can reduce the capacitance and size of the DC capacitor.
SOLUTION TO THE PROBLEMS
25 [0007] A power conversion device according to the present
5
disclosure includes: a power conversion circuit for
converting AC power from an AC power supply, to DC power, and
outputting the DC power; and a control circuit for performing
output control for the power conversion circuit. The power
5 conversion circuit includes: a rectification bridge circuit
connected to the AC power supply; a leg circuit including an
upper leg and a lower leg, connected in series, each of which
includes a plurality of semiconductor elements connected in
series via connection points, the plurality of semiconductor
10 elements of at least the lower leg being switching elements,
the leg circuit connected between DC buses and connected to
the AC power supply via the diode bridge circuit; at least
one DC capacitor connected between the connection point in
the upper leg and the connection point in the lower leg; a
15 reactor inserted in a current path between the AC power
supply and the leg circuit; and a smoothing capacitor
connected between the DC buses. The control circuit performs
PWM control of the leg circuit by generating a duty cycle so
as to cause a voltage of the DC capacitor to follow a command
20 value while controlling an input current from the AC power
supply, such that a sum of duty cycles corresponding to each
leg having the switching elements among the upper and the
lower legs, is constant in one cycle.
25 EFFECT OF THE INVENTION
6
[0008] The power conversion device according to the
present disclosure can suppress interference between control
of input current from the AC power supply and voltage control
for the DC capacitor to perform both the controls with high
5 accuracy, and can reduce the capacitance and the size of the
DC capacitor. Thus, the downsizing of the power conversion
device can be promoted.
BRIEF DESCRIPTION OF THE DRAWINGS
10 [0009] [FIG. 1] FIG. 1 schematically illustrates a
configuration of a power conversion device according to
embodiment 1.
[FIG. 2] FIG. 2 is a control block diagram
illustrating a control circuit of the power conversion device
15 according to embodiment 1.
[FIG. 3] FIG. 3 illustrates voltage/current
waveforms and operation ranges in the power conversion device
according to embodiment 1.
[FIG. 4] FIG. 4 illustrates kinds of switching
20 states in one operation range according to embodiment 1.
[FIG. 5] FIG. 5 illustrates kinds of switching
states in one operation range according to embodiment 1.
[FIG. 6] FIG. 6 illustrates kinds of switching
states in one operation range according to embodiment 1.
25 [FIG. 7] FIG. 7 illustrates kinds of switching
7
states in one operation range according to embodiment 1.
[FIG. 8] FIG. 8 is a waveform diagram illustrating
switching patterns and control in one operation range
according to embodiment 1.
5 [FIG. 9] FIG. 9 is a current path diagram
illustrating the control in FIG. 8.
[FIG. 10] FIG. 10 is a waveform diagram
illustrating switching patterns and control in one operation
range according to embodiment 1.
10 [FIG. 11] FIG. 11 is a current path diagram
illustrating the control in FIG. 10.
[FIG. 12] FIG. 12 is a waveform diagram
illustrating switching patterns and control in one operation
range according to embodiment 1.
15 [FIG. 13] FIG. 13 is a current path diagram
illustrating the control in FIG. 12.
[FIG. 14] FIG. 14 is a waveform diagram
illustrating switching patterns and control in one operation
range according to embodiment 1.
20 [FIG. 15] FIG. 15 is a current path diagram
illustrating the control in FIG. 14.
[FIG. 16] FIG. 16 illustrates a control block of a
high power factor control calculator according to embodiment
1.
25 [FIG. 17] FIG. 17 illustrates a control block of a
8
capacitor voltage control calculator according to embodiment
1.
[FIG. 18] FIG. 18 is a waveform diagram
illustrating control in voltage adjustment of a DC capacitor
5 according to embodiment 1.
[FIG. 19] FIG. 19 is a control block diagram
illustrating the control in FIG. 18.
[FIG. 20] FIG. 20 is a waveform diagram
illustrating control in voltage adjustment of the DC
10 capacitor according to embodiment 1.
[FIG. 21] FIG. 21 is a control block diagram
illustrating the control in FIG. 20.
[FIG. 22] FIG. 22 illustrates voltage and current
waveforms in the power conversion device for illustrating the
15 effect according to embodiment 1.
[FIG. 23] FIG. 23 schematically illustrates a
configuration of another example of the power conversion
device according to embodiment 1.
[FIG. 24] FIG. 24 schematically illustrates a
20 configuration of a power conversion device according to
embodiment 2.
[FIG. 25] FIG. 25 is a control block diagram
illustrating a control circuit of the power conversion device
according to embodiment 2.
25 [FIG. 26] FIG. 26 illustrates voltage/current
9
waveforms and operation ranges in the power conversion device
according to embodiment 2.
[FIG. 27] FIG. 27 illustrates kinds of switching
states in one operation range according to embodiment 2.
5 [FIG. 28] FIG. 28 illustrates kinds of switching
states in one operation range according to embodiment 2.
[FIG. 29] FIG. 29 illustrates kinds of switching
states in one operation range according to embodiment 2.
[FIG. 30] FIG. 30 is a waveform diagram
10 illustrating switching patterns and control in one operation
range according to embodiment 2.
[FIG. 31] FIG. 31 is a current path diagram
illustrating the control in FIG. 30.
[FIG. 32] FIG. 32 is a waveform diagram
15 illustrating switching patterns and control in one operation
range according to embodiment 2.
[FIG. 33] FIG. 33 is a current path diagram
illustrating the control in FIG. 32.
[FIG. 34] FIG. 34 is a waveform diagram
20 illustrating switching patterns and control in one operation
range according to embodiment 2.
[FIG. 35] FIG. 35 is a current path diagram
illustrating the control in FIG. 34.
[FIG. 36] FIG. 36 illustrates a control block of a
25 capacitor voltage control calculator according to embodiment
10
2.
[FIG. 37] FIG. 37 is a waveform diagram
illustrating control in voltage adjustment of a DC capacitor
according to embodiment 2.
5 [FIG. 38] FIG. 38 is a control block diagram
illustrating the control in FIG. 37.
[FIG. 39] FIG. 39 is a control block diagram
illustrating the control in FIG. 37.
[FIG. 40] FIG. 40 is a waveform diagram
10 illustrating control in voltage adjustment of the DC
capacitor according to embodiment 2.
[FIG. 41] FIG. 41 is a control block diagram
illustrating the control in FIG. 40.
[FIG. 42] FIG. 42 is a control block diagram
15 illustrating the control in FIG. 40.
[FIG. 43] FIG. 43 schematically illustrates a
configuration of a power conversion device according to
embodiment 3.
[FIG. 44] FIG. 44 schematically illustrates a
20 configuration of another example of the power conversion
device according to embodiment 3.
[FIG. 45] FIG. 45 schematically illustrates a
configuration of a power conversion device according to
embodiment 4.
25 [FIG. 46] FIG. 46 schematically illustrates a
11
configuration of another example of the power conversion
device according to embodiment 4.
DESCRIPTION OF EMBODIMENTS
5 [0010] Embodiment 1.
FIG. 1 schematically illustrates a configuration of
a power conversion device according to embodiment 1.
As shown in FIG. 1, a power conversion device 100
includes a power conversion circuit 1, and a control circuit
10 7 for performing output control for the power conversion
circuit 1, and performs power conversion of AC power from an
AC power supply 2, to supply DC power to a load 5.
The power conversion circuit 1 consists of a totem
pole type AC/DC converter circuit, and includes a
15 rectification bridge circuit 3 connected to the AC power
supply 2, a leg circuit 4, a DC capacitor Cf, a smoothing
capacitor Cdc, and a reactor L for limiting an input current
iac from the AC power supply 2.
[0011] The rectification bridge circuit 3, the leg circuit
20 4, and the smoothing capacitor Cdc are connected between DC
buses, respectively. The rectification bridge circuit 3 is a
half-bridge circuit composed of two diodes D1, D2 connected
in series. The mid-point of the rectification bridge circuit
3 as a connection point between the two diodes D1, D2 is
25 connected to a first end of the AC power supply 2 via the
12
reactor L. The leg circuit 4 is connected to the AC power
supply 2 via the rectification bridge circuit 3.
The leg circuit 4 has an upper leg 4a and a lower
leg 4b connected in series, and the mid-point as a connection
5 point between the upper leg 4a and the lower leg 4b is
connected to a second end of the AC power supply 2. The
upper leg 4a consists of switching elements Q1, Q2, as
semiconductor elements, connected in series via a connection
point. The lower leg 4b consists of switching elements Q3,
10 Q4, as semiconductor elements, connected in series via a
connection point.
Hereinafter, the switching elements Q1, Q2, Q3, Q4
will be simply referred to as Q1, Q2, Q3, Q4, respectively.
[0012] The DC capacitor Cf is connected between the
15 connection point of the Q1 and the Q2 in the upper leg 4a and
the connection point of the Q3 and the Q4 in the lower leg 4b.
The smoothing capacitor Cdc is connected in
parallel to the load 5 on the load 5 side of the leg circuit
4.
20 The DC capacitor Cf and the smoothing capacitor Cdc
can be each composed of an aluminum electrolytic capacitor, a
film capacitor, or the like.
[0013] The Q1, Q2, Q3, Q4 used in the leg circuit 4 are,
for example, IGBTs (insulated gate bipolar transistors) to
25 which diodes are connected in reverse parallel, MOSFETs
13
(metal oxide semiconductor field effect transistors) to which
diodes are connected between the sources and the drains, or
cascode GaN-HEMTs (gallium nitride-high mobility transistors).
The diodes may be diodes incorporated in the switching
5 elements or external diodes may be separately connected.
The rectification bridge circuit 3 may be
configured by using switching elements instead of the diodes
D1, D2, and the same type of switching elements as those used
in the leg circuit 4 may be used.
10 [0014] An AC voltage vac of the AC power supply 2, a
voltage Vcf of the DC capacitor Cf, and a voltage Vdc of the
smoothing capacitor Cdc are detected by a voltage sensor and
inputted to the control circuit 7. Regarding the AC voltage
Vac of the AC power supply 2, the AC voltage vac is,
15 particularly, an instantaneous voltage.
The input current iac from the AC power supply 2 is
detected by a current sensor and inputted to the control
circuit 7. The control circuit 7 generates a gate signal GQ
(GQ1, GQ2, GQ3, GQ4) for the Q1, Q2, Q3, Q4 in the leg
20 circuit 4 based on information about the inputted voltage and
current, and performs high-frequency switching of the Q1, Q2,
Q3, Q4 by PWM control to control the power conversion circuit
1.
[0015] FIG. 2 is a control block diagram illustrating the
25 control circuit 7.
14
As shown in FIG. 2, the control circuit 7 includes
a pattern generator 10 for generating a switching pattern SP,
a high power factor control calculator 11 (hereinafter,
referred to as first controller 11) for controlling the input
5 current iac, a capacitor voltage control calculator 12
(hereinafter, referred to as second controller 12) for
controlling the voltage Vcf of the DC capacitor Cf, an
addition/subtraction determination unit 13, an adder 14, and
a gate signal generator 15.
10 [0016] The pattern generator 10 generates the switching
pattern SP consisting of a combination of a plurality of
switching states, of the leg circuit 4, which vary in one
cycle of a control cycle. The first controller 11 uses the
generated switching pattern SP to generate a first duty cycle
15 D-PFC for performing control so as to improve a power factor
of the input current iac, converting AC power to DC power,
and outputting the DC power. The second controller 12
generates a second duty cycle D-Vcf so as to cause the
voltage Vcf of the DC capacitor Cf to follow a command value
20 Vcf*.
[0017] The addition/subtraction determination unit 13 and
the adder 14 operate so as to add or subtract the second duty
cycle D-Vcf to or from the first duty cycle D-PFC to
calculate a duty cycle D of the leg circuit 4. In this case,
25 as the duty cycle D, duty cycles D-Q1, D-Q2 for the Q1, Q2 in
15
the upper leg 4a are calculated. The addition/subtraction
determination unit 13 determines whether the second duty
cycle D-Vcf is to be added or subtracted, according to the
switching pattern SP. In the case of subtraction, the second
5 duty cycle D-Vcf is inputted to the adder 14 with the
polarity reversed. The duty cycles D-Q1, D-Q2 are generated
such that the sum of the duty cycles D-Q1, D-Q2 for the Q1,
Q2 becomes constant in one cycle.
[0018] The gate signal generator 15 obtains the duty
10 cycles D-Q3, D-Q4 for the Q3, Q4 in the lower leg 4b based on
the duty cycles D-Q1, D-Q2. The PWM control by comparing
each of the duty cycles D-Q1, D-Q2, D-Q3, D-Q4 with a carrier
wave, based on the switching pattern SP is performed, and the
gate signal GQ (GQ1, GQ2, GQ3, GQ4) for each of the Q1, Q2,
15 Q3, Q4 in the leg circuit 4 is generated based on the
switching pattern SP. As the carrier wave, a triangular wave,
a saw-tooth wave, or the like is used.
The duty cycles D-Q3, D-Q4 for the Q3, Q4 are
obtained according to D-Q3=1-(D-Q2), D-Q4=1-(D-Q1). The gate
20 signals GQ2 and GQ3 are signals that are on-off inverted
relative to each other. The gate signals GQ1 and GQ4 are
signals that are on-off inverted relative to each other.
[0019] Next, the control by the control circuit 7 and the
operation of the power conversion circuit 1 will be described
25 in detail.
16
The power conversion circuit 1 performs highfrequency
switching of the Q1, Q2, Q3, Q4 in the leg circuit
4 to boost a voltage while the input current iac flowing in
the reactor L is controlled to have a high power factor,
5 causes the smoothing capacitor Vdc to smooth power, and
supplies DC power to the load 5.
FIG. 3 illustrates voltage/current waveforms and
operation ranges in the power conversion device 100. FIG. 3
illustrates waveforms of the voltage Vac of the AC power
10 supply 2 such as a system power supply in one cycle, the
voltage Vcf of the DC capacitor Cf, the voltage Vdc of the
smoothing capacitor Cdc as an output voltage of the power
conversion circuit 1, and the input current iac.
[0020] The control circuit 7 determines a plurality of
15 operation ranges α1 to α4 based on a relationship in voltage
magnitude among the inputted AC voltage vac, the voltage Vcf,
and the voltage Vdc. In this case, two operation ranges are
in half the cycle of the AC power supply 2, and four
operation ranges are in one cycle.
20 In this case, Vcf=Vdc/2 and Vdc>vac are satisfied
as a voltage condition. The voltage Vcf may not necessarily
satisfy Vdc/2 as long as the voltage Vcf is lower than or
equal to the voltage Vdc.
[0021] The pattern generator 10 generates the switching
25 pattern SP according to the operation ranges α1 to α4.
17
As described above, the switching pattern SP
consists of a combination of a plurality of switching states,
of the leg circuit 4, which vary in one cycle of the control
cycle. In this case, the switching cycle of the PWM control
5 coincides with the control cycle.
One cycle of the gate signal GQ (GQ1, GQ2, GQ3,
GQ4) corresponds to a combination of four switching states
based on ON and OFF of the Q1, Q2, Q3, Q4 in the leg circuit
4 as described below. The combination of the four switching
10 states is the switching pattern SP. At this time, switching
states in which the reactor L is excited by application of a
positive voltage and switching states in which the reactor L
is reset by application of a negative voltage are combined so
as to alternate in order to control the input current iac.
15 [0022] In the power conversion circuit 1, the operation
for exciting the reactor L and the operation for resetting
the reactor L are different for each of the operation ranges
α1 to α4.
FIG. 4 to FIG. 7 illustrate kinds of the switching
20 states in the operation ranges α1 to α4. In a case where the
gate signal GQ (GQ1, GQ2, GQ3, GQ4) represents 1, the Q1, Q2,
Q3, Q4 is on. In a case where the gate signal GQ (GQ1, GQ2,
GQ3, GQ4) represents 0, the Q1, Q2, Q3, Q4 is off. A
charging, discharging, or through state of the DC capacitor
25 Cf and a voltage applied to the reactor L in each switching
18
state are also illustrated.
[0023] As shown in FIG. 4, in the operation range α1 in
which vac whose polarity is positive is less than or equal to
Vcf, the reactor L is excited in a switching state A1, and
5 the reactor L is reset in switching states D1, E1, F1. In
this case, the reactor L is excited only in the switching
state A1 in which the DC capacitor Cf is in a through state.
As shown in FIG. 5, in the operation range α2 in
which vac whose polarity is positive is higher than Vcf, the
10 reactor L is excited in switching states A2, B2, C2, and the
reactor L is reset in a switching state D2. In this case,
the reactor L is reset only in the switching state D2 in
which the DC capacitor Cf is in a through state.
[0024] As shown in FIG. 6, in the operation range α3 in
15 which vac whose polarity is negative has an absolute value
that is less than or equal to Vcf, the reactor L is excited
in switching states A3, B3, C3, and the reactor L is reset in
a switching state D3. In this case, the reactor L is reset
only in the switching state D3 in which the DC capacitor Cf
20 is in a through state.
As shown in FIG. 7, in the operation range α4 in
which vac whose polarity is negative has an absolute value
that is greater than Vcf, the reactor L is excited in a
switching state A4, and the reactor L is reset in switching
25 states D4, E4, F4. In this case, the reactor L is excited
19
only in the switching state A4 in which the DC capacitor Cf
is in a through state.
[0025] As described above, the pattern generator 10
generates the switching pattern SP according to the operation
5 ranges α1 to α4.
The pattern generator 10 selects four switching
states allowing overlapping from the switching states usable
in the operation ranges α1 to α4 and combines them, so as to
repeatedly alternate excitation and resetting of the reactor
10 L and charge the DC capacitor Cf once and discharge the DC
capacitor Cf once in one cycle, thereby generating the
switching pattern SP. One cycle has four sections based on
the switching states, and one cycle includes one section in
which the DC capacitor Cf is charged and one section in which
15 the DC capacitor Cf is discharged such that the numbers of
both the sections are the same.
[0026] The control in the operation range α1 will be
described below with reference to FIG. 8 and FIG. 9.
FIG. 8 illustrates the switching pattern SP (A1-E1-
20 A1-F1), the input current iac, the gate signal GQ (GQ1, GQ2,
GQ3, GQ4), and the charged and discharged states of the DC
capacitor Cf, in the operation range α1.
FIG. 9 illustrates a current path in the power
conversion circuit 1 in the switching pattern SP (A1-E1-A1-
25 F1).
20
As shown in FIG. 8 and FIG. 9, in one cycle of the
control cycle (switching cycle), the state varies as
indicated by A1 (excited)-E1 (reset and discharged)-A1
(excited)-F1 (reset and charged). That is, the excitation
5 and resetting of the reactor L repeatedly alternate, and the
charging and discharging of the DC capacitor Cf are each
performed once.
[0027] The control in the operation range α2 will be
described below with reference to FIG. 10 and FIG. 11.
10 FIG. 10 illustrates the switching pattern SP (B2-
D2-C2-D2), the input current iac, the gate signal GQ (GQ1,
GQ2, GQ3, GQ4), and the charged and discharged states of the
DC capacitor Cf, in the operation range α2.
FIG. 11 illustrates a current path in the power
15 conversion circuit 1 in the switching pattern SP (B2-D2-C2-
D2).
As shown in FIG. 10 and FIG. 11, in one cycle of
the control cycle (switching cycle), the state varies as
indicated by B2 (excited and discharged)-D2 (reset)-C2
20 (excited and charged)-D2 (reset). That is, the excitation
and resetting of the reactor L repeatedly alternate, and the
charging and discharging of the DC capacitor Cf are each
performed once.
[0028] The control in the operation range α3 will be
25 described below with reference to FIG. 12 and FIG. 13.
21
FIG. 12 illustrates the switching pattern SP (B3-
D3-C3-D3), the input current iac, the gate signal GQ (GQ1,
GQ2, GQ3, GQ4), and the charged and discharged states of the
DC capacitor Cf, in the operation range α3.
5 FIG. 13 illustrates a current path in the power
conversion circuit 1 in the switching pattern SP (B3-D3-C3-
D3).
As shown in FIG. 12 and FIG. 13, in one cycle of
the control cycle (switching cycle), the state varies as
10 indicated by B3 (excited and discharged)-D3 (reset)-C3
(excited and charged)-D3 (reset). That is, the excitation
and resetting of the reactor L repeatedly alternate, and the
charging and discharging of the DC capacitor Cf are each
performed once.
15 [0029] The control in the operation range α4 will be
described below with reference to FIG. 14 and FIG. 15.
FIG. 14 illustrates the switching pattern SP (A4-
E4-A4-F4), the input current iac, the gate signal GQ (GQ1,
GQ2, GQ3, GQ4), and the charged and discharged states of the
20 DC capacitor Cf, in the operation range α4.
FIG. 15 illustrates a current path in the power
conversion circuit 1 in the switching pattern SP (A4-E4-A4-
F4).
As shown in FIG. 14 and FIG. 15, in one cycle of
25 the control cycle (switching cycle), the state varies as
22
indicated by A4 (excited)-E4 (reset and discharged)-A4
(excited)-F4 (reset and charged). That is, the excitation
and resetting of the reactor L repeatedly alternate, and the
charging and discharging of the DC capacitor Cf are each
5 performed once.
[0030] As described above, the switching pattern SP is
generated such that excitation and resetting of the reactor L
repeatedly alternate and charging and discharging of the DC
capacitor Cf are each performed once in one cycle, according
10 to the operation ranges α1 to α4. The control for improving
a power factor of the input current iac and the voltage
control for the DC capacitor Cf are performed by using such a
switching pattern SP, whereby a high-accuracy control
responsiveness can be obtained.
15 The control circuit 7 stores, as a table,
information indicating the switching states for each of the
operation ranges α1 to α4 as shown in, for example, FIG. 4 to
FIG. 7, and selects a plurality of switching states with
reference to the table, to generate the switching pattern SP.
20 The switching pattern SP may be determined based on an
external command.
[0031] The gate signal GQ (GQ1, GQ2, GQ3, GQ4) based on
the switching pattern SP is generated.
As shown in FIG. 8, FIG. 10, FIG. 12, and FIG. 14,
25 the gate signal GQ1 and the gate signal GQ2 are shifted from
23
each other by half the cycle. The switching control of the
leg circuit 4 is performed based on the gate signal GQ1 and
the gate signal GQ2 shifted from each other by half the cycle,
whereby excitation and resetting of the reactor are each
5 performed twice in one cycle so as to alternate. Thus, the
power factor of the input current iac can be controlled. The
switching pattern SP is generated such that the number of
times the DC capacitor Cf is charged and the number of times
the DC capacitor Cf is discharged are equal to each other,
10 whereby a circuit configuration that can suppress the voltage
fluctuation of the DC capacitor Cf and does not use an
external power supply can be obtained.
[0032] In FIG. 8, FIG. 10, FIG. 12, and FIG. 14, a timing
t2 at the center in one cycle (t0-t4) is fixed, and the
15 timings t1, t3 are variable. That is, the gate signal GQ1
and the gate signal GQ2 which are shifted from each other by
half the cycle each become Hi (ON) at the cycle shifted by
half the cycle, while the timing at which the gate signal GQ1
and the gate signal GQ2 each become Low (OFF) varies
20 according to the duty cycles D-Q1, D-Q2.
The control of the input current iac, the voltage
control for the smoothing capacitor Cdc, and the voltage
control for the DC capacitor Cf are all performed by the PWM
control of the leg circuit 4, that is, performed by using the
25 duty cycle D as the command. The control circuit 7 adjusts
24
the timings t1, t3 according to the duty cycle D (D-Q1, D-Q2)
in each of the operation ranges α1 to α4, and controls an
output voltage (Vdc) and the voltage Vcf of the DC capacitor
Cf while performing high power factor control of the input
5 current iac.
[0033] FIG. 16 illustrates a control block of the first
controller 11. The first controller 11 generates the first
duty cycle D-PFC so as to control the input current iac such
that the power factor of 1 with respect to the voltage vac of
10 the AC power supply 2, and further perform voltage control
for the smoothing capacitor Cdc.
As shown in FIG. 16, a subtractor 16 calculates a
deviation between a DC voltage command value Vdc* and the
detected voltage Vdc of the smoothing capacitor Cdc. A PI
15 (proportional integral) controller 17 performs PI control to
calculate an amplitude Iac* such that the deviation
approaches 0. A PLL (phase locked loop) controller 18
generates a sine wave signal sin(ωt) that is in phase with
the voltage vac of the AC power supply 2. A multiplier 19
20 multiples the amplitude Iac* by the sine wave signal sin(ωt)
to calculate a current command iac*.
In a case where the voltage control for the
smoothing capacitor Cdc is not performed and only the high
power factor control of the current iac is performed, the
25 current command Iac* may be set based on an external command.
25
[0034] Subsequently, a subtractor 20 calculates a
deviation between the current command iac* and the detected
input current iac. A PI controller 21 performs PI control
such that the deviation approaches 0, and, thereafter, a
5 divider 22 performs division by the voltage Vcf of the DC
capacitor Cf to calculate a duty cycle 22a.
An FF calculator 23 calculates a feedforward term
23a based on the switching pattern SP generated by the
pattern generator 10. An adder 24 adds the feedforward term
10 23a and the duty cycle 22a to each other to generate the
first duty cycle D-PFC.
[0035] The FF calculator 23 calculates the feedforward
term 23a so as to improve responsiveness in the high power
factor control of the input current iac when control is
15 switched according to the operation ranges α1 to α4. Thus,
the feedforward term 23a is added to generate the first duty
cycle D-PFC, whereby rapid change during switching of control
according to the operation ranges α1 to α4 can be inhibited.
[0036] The feedforward term 23a is obtained by calculation
20 of a theoretical duty cycle that allows electric current
increase and reduction caused by excitation and resetting of
the reactor L to be equal to each other, and two theoretical
expressions are derived in one cycle. For example, in the
operation range α1, calculation is performed according to the
25 following expression (1) and expression (2).
26
(Vdc-vac-Vcf)/(Vdc-Vcf) ···(1)
(Vcf-vac)/Vcf ···(2)
Expression (1) represents a calculation for
balancing electric current increase and reduction according
5 to the two switching states A1, E1 in the switching pattern
SP (A1-E1-A1-F1) in the operation range α1. Expression (2)
represents a calculation for balancing electric current
increase and reduction according to the two switching states
A1, F1.
10 [0037] For example, in the operation range α2, calculation
is performed according to the following expression (3) and
expression (4).
(Vdc-vac)/(Vdc-Vcf) ··· (3)
(Vdc-vac)/Vcf ···(4)
15 Expression (3) represents a calculation for
balancing electric current increase and reduction according
to the two switching states B2, D2 in the switching pattern
SP (B2-D2-C2-D2) in the operation range α2. Expression (4)
represents a calculation for balancing electric current
20 increase and reduction according to the two switching states
C2, D2.
[0038] FIG. 17 illustrates a control block of the second
controller 12. The second controller 12 generates the second
duty cycle D-Vcf so as to cause the voltage Vcf of the DC
25 capacitor Cf to follow a command value Vcf*.
27
As shown in FIG. 17, a subtractor 25 calculates a
deviation between the command value Vcf* and the detected
voltage Vcf of the DC capacitor Cf. A P (proportional)
controller 26 performs P control such that the deviation
5 approaches 0, and, thereafter, a divider 27 performs division
by the voltage Vcf of the DC capacitor Cf to calculate a duty
cycle 27a. A sample and hold unit 28 updates a value of the
duty cycle 27a for each cycle, and outputs the value as the
second duty cycle D-Vcf.
10 [0039] Next, control of the addition/subtraction
determination unit 13 will be described in detail.
As described above, the second duty cycle D-Vcf is
added to or subtracted from the first duty cycle D-PFC to
calculate the duty cycle D (D-Q1, D-Q2) of the leg circuit 4.
15 The addition/subtraction determination unit 13 determines
whether the second duty cycle D-Vcf is to be added or
subtracted, according to the switching pattern SP. At this
time, addition or subtraction is determined such that the sum
of the duty cycles D-Q1, D-Q2 is constant in one cycle. That
20 is, the sum of the duty cycles D-Q1, D-Q2 is constant
regardless of voltage fluctuation of the DC capacitor Cf, and
is equal to the sum of the first duty cycles D-PFC
(corresponding components of the Q1, Q2).
[0040] An example of an operation of the
25 addition/subtraction determination unit 13 in the operation
28
range α1 will be described below.
FIG. 18 shows waveforms for illustrating control in
which the voltage Vcf of the DC capacitor Cf is reduced due
to the voltage Vcf being higher than the command value Vcf*
5 in the operation range α1. FIG. 19 is a control block
diagram illustrating the control in FIG. 18.
As shown in FIG. 18, the timing t1 at which the Q1
is switched off is shifted leftward in FIG. 18 to increase
the discharging section, and the timing t3 at which the Q2 is
10 switched off is shifted rightward in FIG. 18 to shorten the
charging section. As shown in FIG. 19, in a case where the
duty cycle D-Q1 is generated, the addition/subtraction
determination unit 13 determines that the second duty cycle
D-Vcf is to be subtracted from the first duty cycle D-PFC, to
15 reduce the duty cycle D-Q1. In a case where the duty cycle
D-Q2 is generated, the addition/subtraction determination
unit 13 determines that the second duty cycle D-Vcf is to be
added to the first duty cycle D-PFC, to increase the duty
cycle D-Q2.
20 [0041] FIG. 20 shows waveforms for illustrating control in
which the voltage Vcf of the DC capacitor Cf is increased due
to the voltage Vcf being lower than the command value Vcf* in
the operation range α1. FIG. 21 is a control block diagram
illustrating the control in FIG. 20.
25 As shown in FIG. 20, the timing t1 at which the Q1
29
is switched off is shifted rightward in FIG. 20 to shorten
the discharging section, and the timing t3 at which the Q2 is
switched off is shifted leftward in FIG. 20 to increase the
charging section. As shown in FIG. 21, in a case where the
5 duty cycle D-Q1 is generated, the addition/subtraction
determination unit 13 determines that the second duty cycle
D-Vcf is to be added to the first duty cycle D-PFC, to
increase the duty cycle D-Q1. In a case where the duty cycle
D-Q2 is generated, the addition/subtraction determination
10 unit 13 determines that the second duty cycle D-Vcf is to be
subtracted from the first duty cycle D-PFC, to reduce the
duty cycle D-Q2.
[0042] In both a case where the voltage Vcf is reduced as
shown in FIG. 18 and FIG. 19 and a case where the voltage Vcf
15 is increased as shown in FIG. 20 and FIG. 21, the second duty
cycle D-Vcf is added for one of the two duty cycles D-Q1, DQ2,
and the second duty cycle D-Vcf is subtracted for the
other thereof, so that the sum is not changed and is constant.
The sample and hold unit 28 in the second controller 12 holds
20 a value of the second duty cycle D-Vcf in one cycle and
outputs the value. Therefore, in the calculation, the sum of
the two duty cycles D-Q1, D-Q2 can be assuredly made constant.
In a case where the sum of the duty cycles D-Q1, DQ2
of the Q1, Q2 in the upper leg 4a is constant, the sum of
25 the duty cycles D-Q3, D-Q4 of the Q3, Q4 in the lower leg 4b
30
also becomes constant.
[0043] Thus, voltage control for the DC capacitor Cf can
be performed for each control cycle (one switching cycle).
Furthermore, the sum of the two duty cycles D-Q1, D-Q2 is
5 constant and is equal to the sum of the first duty cycles DPFC.
Therefore, interference with the high power factor
control of the input current iac is significantly suppressed.
[0044] As described above, in the present embodiment, the
control circuit 7 uses the switching pattern SP to control
10 charging and discharging of the DC capacitor Cf and control
the input current iac according to the first duty cycle D-PFC.
Furthermore, the addition/subtraction determination unit 13
operates to add or subtract the second duty cycle D-Vcf to or
from the first duty cycle D-PFC, thereby suppressing voltage
15 fluctuation of the DC capacitor Cf. Although the two duty
cycles D-Q1, D-Q2 are adjusted so as to suppress voltage
fluctuation of the DC capacitor Cf, the sum thereof is not
changed and is constant.
[0045] Thus, the voltage control for the DC capacitor Cf
20 can be performed for each control cycle (one switching cycle).
Therefore, a charging/discharging time constant of the DC
capacitor Cf can be made equal to the control cycle.
Therefore, the capacitance of the DC capacitor Cf can be
reduced while a preferable control responsiveness is
25 maintained. The sum of the two duty cycles D-Q1, D-Q2 is
31
constant regardless of voltage fluctuation of the DC
capacitor Cf, and is equal to the sum of the first duty
cycles D-PFC. Therefore, interference with high power factor
control of the input current iac is significantly suppressed.
5 [0046] For example, in the technique disclosed in Patent
Document 1, the capacitance of the DC capacitor Cf needs to
be greater than or equal to several hundreds of μF. However,
even if the capacitance of the DC capacitor Cf is reduced to
several tens of μF, the circuit can be stably operated by the
10 control operation according to the present embodiment. FIG.
22 illustrates voltage and current waveforms in several kW
level of a power conversion device having the configuration
of the present embodiment. In this case, the capacitance of
the DC capacitor Cf is 20 μF. As shown in FIG. 22, the DC
15 capacitor Cf allows achievement of high power factor control
of the input current iac and control for making the voltage
Vcf of the DC capacitor Cf constant, with a low capacitance
of 20 μF.
[0047] As described above, in the control operation
20 according to the present embodiment, interference between the
high power factor control of the input current iac and the
voltage control for the DC capacitor Cf can be suppressed to
perform both the controls with high accuracy, and the
capacitance and the size of the DC capacitor Cf can be
25 reduced. Thus, the downsizing of the power conversion device
32
100 can be promoted.
[0048] In embodiment 1, the feedforward term 23a is added
to generate the first duty cycle D-PFC. However, the first
duty cycle D-PFC may be generated without using such a
5 feedforward control. In this case, although control
responsiveness to rapid change during switching of control
may be degraded, the above-described effect can be similarly
obtained.
[0049] In embodiment 1, the reactor L is connected between
10 the mid-point of the rectification bridge circuit 3 and the
first end of the AC power supply 2. However, the structure
is not limited thereto as long as the reactor L is inserted
in the current path between the AC power supply 2 and the leg
circuit 4.
15 As shown in FIG. 23, a reactor Lp may be connected
between the mid-point of the rectification bridge circuit 3
and the first end of the AC power supply 2, and a reactor Ln
may be connected between the mid-point of the leg circuit 4
and the second end of the AC power supply 2. In this case,
20 imbalance in the current path due to the polarity of the AC
voltage Vac does not occur, whereby generation of a common
mode noise in the power conversion circuit 1 can be
suppressed.
[0050] Embodiment 2.
25 FIG. 24 schematically illustrates a configuration
33
of a power conversion device according to embodiment 2.
As shown in FIG. 24, a power conversion device 200
includes a power conversion circuit 1A, and a control circuit
7A for performing output control for the power conversion
5 circuit 1A, and performs power conversion of AC power from
the AC power supply 2, to supply DC power to the load 5.
The power conversion circuit 1A consists of a totem
pole type AC/DC converter circuit, and includes the
rectification bridge circuit 3 connected to the AC power
10 supply 2, a leg circuit 6, first and second DC capacitors Cf1,
Cf2 that are two DC capacitors, the smoothing capacitor Cdc,
and the reactor L for limiting the input current iac from the
AC power supply 2.
In this case, the leg circuit 6, the first and the
15 second DC capacitors Cf1, Cf2, and the control circuit 7A are
different from those in embodiment 1, and the other
configurations are the same as those in embodiment 1.
Therefore, the description is omitted as appropriate.
[0051] The rectification bridge circuit 3, the leg circuit
20 6, and the smoothing capacitor Cdc are connected between DC
buses, respectively.
The leg circuit 6 has an upper leg 6a and a lower
leg 6b connected in series, and the mid-point as a connection
point between the upper leg 6a and the lower leg 6b is
25 connected to the second end of the AC power supply 2. The
34
upper leg 6a consists of switching elements Q1, Q2, Q3, as
semiconductor elements, connected in series via connection
points. The lower leg 6b consists of switching elements Q4,
Q5, Q6, as semiconductor elements, connected in series via
5 connection points.
Hereinafter, the switching elements Q1, Q2, Q3, Q4,
Q5, Q6 will be simply referred to as Q1, Q2, Q3, Q4, Q5, Q6,
respectively.
[0052] The first DC capacitor Cf1 is connected between a
10 connection point of the Q2 and Q3 in the upper leg 6a and a
connection point of the Q4 and Q5 in the lower leg 6b. The
second DC capacitor Cf2 is connected between a connection
point of the Q1 and the Q2 in the upper leg 6a and a
connection point of the Q5 and Q6 in the lower leg 6b. Thus,
15 the second DC capacitor Cf2 is disposed closer to the outer
side relative to the center of the leg circuit 6 than the
first DC capacitor Cf1 is.
The first and the second DC capacitors Cf1, Cf2 and
the smoothing capacitor Cdc can be each composed of an
20 aluminum electrolytic capacitor, a film capacitor, or the
like.
[0053] The Q1, Q2, Q3, Q4, Q5, Q6 used in the leg circuit
6 are, for example, IGBTs to which diodes are connected in
reverse parallel, MOSFETs to which diodes are connected
25 between the sources and the drains, or cascode GaN-HEMTs, as
35
in embodiment 1. The diodes may be diodes incorporated in
the switching elements or external diodes may be separately
connected. The rectification bridge circuit 3 may be
configured by using switching elements instead of the diodes
5 D1, D2.
[0054] The AC voltage vac of the AC power supply 2,
voltages Vcf1 and Vcf2 of the first and the second DC
capacitors Cf1, Cf2, and the voltage Vdc of the smoothing
capacitor Cdc are detected by a voltage sensor and inputted
10 to the control circuit 7A.
Furthermore, the input current iac from the AC
power supply 2 is detected by a current sensor and inputted
to the control circuit 7A. The control circuit 7A generates
a gate signal GQA (GQ1, GQ2, GQ3, GQ4, GQ5, GQ6) for the Q1,
15 Q2, Q3, Q4, Q5, Q6 in the leg circuit 6 based on information
about the inputted voltage and current, and performs highfrequency
switching of the Q1, Q2, Q3, Q4, Q5, Q6 by PWM
control to control the power conversion circuit 1A.
In this case, the control circuit 7A controls
20 driving of the Q1, Q2, Q3, Q4, Q5, Q6 by setting two cycles
of the switching cycle as a control cycle. The control cycle
is determined according to the switching cycle corresponding
to the number of the DC capacitors (Cf1, Cf2) in the power
conversion circuit 1A.
25 [0055] FIG. 25 is a control block diagram illustrating the
36
control circuit 7A.
As shown in FIG. 25, the control circuit 7A
includes a pattern generator 10A for generating a switching
pattern SPA, a high power factor control calculator 11A
5 (hereinafter, referred to as first controller 11A) for
controlling the input current iac, a capacitor voltage
control calculator 12A (hereinafter, referred to as second
controller 12A) for controlling voltages Vcf1, Vcf2 of the
first and the second DC capacitors Cf1, Cf1,respectively, an
10 addition/subtraction determination unit 13A, the adder 14,
and a gate signal generator 15A.
[0056] The pattern generator 10A generates the switching
pattern SPA consisting of a combination of a plurality of
switching states, of the leg circuit 6, which vary in one
15 cycle of the control cycle corresponding to two switching
cycles. The first controller 11A uses the generated
switching pattern SPA to generate a first duty cycle D-PFC
for performing control so as to improve a power factor of the
input current iac, converting AC power to DC power, and
20 outputting the DC power. The second controller 12A generates
second duty cycles D-Vcf1, D-Vcf2 so as to cause the voltages
Vcf1, Vcf2 of the first and the second DC capacitors Cf1, Cf2
to follow command values Vcf1*, Vcf2*, respectively.
[0057] The addition/subtraction determination unit 13A and
25 the adder 14 operate so as to add or subtract the second duty
37
cycles D-Vcf1, D-Vcf2 to or from the first duty cycle D-PFC
to calculate a duty cycle D of the leg circuit 6. In this
case, as the duty cycle D, the duty cycles D-Q1, D-Q2, D-Q3
for the Q1, Q2, Q3 in the upper leg 6a are calculated. The
5 addition/subtraction determination unit 13A determines
whether the second duty cycles D-Vcf1, D-Vcf2 are to be added
or subtracted, according to the switching pattern SPA. In
the case of subtraction, the second duty cycles D-Vcf1 and DVcf2
are inputted to the adder 14 with the polarities
10 reversed. The duty cycles D-Q1, D-Q2, D-Q3 are generated
such that the sum of the duty cycles D-Q1, D-Q2, D-Q3 for the
Q1, Q2, Q3 becomes constant in one cycle of the control cycle.
[0058] The gate signal generator 15A obtains the duty
cycles D-Q4, D-Q5, D-Q6 for the Q4, Q5, Q6 in the lower leg
15 6b based on the duty cycles D-Q1, D-Q2, D-Q3. The PWM
control by comparing each of the duty cycles D-Q1, D-Q2, D-Q3,
D-Q4, D-Q5, D-Q6 with a carrier wave based on the switching
pattern SPA is performed, and the gate signal GQA (GQ1, GQ2,
GQ3, GQ4, GQ5, GQ6) for each of the Q1, Q2, Q3, Q4, Q5, Q6 in
20 the leg circuit 6 is generated. As the carrier wave, a
triangular wave, a saw-tooth wave, or the like is used.
The duty cycles D-Q4, D-Q5, D-Q6 for the Q4, Q5, Q6
are obtained according to D-Q4=1-(D-Q3), D-Q5=1-(D-Q2), DQ6=
1-(D-Q1). The gate signals GQ3 and GQ4 are signals that
25 are on-off inverted relative to each other. The gate signals
38
GQ2 and GQ5 are signals that are on-off inverted relative to
each other. The gate signals GQ1 and GQ6 are signals that
are on-off inverted relative to each other.
[0059] Next, the control by the control circuit 7A and the
5 operation of the power conversion circuit 1A will be
described in detail.
The power conversion circuit 1A performs highfrequency
switching of the Q1 to Q6 in the leg circuit 4 to
boost a voltage while the input current iac flowing in the
10 reactor L is controlled to have a high power factor, causes
the smoothing capacitor Cdc to smooth power, and supplies DC
power to the load 5.
FIG. 26 illustrates voltage/current waveforms and
operation ranges in the power conversion device 200. FIG. 26
15 illustrates waveforms of the voltage Vac of the AC power
supply 2 such as a system power supply in one cycle, the
voltages Vcf1, Vcf2 of the first and the second DC capacitors
Cf1, Cf2, the voltage Vdc, of the smoothing capacitor Cdc,
which is an output voltage from the power conversion circuit
20 1A, and the input current iac.
[0060] The control circuit 7A determines a plurality of
operation ranges β1 to β6 based on a relationship in voltage
magnitude among the inputted AC voltage vac, the voltage Vcf1,
the voltage Vcf2, and the voltage Vdc. In this case, three
25 operation ranges are in half the cycle of the AC power supply
39
2, and six operation ranges are in one cycle.
In this case, Vcf1=Vdc/3, Vcf2=2Vdc/3, Vdc>vac are
satisfied as a voltage condition. The voltage Vcf2 may not
necessarily satisfy the above-described voltage condition as
5 long as the voltage Vcf2 is lower than or equal to the
voltage Vdc. The voltage Vcf1 may not necessarily satisfy
the above-described voltage condition as long as the voltage
Vcf1 is lower than or equal to the voltage Vcf2.
[0061] The pattern generator 10A generates the switching
10 pattern SPA according to the operation ranges β1 to β6.
As described above, the switching pattern SPA
consists of a combination of a plurality of switching states,
of the leg circuit 6, which vary in one cycle of the control
cycle which corresponds to two cycles of the switching cycle
15 in the PWM control.
One cycle of the control cycle of the gate signal
GQA (GQ1 to GQ6) corresponds to a combination of eight
switching states based on ON and OFF of the Q1 to Q6 in the
leg circuit 6 as described below. The combination of the
20 eight switching states is the switching pattern SPA. At this
time, switching states in which the reactor L is excited by
application of a positive voltage and switching states in
which the reactor L is reset by application of a negative
voltage are combined so as to alternate in order to control
25 the input current iac.
40
[0062] In the power conversion circuit 1A, the operation
for exciting the reactor L and the operation for resetting
the reactor L are different for each of the operation ranges
β1 to β6. Each of the operation ranges β1, β2, β3 in half
5 the cycle in which the AC voltage Vac has a positive polarity
will be described below in detail. In each of the operation
ranges β4, β5, β6 in half the cycle in which the AC voltage
Vac has a negative polarity, the polarity of the current is
reversed, however, the case is similar to the case for the
10 positive polarity, then the description is omitted as
appropriate.
FIG. 27 to FIG. 29 illustrate kinds of the
switching states in the operation ranges β1, β2, β3. In a
case where the gate signal GQA (GQ1 to GQ6) represents 1, the
15 Q1 to Q6 are on. In a case where the gate signal GQA (GQ1 to
GQ6) represents 0, the Q1 to Q6 are off. A charging,
discharging, or through state of the first and the second DC
capacitors Cf1, Cf2, and a voltage applied to the reactor L
in each switching state are also illustrated.
20 [0063] As shown in FIG. 27, in the operation range β1 in
which vac whose polarity is positive is less than or equal to
Vcf1, the reactor L is excited in a switching state A1, and
the reactor L is reset in switching states F1, G1, H1, I1, J1,
K1. In this case, the reactor L is excited only in the
25 switching state A1 in which both the first and the second DC
41
capacitors Cf1, Cf2 are in through states, and six kinds of
different switching states are for resetting of the reactor L.
As shown in FIG. 28, in the operation range β2 in
which vac whose polarity is positive is higher than Vcf1 and
5 less than or equal to Vcf2, the reactor L is excited in
switching states A2, B2, C2, D2, and the reactor L is reset
in switching states F2, G2, I2, J2. In this case, four kinds
of different switching states are for each of excitation and
resetting of the reactor L.
10 As shown in FIG. 29, in the operation range β3 in
which vac whose polarity is positive is higher than Vcf2, the
reactor L is excited in switching states A3, B3, C3, D3, E3,
F3, and the reactor L is reset in a switching state G3. In
this case, the reactor L is reset only in the switching state
15 G3 in which both the first and the second DC capacitors Cf1,
Cf2 are in through states, and six kinds of different
switching states are for excitation of the reactor L.
[0064] As described above, the pattern generator 10A
generates the switching pattern SPA according to the
20 operation ranges β1 to β6.
The pattern generator 10A generates the switching
pattern SPA such that, in one cycle of the control cycle, the
excitation and resetting of the reactor L repeatedly
alternate, and the number of times the first and the second
25 DC capacitors Cf1, Cf2 are each charged and the number of
42
times the first and the second DC capacitors Cf1, Cf2 are
each discharged are equal to each other. Eight switching
states are selected allowing overlapping from the switching
states usable in the operation ranges β1 to β6 and combined,
5 thereby generating the switching pattern SPA. One switching
cycle consists of four sections according to the switching
states. That is, one control cycle consists of eight
sections according to the switching states. In one cycle of
the control cycle, the number of the charging sections and
10 the number of the discharging sections are equal to each
other for the first DC capacitor Cf1, and the number of
charging sections and the number of discharging sections are
equal to each other for the second DC capacitor Cf2.
[0065] The control in the operation range β1 will be
15 described below with reference to FIG. 30 and FIG. 31.
FIG. 30 illustrates the switching pattern SPA (A1-
G1-A1-I1-A1-H1-A1-J1), the input current iac, the gate signal
GQA (GQ1 to GQ6), and the charged and discharged states of
the first and the second DC capacitors Cf1, Cf2, in the
20 operation range β1.
FIG. 31 illustrates a current path in the power
conversion circuit 1A in the switching pattern SPA (A1-G1-A1-
I1-A1-H1-A1-J1).
As shown in FIG. 30 and FIG. 31, in one cycle of a
25 control cycle T consisting of two switching cycles S1, S2,
43
the state varies as indicated by A1 (excited)-G1 (reset and
Cf1 discharged)-A1 (excited)-I1 (reset and Cf1 charged)-A1
(excited)-H1 (reset and Cf2 discharged)-A1 (excited)-J1
(reset and Cf2 charged). That is, excitation and resetting
5 of the reactor L repeatedly alternate, the charging and
discharging of the first DC capacitor Cf1 are each performed
once, and the charging and discharging of the second DC
capacitor Cf2 are each performed once.
[0066] The control in the operation range β2 will be
10 described below with reference to FIG. 32 and FIG. 33.
FIG. 32 illustrates the switching pattern SPA (D2-
F2-E2-F2-B2-I2-B2-F2), the input current iac, the gate signal
GQA (GQ1 to GQ6), and the charged and discharged states of
the first and the second DC capacitors Cf1, Cf2, in the
15 operation range β2.
FIG. 33 illustrates a current path in the power
conversion circuit 1A in the switching pattern SPA (A1-G1-A1-
I1-A1-H1-A1-J1).
As shown in FIG. 32 and FIG. 33, in one cycle of
20 the control cycle T consisting of two switching cycles S1, S2,
the state varies as indicated by D2 (excited and Cf1
charged)-F2 (reset)-E2 (excited and Cf2 discharged)-F2
(reset)-B2 (excited, Cf1 discharged, Cf2 charged)-I2 (reset,
Cf1 charged, Cf2 discharged)-B2 (excited, Cf1 discharged, Cf2
25 charged)-F2 (reset). That is, excitation and resetting of
44
the reactor L repeatedly alternate, the charging and
discharging of the first DC capacitor Cf1 are each performed
twice, and the charging and discharging of the second DC
capacitor Cf2 are each performed twice.
5 [0067] The control in the operation range β3 will be
described below with reference to FIG. 34 and FIG. 35.
FIG. 34 illustrates the switching pattern SPA (B3-
G3-D3-G3-C3-G3-E3-G3), the input current iac, the gate signal
GQA (GQ1 to GQ6), and the charged and discharged states of
10 the first and the second DC capacitors Cf1, Cf2, in the
operation range β3.
FIG. 35 illustrates a current path in the power
conversion circuit 1A in the switching pattern SPA (B3-G3-D3-
G3-C3-G3-E3-G3).
15 As shown in FIG. 34 and FIG. 35, in one cycle of
the control cycle T consisting of two switching cycles S1, S2,
the state varies as indicated by B3 (excited and Cf1
discharged)-G3 (reset)-D3 (excited and Cf1 charged)-G3
(reset)-C3 (excited and Cf2 discharged)-G3 (reset)-E3
20 (excited and Cf2 charged)-G3 (reset). That is, excitation
and resetting of the reactor L repeatedly alternate, the
charging and discharging of the first DC capacitor Cf1 are
each performed once, and the charging and discharging of the
second DC capacitor Cf2 are each performed once.
25 [0068] As described above, the switching pattern SPA is
45
generated such that the excitation and resetting of the
reactor L repeatedly alternate, and the number of times each
of the first and the second DC capacitors Cf1, Cf2 is charged
and the number of times each of the first and the second DC
5 capacitors Cf1, Cf2 is discharged are equal to each other, in
one control cycle, according to the operation ranges β1 to β6.
The control for improving a power factor of the input current
iac and the voltage control for the first and the second DC
capacitors Cf1, Cf2 are performed by using such a switching
10 pattern SPA, whereby a high-accuracy control responsiveness
can be obtained.
The control circuit 7A stores, as a table,
information indicating the switching states for each of the
operation ranges β1 to β6 as shown in, for example, FIG. 27
15 to FIG. 29, and selects a plurality of switching states with
reference to the table, to generate the switching pattern SPA.
The switching pattern SPA may be determined based on an
external command.
[0069] The gate signal GQA (GQ1 to GQ6) based on the
20 switching pattern SPA is generated.
As shown in FIG. 30, FIG. 32, and FIG. 34, the gate
signal GQ1 and the gate signal GQ3 are shifted from each
other by half the cycle of the switching cycle. The gate
signal GQ2 is a signal that is in synchronization with the
25 gate signal GQ1 in one switching cycle S1 and is in
46
synchronization with the gate signal GQ3 in the other
switching cycle S2, in the control cycle T. The switching
control of the leg circuit 6 is performed based on such gate
signals GQ1 to GQ3, whereby excitation and resetting of the
5 reactor are each performed four times so as to alternate in
one control cycle. Thus, the power factor of the input
current iac can be controlled. The switching pattern SPA is
generated such that the number of times each of the first and
the second DC capacitors Cf1, Cf2 is charged and the number
10 of times each of the first and the second DC capacitors Cf1,
Cf2 is discharged are equal to each other, whereby a circuit
configuration that can suppress voltage fluctuation of each
of the first and the second DC capacitors Cf1, Cf2 and does
not use an external power supply can be obtained.
15 [0070] In FIG. 30, FIG. 32, and FIG. 34, the timings t0,
t2, t4, t6, t8 in one cycle (t0-t8) are determined by half
the cycle of the switching cycles S1, S2 and fixed, and the
timings t1, t3, t5 are variable. That is, the gate signal
GQ1 and the gate signal GQ3 which are shifted from each other
20 by half the cycle of the switching cycle each become Hi (ON)
at the cycle shifted by half the cycle, while the timing at
which the gate signal GQ1 and the gate signal GQ3 each become
Low (OFF) varies according to the duty cycles D-Q1, D-Q3.
The gate signal GQ2 varies in the switching cycle S1 in the
25 same manner as the gate signal GQ1 and varies in the
47
switching cycle S2 in the same manner as the gate signal GQ3.
[0071] The control of the input current iac, the voltage
control for the smoothing capacitor Cdc, and the voltage
control for each of the first and the second DC capacitors
5 Cf1, Cf2 are all performed by PWM control of the leg circuit
6, that is, performed by using the duty cycle D as the
command. The control circuit 7A adjusts the timings t1, t3,
t5 according to the duty cycle D (D-Q1, D-Q2, D-Q3) in each
of the operation ranges β1 to β6, and controls the output
10 voltage (Vdc) and the voltages Vcf1, Vcf2 of the first and
the second DC capacitors Cf1, Cf2 while performing high power
factor control of the input current iac.
[0072] The first controller 11A controls the input current
iac such that a power factor of 1 with respect to the voltage
15 vac of the AC power supply 2, and further generates the first
duty cycle D-PFC so as to perform voltage control for the
smoothing capacitor Cdc. The first controller 11A has the
same configuration as the first controller 11 of embodiment 1
shown in FIG. 16, and operates in the same manner as the
20 first controller 11.
Also in this case, the FF calculator 23 calculates
the feedforward term 23a and generates the first duty cycle
D-PFC to which the feedforward term 23a has been added.
[0073] Also in embodiment 2, the feedforward term 23a is
25 calculated so as to improve responsiveness in the high power
48
factor control of the input current iac when control is
switched according to the operation ranges β1 to β6, whereby
rapid change during switching of control can be inhibited.
The feedforward term 23a is obtained by calculation
5 of a theoretical duty cycle that allows electric current
increase and reduction caused by excitation and resetting of
the reactor L to be equal to each other. In this case, up to
four theoretical expressions are derived in one control cycle.
For example, in the operation range β1, calculation is
10 performed according to the following expressions (5) to (8).
[0074] (Vdc-vac-Vcf1)/(Vdc-Vcf1) ···(5)
(Vcf1-vac)/Vcf1 ···(6)
(Vdc-vac-Vcf2)/(Vdc-Vcf2) ···(7)
(Vcf2-vac)/Vcf2 ···(8)
15 Expression (5) represents a calculation for
balancing electric current increase and reduction according
to the two switching states A1, G1 in the switching pattern
SPA (A1-G1-A1-I1-A1-H1-A1-J1) in the operation range β1.
Expression (6) represents a calculation for balancing
20 electric current increase and reduction according to the two
switching states A1, I1. Expression (7) represents a
calculation for balancing electric current increase and
reduction according to the two switching states A1, H1.
Expression (8) represents a calculation for balancing
25 electric current increase and reduction according to the two
49
switching states A1, J1.
[0075] In the operation range β2, calculation is performed
according to the following expressions (9) to (12).
(Vdc-vac)/(Vdc-Vcf1) ···(9)
5 (Vdc-vac)/Vcf2 ···(10)
(Vdc-vac-Vcf2+Vcf1)/(Vdc-2Vcf2+2Vcf1) ···(11)
(Vcf-vac)/(Vdc-Vcf2+Vcf1) ···(12)
Expression (9) represents a calculation for
balancing electric current increase and reduction according
10 to the two switching states D2, F2 in the switching pattern
SPA (D2-F2-E2-F2-B2-I2-B2-F2) in the operation range β2.
Expression (10) represents a calculation for balancing
electric current increase and reduction according to the two
switching states E2, F2. Expression (11) represents a
15 calculation for balancing electric current increase and
reduction according to the two switching states B2, I2.
Expression (12) represents a calculation for balancing
electric current increase and reduction according to the two
switching states B2, F2.
20 [0076] In the operation range β3, calculation is performed
according to the following expressions (13) to (16).
(Vdc-vac)/Vcf1 ···(13)
(Vdc-vac)/(Vdc-Vcf1) ···(14)
(Vdc-vac)/Vcf2 ···(15)
25 (Vdc-vac)/(Vdc-Vcf2) ···(16)
50
Expression (13) represents a calculation for
balancing electric current increase and reduction according
to the two switching states B3, G3 in the switching pattern
SPA (B3-G3-D3-G3-C3-G3-E3-G3) in the operation range β3.
5 Expression (14) represents a calculation for balancing
electric current increase and reduction according to the two
switching states D3, G3. Expression (15) represents a
calculation for balancing electric current increase and
reduction according to the two switching states C3, G3.
10 Expression (16) represents a calculation for balancing
electric current increase and reduction according to the two
switching states E3, G3.
[0077] FIG. 36 illustrates a control block of the second
controller 12A. The second controller 12A generates the
15 second duty cycles D-Vcf1, D-Vcf2 so as to cause the voltages
Vcf1, Vcf2 of the first and the second DC capacitors Cf1, Cf2
to follow command values Vcf1*, Vcf2*, respectively.
As shown in FIG. 36, the subtractor 25 calculates a
deviation between the command value Vcf1* and the detected
20 voltage Vcf1 of the first DC capacitor Cf1. The P controller
26 performs P control such that the deviation approaches 0,
and, thereafter, the divider 27 performs division by the
voltage Vcf1 to calculate a duty cycle 27b. The sample and
hold unit 28 updates a value of the duty cycle 27b for each
25 control cycle, and outputs the value as the second duty cycle
51
D-Vcf1. The subtractor 25 similarly calculates a deviation
between the command value Vcf1* and the detected voltage Vcf2
also for the second DC capacitor Cf2. The P controller 26
performs P control such that the deviation approaches 0, and,
5 thereafter, the divider 27 performs division by the voltage
Vcf2 to calculate a duty cycle 27c. The sample and hold unit
28 updates a value of the duty cycle 27c for each control
cycle, and outputs the value as the second duty cycle D-Vcf2.
[0078] Next, control of the addition/subtraction
10 determination unit 13A will be described in detail.
As described above, the second duty cycles D-Vcf1,
D-Vcf2 are added to or subtracted from the first duty cycle
D-PFC to calculate the duty cycle D (D-Q1, D-Q2, D-Q3) of the
leg circuit 6. The addition/subtraction determination unit
15 13A determines whether the second duty cycles D-Vcf1, D-Vcf2
are to be added or subtracted, according to the switching
pattern SP. At this time, addition or subtraction is
determined such that the sum of the duty cycles D-Q1, D-Q2,
D-Q3 for the Q1, Q2, Q3 in the upper leg 6a is constant in
20 one cycle of the control cycle. That is, the sum of the duty
cycles D-Q1, D-Q2, D-Q3 is constant regardless of voltage
fluctuations of the first and the second DC capacitors Cf1,
Cf2, and is equal to the sum of the first duty cycles D-PFC
(corresponding components of the Q1, Q2, Q3).
25 [0079] An example of an operation of the
52
addition/subtraction determination unit 13A in the operation
range β1 will be described below.
FIG. 37 shows waveforms for illustrating control
for a case where, in the operation range β1, the voltage Vcf1
5 of the first DC capacitor Cf1 is higher than the command
value Vcf1* and the voltage Vcf2 of the second DC capacitor
Cf2 is higher than the command value Vcf2*, and both the
voltage Vcf1 and the voltage Vcf2 are reduced. FIG. 38 and
FIG. 39 are control block diagrams illustrating the control
10 in FIG. 37, and FIG. 38 is for the switching cycle S1 and FIG.
39 is for the switching cycle S2.
As shown in FIG. 37, in the switching cycle S1 in
the control cycle T, the timing t1 at which the Q1, Q2 are
switched off is shifted leftward in FIG. 37 to increase a
15 discharging section for the first DC capacitor Cf1, and the
timing t3 at which the Q3 is switched off is shifted
rightward in FIG. 37 to shorten the charging section for the
first DC capacitor Cf1. In the switching cycle S2 in the
control cycle T, the timing t5 at which the Q1 is switched
20 off is shifted leftward in FIG. 37 to increase the
discharging section for the second DC capacitor Cf2, and the
timing t7 at which the Q2, Q3 are switched off is shifted
rightward in FIG. 37 to shorten the charging section for the
second DC capacitor Cf2.
25 [0080] In the two switching cycles S1, S2 in the control
53
cycle T, each of the duty cycles D-Q1, D-Q2, D-Q3 is adjusted
for each of the switching cycles S1, S2. That is, each of
the duty cycles D-Q1, D-Q2, D-Q3 has a value corresponding to
two switching cycles and can have different values for each
5 of the switching cycles S1, S2.
In the case of the operation range β1, the duty
cycles D-Q1, D-Q2, D-Q3 are adjusted according to voltage
fluctuation of the first DC capacitor Cf1 in the switching
cycle S1, and the duty cycles D-Q1, D-Q2, D-Q3 are adjusted
10 according to voltage fluctuation of the second DC capacitor
Cf2 in the switching cycle S2.
[0081] As shown in FIG. 38, in a case where the duty
cycles D-Q1, D-Q2 are generated in the switching cycle S1,
the addition/subtraction determination unit 13A determines
15 that the second duty cycle D-Vcf1 is to be subtracted from
the first duty cycle D-PFC, to reduce the duty cycles D-Q1,
D-Q2. In a case where the duty cycle D-Q3 is generated, the
addition/subtraction determination unit 13A determines that
the second duty cycle D-Vcf1 is to be added to the first duty
20 cycle D-PFC, to increase the duty cycle D-Q3. In the
switching cycle S1, the second duty cycle D-Vcf2 for the
second DC capacitor Cf2 is not used and the corresponding
value is set to 0.
[0082] As shown in FIG. 39, in a case where the duty cycle
25 D-Q1 is generated in the switching cycle S2, the
54
addition/subtraction determination unit 13A determines that
the second duty cycle D-Vcf2 is to be subtracted from the
first duty cycle D-PFC, to reduce the duty cycle D-Q1. In a
case where the duty cycles D-Q2, D-Q3 are generated, the
5 addition/subtraction determination unit 13A determines that
the second duty cycle D-Vcf2 is to be added to the first duty
cycle D-PFC, to increase the duty cycles D-Q2, D-Q3. In the
switching cycle S2, the second duty cycle D-Vcf1 for the
first DC capacitor Cf1 is not used and the corresponding
10 value is set to 0.
[0083] FIG. 40 shows waveforms for illustrating control
for a case where, in the operation range β1, the voltage Vcf1
of the first DC capacitor Cf1 is less than the command value
Vcf1* and the voltage Vcf2 of the second DC capacitor Cf2 is
15 less than the command value Vcf2*, and both the voltage Vcf1
and the voltage Vcf2 are increased. FIG. 41 and FIG. 42 are
control block diagrams illustrating the control in FIG. 40.
FIG. 41 is for the switching cycle S1 and FIG. 42 is for the
switching cycle S2.
20 As shown in FIG. 40, in the switching cycle S1 in
the control cycle T, the timing t1 at which the Q1, Q2 are
switched off is shifted rightward in FIG. 40 to shorten the
discharging section for the first DC capacitor Cf1, and the
timing t3 at which the Q3 is switched off is shifted leftward
25 in FIG. 40 to increase the charging section for the first DC
55
capacitor Cf1. In the switching cycle S2 in the control
cycle T, the timing t5 at which the Q1 is switched off is
shifted rightward in FIG. 40 to shorten the discharging
section for the second DC capacitor Cf2, and the timing t7 at
5 which the Q2, Q3 are switched off is shifted leftward in FIG.
40 to increase the charging section for the second DC
capacitor Cf2.
[0084] As shown in FIG. 41, in a case where the duty
cycles D-Q1, D-Q2 are generated in the switching cycle S1,
10 the addition/subtraction determination unit 13A determines
that the second duty cycle D-Vcf1 is to be added to the first
duty cycle D-PFC to increase the duty cycles D-Q1, D-Q2. In
a case where the duty cycle D-Q3 is generated, the
addition/subtraction determination unit 13A determines that
15 the second duty cycle D-Vcf1 is to be subtracted from the
first duty cycle D-PFC to reduce the duty cycle D-Q3. In the
switching cycle S1, the second duty cycle D-Vcf2 for the
second DC capacitor Cf2 is not used and the corresponding
value is set to 0.
20 [0085] As shown in FIG. 42, in a case where the duty cycle
D-Q1 is generated in the switching cycle S2, the
addition/subtraction determination unit 13A determines that
the second duty cycle D-Vcf2 is to be added to the first duty
cycle D-PFC to increase the duty cycle D-Q1. In a case where
25 the duty cycles D-Q2, D-Q3 are generated, the
56
addition/subtraction determination unit 13A determines that
the second duty cycle D-Vcf2 is to be subtracted from the
first duty cycle D-PFC to reduce the duty cycles D-Q2, D-Q3.
In the switching cycle S2, the second duty cycle D-Vcf1 for
5 the first DC capacitor Cf1 is not used and the corresponding
value is set to 0.
[0086] In both the case shown in FIG. 37 to FIG. 39 and
the case shown in FIG. 40 to FIG. 42, each of the second duty
cycle D-Vcf1 and the second duty cycle D-Vcf2 is once added
10 to and once subtracted from the sum of the three duty cycles
D-Q1, D-Q2, D-Q3 in the control cycle. Therefore, the sum is
not changed and is constant. The sample and hold unit 28 in
the second controller 12A holds values of the second duty
cycles D-Vcf1, D-Vcf2 in one control cycle and outputs the
15 values. Therefore, in the calculation, the sum of the three
duty cycles D-Q1, D-Q2, D-Q3 can be assuredly made constant.
In a case where the sum of the duty cycles D-Q1, DQ2,
D-Q3 for the Q1, Q2, Q3 in the upper leg 6a is constant,
the sum of the duty cycles D-Q4, D-Q5, D-Q6 for the Q4, Q5,
20 Q6 in the lower leg 6b also becomes constant.
[0087] Thus, voltage control for each of the first and the
second DC capacitors Cf1, Cf2 can be performed for each
control cycle (two switching cycles). The sum of the three
duty cycles D-Q1, D-Q2, D-Q3 is constant regardless of
25 voltage fluctuations of the first and the second DC
57
capacitors Cf1, Cf2, and is equal to the sum of the first
duty cycles D-PFC. Therefore, interference with high power
factor control of the input current iac is significantly
suppressed.
5 [0088] In the above description, both the voltages Vcf1,
Vcf2 of the first and the second DC capacitors Cf1, Cf2 are
reduced or increased. However, either of them may be reduced
or increased. Alternatively, both of them may be controlled
in opposite directions.
10 For example, in a case where the first DC capacitor
Cf1 is charged or discharged and the second DC capacitor Cf2
is charged or discharged in one switching state in a certain
section as in the operation range β2 shown in FIG. 32, one of
the first and the second DC capacitors Cf1 and Cf2 in which
15 the deviation between the voltage Vcf1, Vcf2 and the command
value Vcf1*, Vcf2* is greater can be preferentially
controlled. Thus, more stable control can be continued.
[0089] As described above, in the present embodiment, the
power conversion circuit 1A includes two DC capacitors (the
20 first and the second DC capacitors Cf1, Cf2). The control
circuit 7A controls driving of the leg circuit 6 at a control
cycle corresponding to two cycles of the switching cycle.
The switching pattern SPA is used to control the input
current iac and control charging and discharging of the DC
25 capacitor Cf according to the first duty cycle D-PFC.
58
Furthermore, the addition/subtraction determination unit 13A
operates to add or subtract the second duty cycle D-Vcf to or
from the first duty cycle D-PFC, thereby suppressing voltage
fluctuations of the first and the second DC capacitors Cf1,
5 Cf2. Although the three duty cycles D-Q1, D-Q2, D-Q3 are
each adjusted so as to suppress voltage fluctuations of the
first and the second DC capacitors Cf1, Cf2, the sum in one
control cycle is not changed and is constant.
[0090] The voltage control for the first and the second DC
10 capacitors Cf1, Cf2 can be performed for each control cycle
(two switching cycles). Therefore, the charging/discharging
time constants of the first and the second DC capacitors Cf1,
Cf2 can be made equal to the control cycle. Thus, good
control responsiveness is maintained, and the capacitances of
15 the first and the second DC capacitors Cf1, Cf2 can be
reduced. The sum of the three duty cycles D-Q1, D-Q2, D-Q3
is constant regardless of voltage fluctuations of the first
and the second DC capacitors Cf1, Cf2 and is equal to the sum
of the first duty cycles D-PFC. Therefore, interference with
20 high power factor control of the input current iac is
significantly suppressed.
Therefore, interference between the high power
factor control of the input current iac and the voltage
control for the first and the second DC capacitors Cf1, Cf2
25 can be suppressed to perform both the controls with high
59
accuracy, and the capacitance and the size of each of the
first and the second DC capacitors Cf1, Cf2 can be reduced.
Thus, downsizing of the power conversion device 200 can be
promoted.
5 [0091] In embodiment 2, the power conversion circuit 1A
includes two DC capacitors (the first and the second DC
capacitors Cf1, Cf2). However, the number of the DC
capacitors may be greater than or equal to three.
In a case where N represents the number of the DC
10 capacitors in the power conversion circuit 1A, the control
cycle corresponds to the N switching cycles. The voltage
control for each DC capacitor can be similarly performed for
each control cycle. The N DC capacitors are disposed
sequentially from the center of the leg circuit 6 toward the
15 outer side. The closer the DC capacitor is to the outer side,
the higher the voltage is.
[0092] In embodiments 1 and 2, the control circuit 7, 7A
performs calculation such that the sum of the duty cycles D
of the switching elements in the upper leg 4a, 6a is constant
20 in one control cycle. However, the control circuit 7, 7A may
perform calculation such that the sum of the duty cycles D of
the switching elements in the lower leg 4b, 6b is constant in
one control cycle. In this case, the duty cycle D of the
switching element in the lower leg 4b, 6b is calculated and
25 used more preferentially than that in the upper leg 4a, 6a.
60
In each of the cases, the sum of the duty cycles D is
constant in the control cycle in both the upper and lower
legs.
[0093] Also in embodiment 2, the first duty cycle D-PFC
5 may be generated without using the feedforward control as in
embodiment 1.
Also in embodiment 2, the reactor L may be disposed
in any manner as long as the reactor L is inserted in the
current path between the AC power supply 2 and the leg
10 circuit 4, and, as shown in FIG. 23, the two reactors Lp, Ln
may be connected.
[0094] Embodiment 3.
FIG. 43 schematically illustrates a configuration
of a power conversion device according to embodiment 3.
15 As shown in FIG. 43, a power conversion device 300
includes a power conversion circuit 1B, and a control circuit
7B for performing output control for the power conversion
circuit 1B, and performs power conversion of AC power from
the AC power supply 2, to supply DC power to the load 5. The
20 power conversion circuit 1B consists of an AC/DC converter
circuit, and includes a rectification bridge circuit 30
connected to the AC power supply 2, the leg circuit 4, the DC
capacitor Cf, the smoothing capacitor Cdc, and the reactor L
for limiting the input current iac.
25 In this case, the rectification bridge circuit 30
61
and the control circuit 7B are different from those in
embodiment 1, and the other configurations are the same as in
embodiment 1. Therefore, the description is omitted as
appropriate.
5 [0095] The rectification bridge circuit 30 is a fullbridge
circuit composed of four diodes Da, Db, Dc, Dd, and
two AC terminals are connected to a first end and a second
end, respectively, of the AC power supply. A positive
electrode of the rectification bridge circuit 30 is connected
10 to a mid-point of the leg circuit 4 via the reactor L. A
negative electrode of the rectification bridge circuit 30 is
connected to a negative DC bus, that is, connected to a
negative electrode of the leg circuit 4 and a negative
electrode of the smoothing capacitor Cdc.
15 The rectification bridge circuit 30 performs fullwave
rectification for current inputted from the AC power
supply 2, and outputs a positive half wave only. In this
case, current flowing in the reactor L after the
rectification is the input current iac.
20 The rectification bridge circuit 30 may be
configured by using switching elements instead of the diodes
Da, Db, Dc, Dd. The same type of switching elements as those
used in the leg circuit 4 may be used.
[0096] The control circuit 7B has the same configuration
25 as in embodiment 1. In this case, the full-wave-rectified
62
input current iac is inputted to the mid-point of the leg
circuit 4. Therefore, two kinds of operation ranges are
obtained, and a different current path is formed in the power
conversion circuit 1B. However, the control operation by the
5 control circuit 7B is the same as in embodiment 1. Therefore,
the same effect as in embodiment 1 can be obtained.
[0097] The leg circuit 4 processes the full-wave-rectified
input current iac only and does not process a negative halfwave
current. Therefore, switching of the upper leg 4a may
10 be unnecessary.
[0098] FIG. 44 schematically illustrates a configuration
of another example of the power conversion device according
to embodiment 3.
As shown in FIG. 44, a power conversion device 300A
15 includes a power conversion circuit 1C, and a control circuit
7Ba for performing output control for the power conversion
circuit 1C. The power conversion circuit 1C includes the
rectification bridge circuit 30, a leg circuit 40, the DC
capacitor Cf, the smoothing capacitor Cdc, and the reactor L.
20 The power conversion device 300A uses the leg circuit 40
instead of the leg circuit 4 used in the power conversion
device 300 of embodiment 3. The leg circuit 40 is structured
such that semiconductor elements in an upper leg 40a are
composed of diodes De, Df, and only semiconductor elements in
25 a lower leg 40b are composed of the switching elements Q3, Q4.
63
[0099] In this case, the control circuit 7Ba generates
only a gate signal GQB (GQ3, GQ4) for the Q3, Q4 in the lower
leg 40b, and, at this time, the sum of the duty cycles D-Q3,
D-Q4 for the Q3, Q4 is made constant in one control cycle.
5 Thus, the same effect as in embodiment 1 can be obtained.
The number of the switching elements in the leg
circuit 40 can be reduced to obtain the leg circuit 40 with
low cost. Thus, cost of the power conversion device 300A can
be reduced.
10 [0100] Embodiment 4.
FIG. 45 schematically illustrates a configuration
of a power conversion device according to embodiment 4.
As shown in FIG. 45, a power conversion device 400
includes a power conversion circuit 1D, and a control circuit
15 7C for performing output control for the power conversion
circuit 1D, and performs power conversion of AC power from
the AC power supply 2, to supply DC power to the load 5. The
power conversion circuit 1D consists of an AC/DC converter
circuit, and includes the rectification bridge circuit 30
20 connected to the AC power supply 2, the leg circuit 6, the
first and the second DC capacitors Cf1, Cf2, the smoothing
capacitor Cdc, and the reactor L for limiting the input
current iac.
In this case, the rectification bridge circuit 30
25 and the control circuit 7C are different from those in
64
embodiment 2, and the other configurations are the same as in
embodiment 2. Therefore, the description is omitted as
appropriate.
[0101] The rectification bridge circuit 30 is the same as
5 that in embodiment 3, that is, is a full-bridge circuit
consisting of four diodes Da, Db, Dc, Dd. The two AC
terminals are connected to the first end and the second end,
respectively, of the AC power supply. A positive electrode
of the rectification bridge circuit 30 is connected to a mid10
point of the leg circuit 6 via the reactor L. A negative
electrode of the rectification bridge circuit 30 is connected
to a negative DC bus, that is, connected to a negative
electrode of the leg circuit 6 and a negative electrode of
the smoothing capacitor Cdc.
15 The rectification bridge circuit 30 performs fullwave
rectification for current inputted from the AC power
supply 2, and outputs a positive half wave only. In this
case, current flowing in the reactor L after the
rectification is the input current iac.
20 [0102] The control circuit 7C has the same configuration
as in embodiment 2. In this case, the full-wave-rectified
input current iac is inputted to the mid-point of the leg
circuit 6. Therefore, three kinds of operation ranges are
obtained, and a different current path is formed in the power
25 conversion circuit 1D. However, the control operation by the
65
control circuit 7C is the same as in embodiment 2. Therefore,
the same effect as in embodiment 2 can be obtained.
[0103] The leg circuit 6 processes the full-wave-rectified
input current iac only and does not process a negative half5
wave current. Therefore, switching of the upper leg 6a may
be unnecessary.
[0104] FIG. 46 schematically illustrates a configuration
of another example of the power conversion device according
to embodiment 4.
10 As shown in FIG. 46, a power conversion device 400A
includes a power conversion circuit 1E, and a control circuit
7Ca for performing output control for the power conversion
circuit 1E. The power conversion circuit 1E includes the
rectification bridge circuit 30, a leg circuit 60, the first
15 and the second DC capacitors Cf1, Cf2, the smoothing
capacitor Cdc, and the reactor L. The power conversion
device 400A uses the leg circuit 60 instead of the leg
circuit 6 used in the power conversion device 400 of
embodiment 4. The leg circuit 60 is structured such that
20 semiconductor elements in an upper leg 60a are composed of
diodes De, Df, Dg and only semiconductor elements in a lower
leg 60b are composed of the switching elements Q4, Q5, Q6.
[0105] In this case, the control circuit 7Ca generates
only a gate signal GQC (GQ4, GQ5, GQ6) for the Q4, Q5, Q6 in
25 the lower leg 60b, and, at this time, the sum of the duty
66
cycles D-Q4, D-Q5, D-Q6 for the Q4, Q5, Q6 is made constant
in one control cycle. Thus, the same effect as in embodiment
2 can be obtained.
The number of the switching elements in the leg
5 circuit 60 can be reduced to obtain the leg circuit 60 with
low cost. Thus, cost of the power conversion device 400A can
be reduced.
[0106] Although the disclosure is described above in terms
of various exemplary embodiments and implementations, it
10 should be understood that the various features, aspects, and
functionality described in one or more of the individual
embodiments are not limited in their applicability to the
particular embodiment with which they are described, but
instead can be applied, alone or in various combinations to
15 one or more of the embodiments of the disclosure.
It is therefore understood that numerous
modifications which have not been exemplified can be devised
without departing from the scope of the present disclosure.
For example, at least one of the constituent components may
20 be modified, added, or eliminated. At least one of the
constituent components mentioned in at least one of the
preferred embodiments may be selected and combined with the
constituent components mentioned in another preferred
embodiment.
25
67
DESCRIPTION OF THE REFERENCE CHARACTERS
[0107] 1, 1A, 1B, 1C, 1D power conversion circuit
2 AC power supply
3 rectification bridge circuit
5 4 leg circuit
4a upper leg
4b lower leg
6 leg circuit
6a upper leg
10 6b lower leg
7, 7A, 7B, 7Ba, 7C, 7Ca control circuit
10, 10A pattern generator
11, 11A first controller (high power factor
control calculator)
15 12, 12A second controller (capacitor voltage
control calculator)
13, 13A addition/subtraction determination unit
23a feedforward term
30 rectification bridge circuit
20 40 leg circuit
40a upper leg
40b lower leg
60 leg circuit
60a upper leg
25 60b lower leg
68
100, 200, 300, 300A, 400, 400A power conversion
device
α1 to α4, β1 to β6 operation range
A1 to K1, A2 to J2, A3 to K3 switching state
5 Cdc smoothing capacitor
Cf DC capacitor
Cf1 first DC capacitor
Cf2 second DC capacitor
De, Df, Dg diode (semiconductor element)
10 D-PFC first duty cycle
D-Vcf, D-Vcf1, D-Vcf2 second duty cycle
D-Q1 to D-Q6 duty cycle
iac input current
L, Lp, Ln reactor
15 Q1 to Q6 switching element
S1, S2 switching cycle
SP, SPA switching pattern
T control cycle
Vcf voltage of DC capacitor
20 Vcf1 voltage of first DC capacitor
Vcf2 voltage of second DC capacitor
Vdc voltage of smoothing capacitor
vac AC voltage
69
We CLAIM:
[1] A power conversion device comprising:
a power conversion circuit for converting AC power
5 from an AC power supply, to DC power, and outputting the DC
power; and
a control circuit for performing output control for
the power conversion circuit,
wherein the power conversion circuit includes:
10 a rectification bridge circuit connected to the AC
power supply;
a leg circuit including an upper leg and a lower
leg, connected in series, each of which includes a plurality
of semiconductor elements connected in series via connection
15 points, the plurality of semiconductor elements of at least
the lower leg being switching elements, the leg circuit
connected between DC buses and connected to the AC power
supply via the rectification bridge circuit;
at least one DC capacitor connected between the
20 connection point in the upper leg and the connection point in
the lower leg;
a reactor inserted in a current path between the AC
power supply and the leg circuit; and
a smoothing capacitor connected between the DC
25 buses;
70
and wherein the control circuit performs PWM
control of the leg circuit by generating a duty cycle so as
to cause a voltage of the DC capacitor to follow a command
value while controlling an input current from the AC power
5 supply, such that a sum of duty cycles corresponding to each
leg having the switching elements among the upper and the
lower legs, is constant in one cycle.
[2] The power conversion device according to claim 1,
10 wherein
the at least one DC capacitor includes N DC
capacitors which are a first to an N-th DC capacitors, the
first to the N-th DC capacitors being disposed sequentially
from a center of the leg circuit in an outward direction, and
15 the control circuit performs PWM control of the leg
circuit at a control cycle corresponding to N switching
cycles, such that the sum of the duty cycles is constant in
one cycle of the control cycle.
20 [3] The power conversion device according to claim 2,
wherein
the control circuit includes
a first controller for controlling the input
current and causing the power conversion circuit to output DC
25 power,
71
a second controller for causing a voltage of the
DC capacitor to follow the command value,
a pattern generator for generating a switching
pattern including a combination of switching states, of the
5 leg circuit, which vary in one cycle of the control cycle,
and
an addition/subtraction determination unit for
determining whether addition or subtraction is to be
performed,
10 the first controller generates a first duty cycle
according to the switching pattern from the pattern generator,
a second duty cycle generated by the second
controller is added to or subtracted from the first duty
cycle to calculate the duty cycle of the leg circuit, and
15 the addition/subtraction determination unit
determines, when the second duty cycle is added to or
subtracted from the first duty cycle, whether addition or
subtraction is to be performed according to the switching
pattern.
20
[4] The power conversion device according to claim 3,
wherein
the control circuit determines a plurality of
operation ranges based on a voltage relationship among a
25 voltage of the DC capacitor, a voltage of the AC power supply,
72
and a voltage of the smoothing capacitor, and
the pattern generator generates the switching
pattern according to each of the operation ranges.
5 [5] The power conversion device according to claim 3 or
claim 4, wherein the sum of the duty cycles corresponding to
each leg is equal to a sum of the first duty cycles.
[6] The power conversion device according to any one of
10 claim 3 to claim 5, wherein a plurality of sections
corresponding to the plurality of switching states of the
switching pattern is a combination formed by alternating
sections in which excitation of the reactor is performed and
sections in which the excitation is reset.
15
[7] The power conversion device according to any one of
claim 3 to claim 6, wherein
the control circuit performs control so as to cause
a voltage to follow the command value for each DC capacitor,
20 and
the number of charging sections and the number of
discharging sections are equal to each other for each DC
capacitor in the plurality of sections corresponding to the
plurality of switching states of the switching pattern.
25
73
[8] The power conversion device according to claim 7,
wherein the control circuit performs control so as to cause a
voltage to follow the command value for each DC capacitor
preferentially for a DC capacitor having a greater deviation
5 between a voltage of the DC capacitor and the command value.
[9] The power conversion device according to any one of
claim 3 to claim 8, wherein the first controller calculates a
feedforward term according to the switching pattern and uses
10 the feedforward term.
[10] The power conversion device according to any one of
claim 3 to claim 9, wherein the second duty cycle generated
by the second controller is fixed in one cycle of the control
15 cycle.
[11] The power conversion device according to any one of
claim 2 to claim 10, wherein the first to the N-th DC
capacitors are disposed such that a voltage is increased from
20 the center of the leg circuit in the outward direction.
[12] The power conversion device according to any one of
claim 1 to claim 11, wherein
the rectification bridge circuit is a half-bridge
25 circuit connected between the DC buses,
74
a mid-point of the half-bridge circuit is connected
to a first end of the AC power supply,
a mid-point of the leg circuit is connected to a
second end of the AC power supply, and
5 the plurality of semiconductor elements of the
upper leg are switching elements.
[13] The power conversion device according to any one of
claim 1 to claim 11, wherein
10 the rectification bridge circuit is a full-bridge
circuit including two AC terminals connected to a first end
and a second end, respectively, of the AC power supply, and
a positive electrode of the full-bridge circuit is
connected to a mid-point of the leg circuit.