FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
POWER CONVERTING DEVICE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION ORGANISED AND
EXISTING UNDER THE LAWS OF JAPAN, WHOSE ADDRESS IS 7-3,
MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310, JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED
2
DESCRIPTION
TECHNICAL FIELD
[0001] The present disclosure relates to a power
converting device.
5
BACKGROUND ART
[0002] An inverter is one type of power converting device.
The input of the inverter is DC voltage, and the output of
the inverter is AC voltage. Technologies in which an
10 induction electric motor is driven to be rotated by using a
two-level three-phase inverter, have been widely known. The
two-level three-phase inverter receives a PWM command pulse
generated by a controller and outputs two levels of voltages.
However, a time point at which the output voltage of the
15 inverter is changed differs from a corresponding time point
at which the PWM command pulse is changed. If the difference
is large, problems might arise in that: irregularity in
rotation of the induction electric motor occurs; or
electromagnetic noise increases. That is, although the
20 inverter generates an AC waveform (sine wave), a deviation
(harmonic) from an ideal sine wave leads to occurrence of
irregularity in rotation or increase in noise. Basically, a
command is given so as to generate a waveform similar to the
sine wave by correcting the difference between the command
25 and the output. However, a difference generated by
3
incomplete correction leads to a deviation from the sine wave.
One of causes of the difference is a dead time that
is set in order to prevent upper-arm and lower-arm
semiconductor switching elements of the inverter from being
5 simultaneously turned on. Another cause of the difference is
presence of delay time of operations of respective components
or a variation among the delay time.
[0003] There is a technology of Patent Document 1 as a
technology for solving the above problems. In Patent
10 Document 1, a voltage detection circuit is connected to an
output portion of an inverter. In addition, a voltage
division resistor is connected to a DC input portion of the
inverter, and a comparison reference voltage is generated.
The comparison reference voltage is approximately 1/2 of the
15 DC input voltage of the inverter. The voltage detection
circuit detects, by using the comparison reference voltage, a
time point at which the output voltage of the inverter has
been changed. Further, the controller receives the result of
the detection of the time point from the voltage detection
20 circuit and compensates for a dead time.
[0004] In addition, there is a technology of Patent
Document 2 as another technology. In Patent Document 2, an
upper-arm ON detection circuit and a lower-arm ON detection
circuit for respectively detecting ON states (5 V to 10 V) of
25 upper-arm semiconductor switching elements and lower-arm
4
semiconductor switching elements are connected to an output
portion of an inverter. If the output voltage of the
inverter is changed, the upper-arm ON detection circuit and
the lower-arm ON detection circuit respectively transmit
5 detection pulses. A controller calculates a time period that
is 1/2 of the difference in time point between the two
detection pulses. The controller obtains, on the basis of
the result of the calculation, a change time point
corresponding to a change time point of the output voltage of
10 the inverter on the basis of the standard of 1/2 of the DC
input voltage of the inverter. The controller compensates
for a dead time on the basis of the change time point
obtained by the calculation.
15 CITATION LIST
PATENT DOCUMENT
[0005] Patent Document 1: Japanese Laid-Open Patent
Publication No. 1994-121544
Patent Document 2: Japanese Laid-Open Patent
20 Publication No. 2000-295860
SUMMARY OF THE INVENTION
PROBLEMS TO BE SOLVED BY THE INVENTION
[0006] In the technology described in the above Patent
25 Document 1, components are attached to both the output
5
portion of the inverter and the input portion of the inverter.
Consequently, the power converting device has a complex
configuration and is upsized.
Meanwhile, in the technology described in the above
5 Patent Document 2, no component is attached to the input
portion of the inverter, and thus the power converting device
can be set to have a simple configuration. However, the
switching speeds of semiconductor switching elements of power
converting devices have been progressively increased owing to
10 improvement in the structures of semiconductors, usage of new
materials for the semiconductors, and the like, and the
increase in the switching speeds might lead to fluctuation of
the voltage between main terminals of each semiconductor
switching element due to a parasitic inductance component and
15 a parasitic capacitance component of the power converting
device. In the technology described in Patent Document 2,
the upper-arm ON detection circuit and the lower-arm ON
detection circuit may malfunction and transmit detection
pulses a plurality of times. Consequently, a problem exists
20 in that the accuracy of detecting a change time point of the
output voltage of the power converting device deteriorates.
[0007] The present disclosure has been made to solve the
above problems, and an object of the present disclosure is to
attain a simple configuration, and furthermore, to suppress
25 deterioration of the accuracy of detecting a change time
6
point of the output voltage of a power converting device even
if the switching speed of semiconductor switching elements is
increased.
5 MEANS FOR SOLVING THE PROBLEMS
[0008] A power converting device according to the present
disclosure includes
an upper-arm semiconductor switching element and a
lower-arm semiconductor switching element connected in series
10 between a positive-side input terminal and a negative-side
input terminal;
an upper-arm gate drive circuit configured to drive
the upper-arm semiconductor switching element and including
an upper-arm time point detection circuit configured to
15 detect a time point at which a voltage between main terminals
of the upper-arm semiconductor switching element has crossed
a first reference voltage;
a lower-arm gate drive circuit configured to drive
the lower-arm semiconductor switching element and including a
20 lower-arm time point detection circuit configured to detect a
time point at which a voltage between main terminals of the
lower-arm semiconductor switching element has crossed a
second reference voltage; and
a controller including
25 a calculator configured to calculate a change
7
time point of an output voltage outputted from a connection
portion between the upper-arm semiconductor switching element
and the lower-arm semiconductor switching element, and
a PWM command pulse generator configured to
5 generate, on the basis of information about the time point
calculated by the calculator, a PWM command pulse to be given
to the upper-arm gate drive circuit and the lower-arm gate
drive circuit, wherein
each of the upper-arm time point detection circuit
10 and the lower-arm time point detection circuit includes
a voltage division circuit configured to divide
or reduce the voltage between the main terminals of the
semiconductor switching element,
a comparator configured to compare an output
15 from the voltage division circuit with the corresponding one
of the first reference voltage and the second reference
voltage, and detect and output a time point at which the
voltage between the main terminals of the semiconductor
switching element has been changed, and
20 a filter disposed between the voltage division
circuit and the comparator and having a time constant smaller
than a change time period of the voltage between the main
terminals of the semiconductor switching element.
25 EFFECT OF THE INVENTION
8
[0009] In the power converting device according to the
present disclosure, it is possible to simplify a
configuration, and furthermore, to suppress deterioration of
the accuracy of detecting a change time point of the output
5 voltage of the power converting device even if the switching
speed of a semiconductor switching element is increased.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] [FIG. 1] FIG. 1 is a configuration diagram showing
10 a power converting device according to embodiment 1.
[FIG. 2] FIG. 2 is a time-series waveform diagram
for explaining operation of the power converting device
according to embodiment 1.
[FIG. 3] FIG. 3 is a configuration diagram showing
15 a gate drive circuit of a power converting device according
to embodiment 2.
[FIG. 4] FIG. 4 is a configuration diagram showing
a mask circuit in embodiment 2.
[FIG. 5] FIG. 5 is a configuration diagram showing
20 a gate drive circuit of the power converting device according
to embodiment 2.
[FIG. 6] FIG. 6 is a configuration diagram showing
a power converting device according to embodiment 3.
25 EMBODIMENTS FOR CARRYING OUT THE INVENTION
9
[0011] Embodiment 1
FIG. 1 is a configuration diagram showing a power
converting device according to embodiment 1. FIG. 2 is a
time-series waveform diagram for explaining operation of the
5 power converting device according to embodiment 1. A power
converting device 1 has a two-level inverter circuit. The
input of the power converting device 1 is DC voltage, and the
power converting device has two input portions which are a
positive-side inverter input portion (positive-side input
10 terminal) 2 and a negative-side inverter input portion
(negative-side input terminal) 3. Description will be given
below on the assumption of a case in which the potential of
the positive-side inverter input portion 2 is 1000 V and the
potential of the negative-side inverter input portion 3 is 0
15 V. A capacitor 4 is present between the positive-side
inverter input portion 2 and the negative-side inverter input
portion 3 and stores a DC voltage of 1000 V.
[0012] Further, an upper-arm semiconductor switching
element 5A and a lower-arm semiconductor switching element 5B
20 are connected in series between the positive-side inverter
input portion 2 and the negative-side inverter input portion
3 so as to form an upper-arm circuit and a lower-arm circuit,
respectively. As an output of the power converting device 1,
an inverter output 6 is outputted from a connection portion
25 5C between the upper-arm semiconductor switching element 5A
10
and the lower-arm semiconductor switching element 5B. It is
noted that, for example, an induction electric motor (not
shown in FIG. 1) is connected to a portion subsequent to the
inverter output 6. In a case in which a three-phase
5 induction electric motor is configured as the induction
electric motor, the inverter circuit shown in FIG. 1
indicates an inverter circuit for one of the three phases,
e.g., a U phase. And the same type of inverter circuit is
provided in addition to this inverter circuit also to each of
10 a V phase and a W phase, and these circuits are connected to
stator windings of the three-phase induction electric motor.
Alternatively, an electric motor other than the induction
electric motor may be used.
[0013] When the upper-arm semiconductor switching element
15 5A is turned on, the potential of the inverter output 6
becomes equal to the potential of the positive-side inverter
input portion 2. That is, the potential of the inverter
output 6 becomes 1000 V. When the lower-arm semiconductor
switching element 5B is turned on, the potential of the
20 inverter output 6 becomes equal to the potential of the
negative-side inverter input portion 3. That is, the
potential of the inverter output 6 becomes 0 V. In this
manner, the potential of the inverter output has two levels,
i.e., a high level and a low level.
25 It is noted that, as each semiconductor switching
11
element, a unipolar device such as a metal-oxidesemiconductor field-effect transistor (MOSFET) may be used,
or a bipolar device such as an insulated-gate bipolar
transistor (IGBT) may be used. As a material of the
5 semiconductor switching element, a widely-used silicon (Si)
material may be used, or a wide-bandgap semiconductor
material such as silicon carbide (SiC) may be used.
[0014] The switching speeds of semiconductor switching
elements of power converting devices have been progressively
10 increased owing to improvement in the structures of
semiconductors, usage of new materials for the semiconductors,
and the like. In bipolar devices such as insulated-gate
bipolar transistors (IGBTs), a carrier disappearance time
period is shortened, influence of a damping resistance
15 component is relatively weakened, and influence of a
parasitic capacitance component is relatively strengthened.
In addition, at the time of switching with small current, the
amount of accumulated carriers is small. Thus, while the
influence of the damping resistance component is relatively
20 weak, the influence of the parasitic capacitance component is
relatively strong. In unipolar devices such as metal-oxidesemiconductor field-effect transistors (MOSFETs), widebandgap semiconductor materials are used, and thus
semiconductor switching elements having a high voltage
25 durability have been progressively put into practical use.
12
In a unipolar device, in principle, influence of minority
carriers is not inflicted, and, while influence of a damping
resistance component is relatively weak, influence of a
parasitic capacitance component is relatively strong.
5 Therefore, the voltage between main terminals of each
semiconductor switching element may oscillate at the time of
switching owing to parasitic capacitance component of the
semiconductor switching elements and parasitic inductance
component on wires of the power converting device. In
10 association with the oscillation, the potential of the output
of the inverter also oscillates.
[0015] In FIG. 1, the power converting device 1 includes a
controller 7. The controller 7 includes a PWM command pulse
generator 8 which generates a pulse width modulation (PWM)
15 command pulse. The PWM command pulse is a signal serving as
a command as to a time point at which the level of the
inverter output 6 should be changed from the high level to
the low level, or a time point at which the level should be
changed from the low level to the high level. An upper-arm
20 gate drive circuit 9A receives the PWM command pulse via a
signal insulation circuit 10A. The upper-arm gate drive
circuit 9A includes a drive circuit 11A. In FIG. 2, “A”
indicates the waveform of a PWM command pulse, “B” indicates
an operation waveform of the upper-arm gate drive circuit,
25 “C” indicates an operation waveform of the lower-arm gate
13
drive circuit, “D” indicates the waveform of a voltage
between main terminals of the upper-arm semiconductor
switching element, “E” indicates the waveform of a voltage
between main terminals of the lower-arm semiconductor
5 switching element, and “F” indicates the voltage value of the
output of the inverter.
As shown in FIG. 2, when the level of the PWM
command pulse A is changed from the high level to the low
level, the drive circuit 11A immediately applies a negative
10 gate voltage to the gate of the upper-arm semiconductor
switching element 5A so that the upper-arm semiconductor
switching element 5A is driven to be turned off. When the
level of the PWM command pulse is changed from the low level
to the high level, the drive circuit 11A applies a positive
15 gate voltage to the gate of the upper-arm semiconductor
switching element 5A so that the semiconductor switching
element 5A is driven to be turned on, after the elapse of a
certain delay time period τ.
[0016] A lower-arm gate drive circuit 9B also receives the
20 PWM command pulse via a signal insulation circuit 10B. The
lower-arm gate drive circuit 9B also includes a drive circuit
11B. As shown in FIG. 2, when the level of the PWM command
pulse is changed from the low level to the high level, the
drive circuit 11B immediately applies the negative gate
25 voltage to the gate of the lower-arm semiconductor switching
14
element 5B so that the semiconductor switching element 5B is
driven to be turned off. When the level of the PWM command
pulse is changed from the high level to the low level, the
drive circuit 11B applies the positive gate voltage to the
5 gate of the lower-arm semiconductor switching element 5B so
that the semiconductor switching element 5B is driven to be
turned on, after the elapse of the certain delay time period
τ.
[0017] Owing to the presence of the certain delay time
10 period τ, there are periods in which both the upper-arm
semiconductor switching element 5A and the lower-arm
semiconductor switching element 5B are driven to be turned
off. Each of these periods τ is called a dead time. Since
the dead time is present, the upper-arm and lower-arm
15 semiconductor switching elements of the inverter can be
prevented from being simultaneously turned on. It is noted
that, although a configuration in which the dead time is set
by each gate drive circuit has been described above, a
configuration in which the dead time is set by the controller
20 7 may be used. In the PWM command pulse from the controller
7, the dead times are set after a PWM command pulse is
generated, so that a dead-time-set PWM command pulse for the
upper-arm gate drive circuit 9A and a dead-time-set PWM
command pulse for the lower-arm gate drive circuit 9B can be
25 generated.
15
[0018] Further, there is a delay time period (T1+T2 in FIG.
2) from a time point at which the voltage of the gate of the
semiconductor switching element is changed to a time point at
which the voltage between the main terminals of the
5 semiconductor switching element is changed. This delay time
period means a delay time period taken until a diode is
turned off by turning on the opposed arm (upper arm) while
the given arm (lower arm) is in a backflow mode. Here, “T1”
is a delay time period taken until the gate voltage is
10 actually reduced, and “T2” is a delay time period taken until
the diode is turned off by turning on the opposed arm.
The delay time period changes when a capacitor
voltage, a temperature, or the like is changed. In this
manner, a time point at which the level of the inverter
15 output voltage is changed from the high level to the low
level, and a time point at which the level is changed from
the low level to the high level, differ from corresponding
change time points of the PWM command pulse. A time width
during which the inverter output voltage is kept at the high
20 level, and a time width during which the inverter output
voltage is kept at the low level, differ from corresponding
time widths of the PWM command pulse. If these differences
are large, problems might arise in that: irregularity in
rotation of the induction electric motor occurs; or
25 electromagnetic noise increases.
16
[0019] Considering this, in the power converting device
according to embodiment 1, the upper-arm gate drive circuit
9A includes an upper-arm time point detection circuit 20A
which detects a time point at which the voltage between the
5 main terminals of the upper-arm semiconductor switching
element 5A has crossed a reference voltage (first reference
voltage). In FIG. 2, “X” indicates the reference voltage for
the upper-arm time point detection circuit, “Y” indicates a
reference voltage (second reference voltage) for a lower-arm
10 time point detection circuit, and “Z” indicates a voltage
that is 1/2 of the DC input voltage of the inverter. In
general, it is necessary that two voltage measurement points
are provided in order to measure a voltage. In conventional
technologies, one of the voltage measurement points is
15 provided in an inverter output portion so as to be apart from
a semiconductor switching element. Consequently, the voltage
of the semiconductor switching element cannot be measured
with high accuracy. Meanwhile, in the present embodiment,
the two voltage measurement points are provided in the main
20 terminals of each semiconductor switching element. Since the
two voltage measurement points are provided near the
semiconductor switching element, the voltage of the
semiconductor switching element can be measured with high
accuracy.
25 [0020] The magnitude of the reference voltage X is set to
17
be equal to or larger than a gate drive voltage to be applied
at the time of turning on the upper-arm semiconductor
switching element 5A. A manufacturer of each semiconductor
switching element sets a limitation value for the voltage
5 capable of being applied to the gate of the semiconductor
switching element. The limitation value is ±20 V in many
cases. The corresponding gate drive circuit applies the
positive/negative gate voltage to the gate of the
semiconductor switching element, and the value of the voltage
10 falls within the limitation value specified by the
manufacturer of the semiconductor switching element. In many
cases, the value of the gate drive voltage applied at the
time of turn-on is +10 V to +18 V, and the value of the gate
drive voltage at the time of turn-off is 0 V to -18 V.
15 [0021] A case in which the state of the upper-arm gate
drive circuit 9A is switched from a state of being driven to
be turned off to a state of being driven to be turned on,
will be contemplated. As described above, the voltage
between the main terminals of each semiconductor switching
20 element might fluctuate at the time of switching. In the
present embodiment, as shown in FIG. 2, the upper-arm time
point detection circuit 20A can detect, before the voltage
between the main terminals of the semiconductor switching
element takes a value smaller than the gate drive voltage to
25 be applied at the time of turn-on, a time point at which the
18
voltage between the main terminals of the semiconductor
switching element has crossed the reference voltage X. At
this time point, the semiconductor switching element has not
yet taken a complete ON state, and oscillation has not yet
5 started. Thus, the upper-arm time point detection circuit
20A does not perform detection a plurality of times and does
not malfunction. Therefore, even if the switching speed of
the semiconductor switching element is increased,
deterioration of the accuracy of detecting a change time
10 point of the output voltage of the power converting device
can be suppressed.
[0022] The upper-arm time point detection circuit 20A
includes a voltage division circuit 21A configured by a
passive component such as a resistor, a capacitor, or an
15 inductor. The voltage division circuit 21A divides or
reduces the voltage between the main terminals of the
semiconductor switching element so as to convert the voltage
into a relatively small voltage. Thus, a component having a
small voltage durability can be used as a circuit component
20 connected on a side subsequent to the voltage division
circuit 21A. The voltage division circuit performs
operations that are symmetric between the case in which the
level of the voltage between the main terminals of the
semiconductor switching element is changed from the high
25 level to the low level and the case in which the level is
19
changed from the low level to the high level. A resistor
voltage division circuit is the simplest example of the
voltage division circuit. Here, the resistor voltage
division means a circuit that reduces the voltage by
5 connecting a plurality of resistors in series. The
“operations” indicate motions in the divided voltage, and the
phrase “performs operations that are symmetric” means that a
time constant at which the voltage increases and a time
constant at which the voltage decreases are equal to each
10 other.
In the above configuration, it is possible to
suppress deterioration of the accuracy of detecting a change
time point of the output voltage of the power converting
device.
15 [0023] Here, a case in which the voltage division circuit
is implemented by a semiconductor component such as a diode
or a transistor, will be contemplated. Voltage division or
voltage reduction can be performed also by a semiconductor
component. However, in general, in operations of
20 semiconductor components, an operation at the time of turn-on
and an operation at the time of turn-off are asymmetric each
other. Thus, the voltage division circuit performs
operations that are asymmetric between the case in which the
level of the voltage between the main terminals of the
25 semiconductor switching element is changed from the high
20
level to the low level and the case in which the level is
changed from the low level to the high level. Therefore, the
accuracy of detecting a change time point of the output
voltage of the power converting device deteriorates.
5 [0024] The upper-arm time point detection circuit 20A
further includes a comparator 22A, and a filter 23A (low-pass
filter) disposed between the comparator 22A and the voltage
division circuit 21A and having a time constant smaller than
a change time period of the voltage between the main
10 terminals of the semiconductor switching element. The
comparator 22A receives an output from the voltage division
circuit 21A, compares the output and the reference voltage X ,
and detects and outputs a time point at which the voltage
between the main terminals of the upper-arm semiconductor
15 switching element 5A has been changed. An output from the
comparator 22A is inputted to the controller 7 via the signal
insulation circuit 10A of the gate drive circuit.
A circuit dedicated to information about a time
point may be prepared as the signal insulation circuit 10A.
20 That is, a signal insulation circuit for transmission of only
information about a time point is provided. Alternatively, a
circuit for transmitting error information about the gate
drive circuit to the controller 7 may be used as the signal
insulation circuit, and information about a time point may be
25 superimposed on the error information. That is, both the
21
error information and the information about the time point
are transmitted to the signal insulation circuit for error
information transmission. If the circuit for transmitting
error information about the gate drive circuit to the
5 controller 7 is used, it is possible to prevent the signal
insulation circuit from being upsized.
[0025] The filter 23A in the present embodiment is a lowpass filter, and thus, if a short pulse (a pulse having a
high frequency) having a time width smaller than the change
10 time period of the voltage between the main terminals of the
semiconductor switching element is inputted to the filter 23A,
the comparator 22A does not react to a high-frequency pulse.
Meanwhile, if a short pulse (a pulse having a low frequency)
having a time width not smaller than the change time period
15 of the voltage between the main terminals of the
semiconductor switching element is inputted to the filter 23A,
the comparator 22A reacts to a high-level period (see FIG. 2).
That is, even if a noise (having a high frequency) having a
time width smaller than the change time period of the voltage
20 between the main terminals of the semiconductor switching
element is inputted to the filter 23A, the noise is removed
by the filter 23A. Information that is lost by operation of
the filter 23A is information about a pulse having a time
width smaller than the change time period of the voltage
25 between the main terminals of the semiconductor switching
22
element. Meanwhile, information about a pulse having a time
width not smaller than the change time period of the voltage
between the main terminals of the semiconductor switching
element remains, and thus deterioration of the accuracy of
5 detecting a change time point of the output voltage of the
power converting device 1 can be suppressed.
[0026] Although the configuration and the operation of the
upper-arm gate drive circuit 9A have been described above, a
configuration and operation of the lower-arm gate drive
10 circuit 9B are also the same as those of the upper-arm gate
drive circuit 9A. Specifically, the lower-arm gate drive
circuit 9B includes a lower-arm time point detection circuit
20B, and the lower-arm time point detection circuit 20B
includes a voltage division circuit 21B, a comparator 22B,
15 and a filter 23B.
[0027] The controller 7 includes a calculator 30 which
calculates a change time point of the inverter output voltage.
The calculator 30 receives, from the upper-arm gate drive
circuit 9A, information about the time point at which the
20 voltage between the main terminals of the upper-arm
semiconductor switching element 5A has crossed the reference
voltage X. The calculator 30 further receives, from the
lower-arm gate drive circuit 9B, information about the time
point at which the voltage between the main terminals of the
25 lower-arm semiconductor switching element 5B has crossed the
23
reference voltage Y. The calculator 30 calculates a time
point that is 1/2 of the difference between the two pieces of
information about the time points. By calculating the time
point that is 1/2 of the difference between the two pieces of
5 information about the time points, an effective width of an
output pulse from the inverter is ascertained. Then, the
controller 7 identifies, on the basis of the result of the
calculation, a change time point corresponding to the change
time point of the inverter output voltage on the basis of the
10 standard of the voltage Z which is 1/2 of the DC input
voltage of the inverter. If a pulse width estimated on the
control side and a pulse width having been actually outputted
differ from each other, the difference causes a waveform
distortion. In order to eliminate such a waveform distortion,
15 it is effective to identify a time point at which the
inverter output voltage has reached a value that is 1/2 of
the DC input voltage. In this manner, the calculator 30
calculates a time point at which the inverter output voltage
has been changed. By setting so that the reference voltage X
20 and the reference voltage Y are equal to each other, in many
cases, it is possible to identify the time point at which the
inverter output voltage has reached a value that is 1/2 of
the DC input voltage. But, if the absolute value of a
temporal change rate dV/dt of the voltage between the main
25 terminals when the semiconductor switching element is turned
24
on and the said absolute value when the semiconductor
switching element is turned off significantly differ from
each other, the identification can be realized by adjusting
the difference between the reference voltage X and the
5 reference voltage Y.
[0028] The controller 7 includes the PWM command pulse
generator 8. The PWM command pulse generator 8 receives
information about the time point calculated by the calculator
30 and generates a PWM command pulse to be transmitted to
10 each of the upper-arm gate drive circuit 9A and the lower-arm
gate drive circuit 9B. The time point at which the level of
the inverter output voltage is changed from the high level to
the low level, and the time point at which the level is
changed from the low level to the high level, differ from the
15 corresponding change time points of the PWM command pulse. So
a PWM command pulse is generated on the basis of the
information about the time point calculated by the calculator
30 in order to compensate for the difference. Specifically,
a pulse width is adjusted. More specifically, a pulse
20 switching timing is adjusted to adjust the pulse width. For
example, the time point at which the level is changed from
the high level to the low level may be advanced, or the time
point at which the level is changed from the low level to the
high level may be delayed. Further both the advancement and
25 the delay may be used. It is noted that there are PWM
25
command pulse generating methods other than the above method.
[0029] In conventional technologies, components are
attached to both an output portion of an inverter and an
input portion of the inverter. Consequently, the power
5 converting device has a complex configuration and is upsized.
However, in the present embodiment, no component is attached
to the input portion of the inverter, and thus the
configuration of the power converting device can be
simplified.
10 [0030] Embodiment 2
FIG. 3 is a configuration diagram showing a gate
drive circuit of a power converting device according to
embodiment 2. The components other than the gate drive
circuit are the same as those in embodiment 1, and
15 descriptions thereof will be omitted. In addition, the
upper-arm gate drive circuit 9A and the lower-arm gate drive
circuit 9B have the same configuration, and the upper-arm
gate drive circuit 9A will be described below. The
configuration and the operation of the time point detection
20 circuit of the gate drive circuit are the same as those in
embodiment 1, and descriptions thereof will be omitted.
[0031] As a character of the present embodiment, the gate
drive circuit includes a short-circuit detection circuit
which performs detection as to whether or not a short-circuit
25 fault of the semiconductor switching element has occurred.
26
The short-circuit detection circuit shares components with
the time point detection circuit, and these components are
referred to as shared components. The shared components
include at least the voltage division circuit.
5 [0032] A case in which the power converting device is
normally operated, i.e., a case in which no short-circuit
fault of the semiconductor switching element has occurred,
will be contemplated. Here, the short-circuit fault of the
semiconductor switching element means simultaneous electric
10 conduction through the upper-arm semiconductor switching
element 5A and the lower-arm semiconductor switching element
5B. In FIG. 3, when the upper-arm semiconductor switching
element 5A is driven to be turned on by the upper-arm gate
drive circuit 9A, the upper-arm semiconductor switching
15 element 5A takes an ON state. Thus, the voltage between the
main terminals of the upper-arm semiconductor switching
element 5A becomes a relatively low voltage. On the other
hand, a case in which a short-circuit fault of the
semiconductor switching element has occurred will be
20 contemplated. Although the upper-arm semiconductor switching
element 5A is driven to be turned on by the upper-arm gate
drive circuit 9A, a large short-circuit current flows through
the upper-arm semiconductor switching element 5A. Thus, the
voltage between the main terminals of the upper-arm
25 semiconductor switching element 5A becomes a relatively high
27
voltage.
[0033] The voltage division circuit 21A divides or reduces
the voltage between the main terminals of the upper-arm
semiconductor switching element 5A so as to convert the
5 voltage into a relatively small voltage. Thus, if an upperarm short-circuit detection circuit 40A shares the voltage
division circuit 21A with the upper-arm time point detection
circuit 20A and receives the output from the voltage division
circuit 21A, the upper-arm short-circuit detection circuit
10 40A can obtain information about the voltage between the main
terminals of the upper-arm semiconductor switching element 5A.
In the configuration of the upper-arm short-circuit detection
circuit 40A shown in FIG. 3, a short-circuit detection
comparator 41A receives the output from the voltage division
15 circuit 21A via a short-circuit detection filter 42A. A time
constant of the short-circuit detection filter 42A has to be
large so as to prevent occurrence of a malfunction in which
occurrence of a short-circuit fault is detected despite the
fact that no short-circuit fault has occurred. The time
20 constant is often set to become a value not smaller than the
change time period of the voltage between the main terminals
of the semiconductor switching element.
[0034] Meanwhile, the time constant of the short-circuit
detection filter 42A also has to be small such that
25 occurrence of a short-circuit fault can be detected early.
28
In this manner, the time constant of the short-circuit
detection filter 42A is adjusted so as to be suitable for
short-circuit detection. The short-circuit detection
comparator 41A has a short-circuit detection reference
5 voltage 43A. As described above, the voltage between the
main terminals of the semiconductor switching element becomes
a relatively high voltage or a relatively low voltage
depending on whether or not a short-circuit fault has
occurred. The short-circuit detection reference voltage 43A
10 is adjusted so as to enable determination as to whether or
not a short-circuit fault has occurred.
[0035] In the configuration of the upper-arm short-circuit
detection circuit 40A shown in FIG. 3, the output from the
short-circuit detection comparator 41A is transmitted to the
15 controller 7 via a mask circuit 44A and the signal insulation
circuit 10A of the upper-arm gate drive circuit 9A. FIG. 4
is a configuration diagram showing the mask circuit 44A.
Here, the mask circuit is a circuit for preventing
transmission of a signal. In the case of the present
20 embodiment, the mask circuit is a circuit for preventing
transmission of a short-circuit detection signal in the case
in which no short-circuit has occurred.
When the semiconductor switching element is being
driven to be turned off, the semiconductor switching element
25 is in an OFF state. Even when the voltage between the main
29
terminals of the semiconductor switching element has become a
relatively high voltage, this relatively high voltage is not
an abnormal voltage and does not mean that a short-circuit
fault has occurred. Meanwhile, in an intermediate period
5 during which the state of the semiconductor switching element
is switched from a state of being driven to be turned off to
a state of being driven to be turned on, the voltage between
the main terminals of the semiconductor switching element is
a relatively high voltage. This relatively high voltage is
10 not an abnormal voltage and does not mean that a shortcircuit fault has occurred. The mask circuit 44A receives
information about the driven state of the semiconductor
switching element and performs a masking operation such that
the output from the short-circuit detection comparator 41A is
15 not transmitted to the signal insulation circuit 10A in a
situation in which no short-circuit fault has occurred.
[0036] In this manner, the upper-arm short-circuit
detection circuit 40A can detect occurrence of a shortcircuit fault of the upper-arm semiconductor switching
20 element 5A. If the controller 7 receives information about
occurrence of the short-circuit fault from the upper-arm
short-circuit detection circuit 40A, the controller 7 takes a
countermeasure such as transmission of an OFF command to all
the semiconductor switching elements in order to stop the
25 flow of the short-circuit current. It is noted that the
30
upper-arm short-circuit detection circuit 40A may directly
transmit the information about occurrence of the shortcircuit fault to the drive circuit 11A so that the upper-arm
semiconductor switching element 5A is driven to be turned off
5 by the drive circuit 11A.
[0037] Here, a case in which the time point detection
circuit includes the voltage division circuit and the shortcircuit detection circuit also includes a voltage division
circuit for short-circuit detection, will be contemplated.
10 Since the voltage between the main terminals of the
semiconductor switching element is applied to the two voltage
division circuits, it is necessary to provide insulation
distance. Therefore, the distance between each voltage
division circuit and the main terminals of the semiconductor
15 switching element is elongated. Consequently, the time point
detection circuit cannot measure the voltage of the
semiconductor switching element by high accuracy. Meanwhile,
the upper-arm gate drive circuit 9A configured as shown in
FIG. 3 includes the upper-arm short-circuit detection circuit
20 40A which performs detection as to whether or not a shortcircuit fault of the upper-arm semiconductor switching
element 5A has occurred, the upper-arm short-circuit
detection circuit 40A shares components with the upper-arm
time point detection circuit 20A, and the shared components
25 include the voltage division circuit 21A. Thus, the upper-
31
arm gate drive circuit 9A can be downsized. In addition, the
voltage division circuit 21A can be disposed near the main
terminals of the upper-arm semiconductor switching element 5A.
Therefore, occurrence of a short-circuit fault can be
5 detected, and deterioration of the accuracy of detecting a
change time point of the output voltage of the power
converting device 1 can be suppressed.
[0038] FIG. 5 is a configuration diagram showing another
gate drive circuit of the power converting device according
10 to embodiment 2. The configuration and the operation of the
upper-arm time point detection circuit 20A in the upper-arm
gate drive circuit 9A are the same as those shown in FIG. 3,
and descriptions thereof will be omitted. The difference
from the gate drive circuit shown in FIG. 3 is that the
15 voltage division circuit is not the only shared component.
An upper-arm short-circuit detection circuit 50A in FIG. 5
shares, as shared components, the voltage division circuit
21A, the filter 23A, the comparator 22A, and the reference
voltage X of the upper-arm time point detection circuit 20A.
20 The upper-arm time point detection circuit 20A detects a time
point at which the voltage between the main terminals of the
upper-arm semiconductor switching element 5A has been changed.
Thus, the short-circuit detection reference voltage value of
the upper-arm short-circuit detection circuit 50A is used as
25 the reference voltage value of the upper-arm time point
32
detection circuit 20A, further the upper-arm time point
detection circuit 20A can perform a detection operation.
Therefore, the components can be shared as shown in the
configuration shown in FIG. 5.
5 [0039] However, a short-circuit detection filter 51A of
the upper-arm short-circuit detection circuit 50A has to be
adjusted for short-circuit detection and cannot be used as a
shared component. If the filter 23A, for the time point
detection circuit, having a relatively small time constant is
10 connected to a first stage and the short-circuit detection
filter 51A having a relatively large time constant is
disposed on a second stage, both the time point detection
circuit and the short-circuit detection circuit can be
realized. Accordingly, as shown in FIG. 5, the upper-arm
15 short-circuit detection circuit 50A includes the shortcircuit detection filter 51A and a mask circuit 52A. Further,
the short-circuit detection filter 51A has a time constant
not smaller than the change time period of the voltage
between the main terminals of the semiconductor switching
20 element 5A. The output from the comparator 22A of the upperarm time point detection circuit 20A passes the signal
insulation circuit 10A via the short-circuit detection filter
51A and the mask circuit 52A and is transmitted to the
controller 7.
25 As described above, the upper-arm gate drive
33
circuit 9A includes the short-circuit detection circuit 50A
which detects occurrence of a short-circuit fault of the
semiconductor switching element 5A. Further, the shortcircuit detection circuit 50A receives the output from the
5 comparator 22A via the short-circuit detection filter 51A
having a time constant not smaller than the change time
period of the voltage between the main terminals of the
semiconductor switching element 5A.
[0040] In the configuration shown in FIG. 5, there are
10 many shared components, and thus both the upper-arm time
point detection circuit 20A and the upper-arm short-circuit
detection circuit 50A can be disposed near the main terminals
of the upper-arm semiconductor switching element 5A.
Therefore, the upper-arm gate drive circuit 9A can be
15 downsized. In addition, occurrence of a short-circuit fault
can be detected, and deterioration of the accuracy of
detecting a change time point of the output voltage of the
power converting device 1 can be suppressed.
[0041] Embodiment 3
20 FIG. 6 is a configuration diagram showing a power
converting device according to embodiment 3. In the present
embodiment, a first power converting device 1A, a second
power converting device 1B, and the controller 7 are provided.
The configuration of each of the first power converting
25 device 1A and the second power converting device 1B is the
34
same as the configuration of the power converting device 1
described in embodiment 1, and thus descriptions thereof will
be omitted.
A positive-side inverter input portion 2A of the
5 first power converting device 1A and a positive-side inverter
input portion 2B of the second power converting device 1B may
be connected to each other, and a negative-side inverter
input portion 3A of the first power converting device 1A and
a negative-side inverter input portion 3B of the second power
10 converting device 1B may be connected to each other. In this
case, the DC voltage value of the input of the first power
converting device 1A and the DC voltage value of the input of
the second power converting device 1B are equal to each other.
Further, a capacitor 4A between the two input portions in the
15 first power converting device 1A may be shared with the
second power converting device 1B, and a capacitor 4B between
the two input portions in the second power converting device
1B may be shared with the first power converting device 1A.
An inverter output 6A of the first power converting
20 device 1A and an inverter output 6B of the second power
converting device 1B can be connected to, for example, a
double-three-phase induction electric motor.
[0042] The controller 7 includes: a first calculator 30A
which calculates a time point at which an output voltage of
25 the first power converting device 1A has been changed; and a
35
second calculator 30B which calculates a time point at which
an output voltage of the second power converting device 1B
has been changed. The controller 7 includes the PWM command
pulse generator 8 which receives information about the time
5 points calculated by the first calculator 30A and the second
calculator 30B and which generates PWM command pulses to be
given to the first power converting device 1A and the second
power converting device 1B.
A time point at which the inverter output voltage
10 of the first power converting device 1A is changed, and a
time point at which the inverter output voltage of the second
power converting device 1B is changed, differ from each other,
and the PWM command pulse generator 8 generates the PWM
pulses so as to compensate for the difference.
15 [0043] Therefore, a time point at which the level of the
inverter output voltage of the first power converting device
1A is changed from the high level to the low level, and a
time point at which the level of the inverter output voltage
of the second power converting device 1B is changed from the
20 high level to the low level, can be set so as to coincide
with each other. Alternatively, a time point at which the
level of the inverter output voltage of the first power
converting device 1A is changed from the high level to the
low level, and a time point at which the level of the
25 inverter output voltage of the second power converting device
36
1B is changed from the low level to the high level, can also
be set so as to coincide with each other. Thus, when the
first power converting device 1A and the second power
converting device 1B are provided, irregularity in rotation
5 of the induction electric motor can be suppressed. Further,
electromagnetic noise can be suppressed.
It is noted that, although a case in which two
power converting devices, i.e., the first power converting
device 1A and the second power converting device 1B, are
10 provided has been described above, three or more power
converting devices may be provided.
[0044] In the above embodiments 1 to 3, it is possible to
attain a simple configuration, and furthermore, it is
possible to suppress deterioration of the accuracy of
15 detecting a change time point of the output voltage of a
power converting device even if the switching speed of
semiconductor switching elements is increased.
As described in each of the above embodiments, the
power converting device includes a controller and gate drive
20 circuits which include detection circuits for detecting a
time point at which the voltage of the semiconductor
switching element has been changed. In the power converting
device, a time point at which the inverter output voltage has
been changed is detected by high accuracy, and a difference
25 in the time point is corrected. Therefore, the present
37
disclosure is useful for correcting a dead time or
cooperative control of a plurality of inverters.
[0045] For example, there is a case in which, in a railway
vehicle, a plurality of electric motors are used, and a large
5 number of power converting devices for controlling the
electric motors are also used. In such a case, it is
required to attain uniformity in rotation among the plurality
of electric motors by suppressing irregularities in rotation
of the individual electric motors. The present disclosure
10 satisfies this requirement.
In addition, the present disclosure is useful also
in the case of assuming electrification of an aircraft. That
is, the accuracy of detecting a change time point of the
output voltage of the power converting device is improved,
15 and thus each gate drive circuit can be downsized. Therefore,
the weight of the entire device can be reduced. Further,
occurrence of a short-circuit fault can also be detected,
whereby improvement in reliability can also be expected.
Likewise, on the assumption of a case in which the power
20 converting device is used for an electrically-propelled ship
or the like, the present disclosure is useful also in the
case in which a plurality of propulsion motors are controlled
in a coordinated way.
[0046] Although the disclosure is described above in terms
25 of various exemplary embodiments and implementations, it
38
should be understood that the various features, aspects, and
functionality described in one or more of the individual
embodiments are not limited in their applicability to the
particular embodiment with which they are described, but they
5 can be applied, alone or in various combinations to one or
more of the embodiments of the disclosure.
It is therefore understood that numerous
modifications which have not been exemplified can be devised
without departing from the scope of the specification of the
10 present disclosure. For example, at least one of the
constituent components may be modified, added, or eliminated.
At least one of the constituent components mentioned in at
least one of the preferred embodiments may be selected and
combined with the constituent components mentioned in another
15 preferred embodiment.
DESCRIPTION OF THE REFERENCE CHARACTERS
[0047] 1, 1A, 1B power converting device
2 positive-side inverter input
20 3 negative-side inverter input
5A, 5B semiconductor switching element
7 controller
8 PWM command pulse generator
9A upper-arm gate drive circuit
25 9B lower-arm gate drive circuit
39
20A upper-arm time point detection circuit
20B lower-arm time point detection circuit
21A, 21B voltage division circuit
22A, 22B comparator
5 23A, 23B filter
30 calculator
40, 50 short-circuit detection circuit

We Claim:
[1] A power converting device comprising:
an upper-arm semiconductor switching element and a
lower-arm semiconductor switching element connected in series
5 between a positive-side input terminal and a negative-side
input terminal;
an upper-arm gate drive circuit configured to drive
the upper-arm semiconductor switching element and including
an upper-arm time point detection circuit configured to
10 detect a time point at which a voltage between main terminals
of the upper-arm semiconductor switching element has crossed
a first reference voltage;
a lower-arm gate drive circuit configured to drive
the lower-arm semiconductor switching element and including a
15 lower-arm time point detection circuit configured to detect a
time point at which a voltage between main terminals of the
lower-arm semiconductor switching element has crossed a
second reference voltage; and
a controller including
20 a calculator configured to calculate a change
time point of an output voltage outputted from a connection
portion between the upper-arm semiconductor switching element
and the lower-arm semiconductor switching element, and
a PWM command pulse generator configured to
25 generate, on the basis of information about the time point
41
calculated by the calculator, a PWM command pulse to be given
to the upper-arm gate drive circuit and the lower-arm gate
drive circuit, wherein
each of the upper-arm time point detection circuit
5 and the lower-arm time point detection circuit includes
a voltage division circuit configured to divide
or reduce the voltage between the main terminals of the
semiconductor switching element,
a comparator configured to compare an output
10 from the voltage division circuit with the corresponding one
of the first reference voltage and the second reference
voltage, and detect and output a time point at which the
voltage between the main terminals of the semiconductor
switching element has been changed, and
15 a filter disposed between the voltage division
circuit and the comparator and having a time constant smaller
than a change time period of the voltage between the main
terminals of the semiconductor switching element.
20 [2] The power converting device according to claim 1,
wherein a magnitude of each of the first reference voltage
and the second reference voltage is set to be equal to or
larger than a gate drive voltage to be applied at a time of
turning on the semiconductor switching element.
25
42
[3] The power converting device according to claim 1 or
2, wherein
each of the upper-arm gate drive circuit and the
lower-arm gate drive circuit further includes a short-circuit
5 detection circuit configured to detect occurrence of a shortcircuit fault of the semiconductor switching element,
the short-circuit detection circuit shares
components with the upper-arm time point detection circuit
and the lower-arm time point detection circuit, and
10 the shared components include at least the voltage
division circuit.
[4] The power converting device according to claim 1 or
2, wherein
15 each of the upper-arm gate drive circuit and the
lower-arm gate drive circuit further includes a short-circuit
detection circuit configured to detect occurrence of a shortcircuit fault of the semiconductor switching element, and
the short-circuit detection circuit receives an
20 output from the comparator via a short-circuit detection
filter having a time constant not smaller than the change
time period of the voltage between the main terminals of the
semiconductor switching element.
25 [5] A power converting apparatus comprising
43
a plurality of power converting devices each of
which is the power converting device according to any one of
claims 1 to 4, wherein
the controller includes
5 a plurality of calculators configured to
calculate time points at which output voltages of the
plurality of respective power converting devices have been
changed, and
a PWM command pulse generator configured to
10 generate, on the basis of information about the time points
calculated by the plurality of calculators, PWM command
pulses to be given to the plurality of power converting
devices.