Claims:1. A processor comprising:
a cryptographic accelerator;
a video accelerator;
a memory controller;
a first plurality of cores;
a second plurality of cores, wherein the second plurality of cores heterogeneous to and having a lower power consumption than the first plurality of cores;
an interconnect to couple the first plurality of cores and the second plurality of cores;
a shared cache memory coupled to at least the first plurality of cores; and
logic to cause a core of the second plurality of cores to execute an operation, wherein based at least in part on a performance level of the core of the second plurality of cores, the logic is to cause an execution state of the core of the second plurality of cores to be transferred to a core of the first plurality of cores to enable the core of the first plurality of cores to execute the operation.

2. The processor of claim 1, wherein the logic is to cause the core of the second plurality of cores and not the core of the first plurality of cores to be woken in response to an interrupt when the core of the first plurality of cores and the core of the second plurality of cores are in a low power state.
, Description:RELATED APPLICATION; PRIORITY CLAIM
This patent application is related to and claims priority from India Patent Application No. 1367/CHENP/2014, filed 20 February 2014, entitled “POWER EFFICIENT PROCESSOR ARCHITECTURE”.

Background
Typically, a processor uses a power saving sleep mode such as in accordance with an Advanced Configuration and Power Interface (ACPI) standard (e.g., Rev. 3.0b, published October 10, 2006) when possible. These so-called C-state core low power states (ACPI C-states) in addition to voltage and frequency scaling (DVFS or ACPI performance state (P-states)) can save power when a core is idle or not fully utilized. However, even in a multi-core processor context, a core is often woken from an efficient sleep state to perform a relatively simple operation, and is then returned to the sleep state. This operation can adversely affect power efficiency, as there is a cost in both latency and power consumption for exiting and returning to low power states. During the state transition power may be consumed in some types of processors without useful work being accomplished, to the detriment of power efficiency.
Examples of operations to be handled upon exiting a low power state include keyboard inputs, timer interrupts, network interrupts and so on. To handle these operations in a power sensitive manner, current operating systems (OSs) change program behavior by processing larger amounts of data at a time, or moving to a tickless OS where there are no periodic timer interrupts, and only sporadic programmed ones. Another strategy is to use timer coalescing, where multiple interrupts are grouped and handled at the same time. But in addition to changing a program’s behavior, all of these options raise complexity and still can lead to power inefficient operation. Further, some types of software (e.g., media playback) may make attempts to defeat hardware power efficiency mechanisms by requesting frequent, periodic wakes regardless of how much work needs to be accomplished. Thus, the tickless/timer coalescing strategies can save some power by reducing unnecessary wakes from deep C-states, but they require invasive changes to the OS and may take a significant amount of time to propagate through a computing ecosystem, as such changes are not implemented until a new version of an operating system is distributed.