Claims:1. An apparatus comprising:
an n-type high-side field effect transistor (HSFET) coupled to a first power supply rail and an inductor;
an n-type low-side field effect transistor (LSFET) coupled in series with the HSFET and coupled to a second supply rail;
a first driver to drive the HSFET, the first driver powered via a third supply rail, and coupled to the inductor;
a second driver to drive the LSFET, the second driver powered via a fourth supply rail, and coupled to the second supply rail; and
a bootstrap circuit including:
a capacitor coupled to the inductor and the third supply rail; and
a switch coupled to the capacitor and the fourth supply rail.
, Description:BACKGROUND
[0001] Inverting buck-boost DC-DC converter comprises an n-type high-side field effect transistor (HSFET) switch which requires a bootstrap circuit to supply corresponding high-side driver(s) to ensure correct n-type HSFET switch operation. Conventional bootstrap circuit fails to work reliably when a wide input supply (e.g., 1.9 V to 5.5 V) and output voltage (e.g., 0 V to -6 V) range of the inverting buck-boost DC-DC converter is considered.
[0002] When an inverting buck-boost DC-DC converter comprises a p-type HSFET, the p-type HSFET becomes highly resistive (e.g., when an input supply is less than 3 V). To compensate for this high resistance, the size of the p-type HSFET is increased (e.g., the width is increased) to support full loading conditions. When input power supply varies highly (e.g., 2 V to 5.5 V), both high resistance and/or large size for the p-type HSFET make the inverting buck-boost DC-DC converter uncompetitive.
[0003] When an inverting buck-boost DC-DC converter comprises an n-type HSFET, the bootstrap circuit causes signals for HSFET driver to be level-shifted to a floating domain - between bootstrap supply VBoot and inductor voltage, Vlx (or simply Lx). For an inverting buck-boost DC-DC converter, the wide range of input output voltages makes the level-shifting complex. For example, for an input power supply Vin of about 1.9 V to 5.5 V, output power supply Vout of about -3 V to -6 V, and with gate drive (e.g., voltage of Bootstrap capacitance) maintained at 4 V, level-shifting is expected to take care of following cases of voltage domain transitions: First case, maximum Vlx (LX) swing is -6 V to 5.5 V and for VBoot is -2 V to 9.5 V; Second case, minimum Vlx swing is -2 V to 1.9 V and for VBoot is 2 V to 5.9 V; and Third case, Vlx swing is 0 V to 1.9 V and for VBoot is 0 V to 3.8 V for startup. To support high voltage without reliability concerns, either cascode devices or clamps are used for protection but both have disadvantages associated with them. For example, cascode devices cannot support low supply voltage because of headroom issues while clamps leak constantly making it high power level-shifter.

BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0005] Fig. 1 illustrates a portion of an inverting DC-DC converter with a bootstrap circuit that overstresses an n-type high-side field effect transistor switch (HSFET).
[0006] Fig. 2 illustrates a portion of an inverting DC-DC converter with bootstrap circuit that generates constant gate-to-source voltage (VGS) across the n-type HSFET, in accordance with some embodiments.
[0007] Fig. 3 illustrates a bootstrap switch in the bootstrap circuit, where the bootstrap switch may cause a forward bias bulk-to-substrate diode.
[0008] Fig. 4 illustrates a bootstrap switch with dynamic bulk biasing, in accordance with some embodiments.
[0009] Fig. 5 illustrates a timing diagram of the bootstrap switch of Fig. 4 during startup and steady-state, in accordance with some embodiments.
[0010] Fig. 6 illustrates an open loop supply generator for the bootstrap circuit, in accordance with some embodiments.
[0011] Fig. 7 illustrates a closed loop supply generator for the bootstrap circuit, in accordance with some embodiments.
[0012] Fig. 8 illustrates a timing diagram of a simulation of the bootstrap circuit, in accordance with embodiments.
[0013] Fig. 9 illustrates an inverting DC-DC converter with p-type HSFET.
[0014] Fig. 10 illustrates an inverting DC-DC converter with substantially constant gate drive for the p-type HSFET, in accordance with some embodiments.
[0015] Fig. 11 illustrates an open loop supply generator to generate a supply for the driver of the p-type HSFET, in accordance with some embodiments.
[0016] Fig. 12 illustrates a closed loop supply generator to generate a supply for the driver of the p-type HSFET, in accordance with some embodiments.
[0017] Fig. 13 illustrates a portion of an inverting DC-DC converter with a bootstrap circuit and various voltage domains.
[0018] Fig. 14 illustrates a level-shifting scheme for driving the n-type HSFET, in accordance with some embodiments.
[0019] Fig. 15 illustrates a supply generator to generate one of the supplies for the level-shifting scheme for driving the n-type HSFET, in accordance with some embodiments.
[0020] Fig. 16 illustrates a circuit schematic of the level-shifter for the inverting DC-DC converter, in accordance with some embodiments.
[0021] Fig. 17 illustrates a plot showing operation of the level-shifter for the inverting DC-DC converter, in accordance with some embodiments.
[0022] Fig. 18 illustrates a smart device or a computer system or an SoC (System-on-Chip) coupled to a power management integrated circuit (PMIC) which includes the inverting DC-DC converter of various embodiments, in accordance with various embodiments.

DETAILED DESCRIPTION
[0023] Various embodiments improve reliability of an n-type high-side field effect transistor switch (HSFET) for an inverting DC-DC converter. In some embodiments, a derivative supply voltage (VDDL) is generated and provided to a switch of a bootstrap circuitry instead of an input power supply rail VDD_PWR or Vin. As such, a VBoot supply level remains constant irrespective of the output voltage Vout and VDD_PWR operating conditions, where VBoot supply level is provided to the HSFET driver. The derivative supply voltage VDDL becomes positive and negative during startup and steady-state conditions, respectively. Hence, dynamic biasing inside the switch ensures no reliability issues under all operating conditions.