Claims:1. An apparatus comprising:
an interconnect fabric;
a plurality of processor cores, wherein each processor core of the plurality of processor cores is coupled to one another via the interconnect fabric;
a first wake circuitry to wake up a first circuitry;
a second wake circuitry to wake up a second circuitry; and
a control circuitry coupled to the first wake circuitry and the second wake circuitry, wherein the control circuitry is to turn off the first wake circuitry and the second wake circuitry when a processor core of the plurality of processor cores is in an active operational mode.
, Description:BACKGROUND
[0001] In existing designs, system wake logic is always ON and consumes power all the time, irrespective of the system being in an active state (e.g., S0 state as defined by the Advanced Configuration and Power Interface (ACPI) specification) or an idle standby state (e.g., S0ix state as defined by the ACPI specification).
[0002] Further, when a system (e.g., notebook, tablet, handheld device) is in a fully operational state (e.g., S0-Fully ON state), Operating System Power Manager (OSPM) opportunistically uses Runtime D3 (RTD3) to transition devices within the system to a lower power mode. RTD3 refers to the placement of a device into D3hot or D3cold state while the rest of the platform or system remains in an S0 state. OSPM opportunistically uses RTD3 by monitoring device idle state. For example, the OSPM waits for the device idleness and if the Latency Tolerance Report (LTR) requirement is met, then the OSPM (or OS) will drive that device into a low power mode, so that it consumes less power and improves the overall battery life. But RTD3 is not applied to all the devices in a system and is completely dependent on an implementation choice of an OEM (Original Equipment Manufacturer), and it is cost additive to the product.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0004] Fig. 1 illustrates a system-on-chip (SoC) architecture for controlling wake logic of individual domains or intellectual property (IP) blocks in S0 state and/or S0ix state, in accordance with some embodiments.
[0005] Fig. 2 illustrates a system or platform architecture for controlling wake logic of various components of the system or platform, in accordance with some embodiments.
[0006] Fig. 3 illustrates a state transition diagram for wake logic control in S0, S0ix states at an SoC level and a platform level, respectively, in accordance with some embodiments.
[0007] Fig. 4 illustrates a pseudo-code that is used to communicate to a software (e.g., operating system) all operational modes supported by the system.
[0008] Fig. 5 illustrates a pseudo-code that lists devices which become unusable in certain system operational modes, in accordance with some embodiments.
[0009] Fig. 6 illustrates a flowchart showing software to hardware interaction for power management using system operational mode, in accordance with some embodiments.
[0010] Fig. 7 illustrates a state transition diagram for power management using system operational mode, in accordance with some embodiments.
[0011] Fig. 8 illustrates a smart device or a computer system or an SoC (System-on-Chip) with wakeup logic and associated control to manage power, and/or software or firmware for power management using system operational mode, in accordance with some embodiments.

DETAILED DESCRIPTION
[0012] As discussed herein, in existing designs, system wake logic is always powered ON and consumes power all the time, irrespective of the system being in an active (e.g., S0) or low power state (e.g., S0ix state). In the active state case (e.g., S0 case), existing designs do not turn off wake logic or circuits associated with various intellectual property (IP) blocks inside a system-on-chip (SoC). The same is true at a platform or board level where there is no provision for turning off wake circuitry in the active case (e.g., S0 case) where the SoC is in a fully turned on state. In the connected standby or low power case (e.g., S0ix case), once the system enters the low power state, there is no means for the system power management to selectively turn off wake logic associated with platform components.