FORM 2
THE PATENTS ACT, 1970
(39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
DRIVE CIRCUIT FOR POWER SEMICONDUCTOR ELEMENT,
SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE;
MITSUBISHI ELECTRIC CORPORATION, A CORPORATION
ORGANISED AND EXISTING UNDER THE LAWS OF JAPAN, WHOSE
ADDRESS IS 7-3, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO 1008310,
JAPAN
THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED
- 2 -
DESCRIPTION
TECHNICAL FIELD
[0001] The present disclosure relates to a drive circuit for a power semiconductor
element, a semiconductor device, and a power conversion device.
5 BACKGROUND ART
[0002] When a short-circuited state occurs in a power semiconductor element such as
an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide
Semiconductor Field Effect Transistor), a high current may flow and the semiconductor
element may be thermally destructed. Therefore, the function of sensing the short10 circuited state of the power semiconductor element and protecting the power
semiconductor element is required.
[0003] In addition, in recent years, short circuit tolerance has decreased with a
reduction in size of power semiconductor elements, and thus, high-speed protection
from a short circuit has been increasingly required. A short circuit protection circuit
15 that achieves high-speed protection from a short circuit may malfunction due to its high
responsiveness, and thus, measures are taken against noise by using a filter or the like.
[0004] Japanese Patent Laying-Open No. 2017-143700 (PTL 1) describes a short
circuit detection device configured to detect a short-circuited state of a power
semiconductor element by using the fact that a Miller period of a gate voltage
20 disappears at the time of a short circuit. The short circuit detection device detects that
the power semiconductor element is short-circuited, when the gate voltage reaches a
reference voltage earlier than a predetermined time. The short circuit detection device
further determines that the power semiconductor element is not short-circuited, when a
decrease in gate voltage is detected within a predetermined time period, even if the
25 short circuit detection device detects the short-circuited state. That is, in PTL 1, when
the gate voltage temporarily exceeds the reference voltage due to noise and the like, the
short circuit detection device determines that the power semiconductor element is not
short-circuited, which leads to suppression of false detection of a short circuit.
[0005] Japanese Patent Laying-Open No. 2014-117112 (PTL 2) describes a short
- 3 -
circuit sensing circuit configured to sense a short circuit current flowing through a
power semiconductor element, based on a voltage across terminals of a resistor
connected to a sense cell of the power semiconductor element. In PTL 2, a noise
filtering element is connected to an output of the short circuit sensing circuit, to thereby
5 remove a harmonic wave caused by switching noise from the output of the short circuit
sensing circuit, and as a result, suppress false sensing of a short circuit. PTL 2 further
describes a configuration in which a noise filtering element is connected to an output of
a short circuit sensing circuit configured to sense a short circuit using a positive
electrode-side voltage (e.g., a collector voltage in the case of an IGBT) of a power
10 semiconductor element.
CITATION LIST
PATENT LITERATURE
[0006] PTL 1: Japanese Patent Laying-Open No. 2017-143700
PTL2: Japanese Patent Laying-Open No. 2014-117112
15 SUMMARY OF INVENTION
TECHNICAL PROBLEM
[0007] However, the short circuit detection device described in PTL 1 determines that
the power semiconductor element is not short-circuited, when a decrease in gate
voltage is detected within the predetermined time period. Therefore, when a physical
20 quantity (such as, for example, a gate current and a gate electric charge) other than the
gate voltage is used for short circuit determination, or when short circuit determination
is made based on a correlation among a plurality of physical quantities obtained from
the gate electrode, the short circuit detection device described in PTL 1 is not
applicable.
25 [0008] In the short circuit sensing circuit described in PTL 2, the short circuit current is
sensed using the resistor connected to the sense cell of the power semiconductor
element, and thus, the sense cell is required. Therefore, when the power
semiconductor element without a sense cell is used, the short circuit sensing circuit
described in PTL 2 is not applicable. In addition, when the power semiconductor
- 4 -
element with a sense cell and the resistor is used, it is concerned that the power
semiconductor element and a drive circuit increase in size. Even when a short circuit
is sensed based on the positive electrode-side voltage of the power semiconductor
element, a high voltage diode is required, and thus, it is concerned that the power
5 semiconductor element and the drive circuit increase in size.
[0009] The present disclosure has been made to solve the above-described problems,
and an object of the present disclosure is to suppress a malfunction caused by wrong
determination in a drive circuit that is applicable to a wide variety of power
semiconductor elements and capable of simply determining a short-circuited state of a
10 power semiconductor element.
SOLUTION TO PROBLEM
[0010] A drive circuit for a power semiconductor element according to the present
disclosure is a drive circuit that drives a power semiconductor element including a gate
electrode, a first main electrode and a second main electrode. The drive circuit
15 includes: a controller to control an opened/closed state of the power semiconductor
element based on an externally received command; a short circuit determination
circuitry to determine whether the power semiconductor element is in a short-circuited
state in a turn-on operation of the power semiconductor element, and output a
determination signal indicating a determination result; and a filter to receive the
20 determination signal from the short circuit determination circuitry, generate a delay
signal of the determination signal, and output the delay signal to the controller. A
delay time of the filter is set to be longer than a length of a Miller period in the turn-on
operation of the power semiconductor element.
ADVANTAGEOUS EFFECTS OF INVENTION
25 [0011] According to the present disclosure, it is possible to suppress a malfunction
caused by wrong determination in a drive circuit that is applicable to a wide variety of
power semiconductor elements and capable of simply determining a short-circuited
state of a power semiconductor element.
BRIEF DESCRIPTION OF DRAWINGS
- 5 -
[0012] Fig. 1 shows a first configuration example of a power semiconductor element
and a drive circuit therefor according to a first embodiment.
Fig. 2 shows a second configuration example of the power semiconductor
element and the drive circuit therefor according to the first embodiment.
5 Fig. 3 shows waveform diagrams schematically showing time variation in gate
voltage, gate current, determination signal, and delay signal in a turn-on operation of
the power semiconductor element.
Fig. 4 shows waveform diagrams schematically showing time variation in gate
voltage, gate current, determination signal, and delay signal when noise is applied to a
10 gate electrode during the turn-on operation of the power semiconductor element.
Fig. 5 shows waveform diagrams schematically showing time variation in gate
voltage, gate current, determination signal, and delay signal when a turn-off operation
is started during the turn-on operation of the power semiconductor element.
Fig. 6 shows a first configuration example of a filter.
15 Fig. 7A shows a part of a second configuration example of the filter.
Fig. 7B shows the second configuration example of the filter.
Fig. 8 shows a first configuration example of a short circuit determination unit.
Fig. 9 shows waveform diagrams schematically showing time variation in
differential signal of the gate voltage and gate electric charge.
20 Fig. 10 shows waveform diagrams schematically showing time variation in
differential signal of the gate voltage and gate electric charge when the turn-off
operation is started during the turn-on operation of the power semiconductor element.
Fig. 11 shows a second configuration example of the short circuit determination
unit.
25 Fig. 12 is a block diagram showing a configuration of a power conversion
system in which a power conversion device according to a six embodiment is applied.
DESCRIPTION OF EMBODIMENTS
[0013] Embodiments of the present disclosure will be described in detail with reference
to the drawings, in which the same or corresponding portions are denoted by the same
- 6 -
reference characters and description thereof will not be repeated. The embodiments
and modifications described below may be combined as appropriate.
[0014] First Embodiment
Fig. 1 shows a first configuration example of a semiconductor device including
5 a drive circuit according to a first embodiment. As shown in Fig. 1, the
semiconductor device according to the first configuration example includes a power
semiconductor element 1 (hereinafter, simply referred to as "semiconductor element 1")
and a drive circuit 100.
[0015] Semiconductor element 1 includes a first main electrode, a second main
10 electrode and a gate electrode. A device made of any one of Si (silicon), SiC (silicon
carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide) can be applied as
semiconductor element 1.
[0016] Although the example of Fig. 1 illustrates an IGBT as semiconductor element 1,
semiconductor element 1 is not necessarily limited to an IGBT and may be a fully
15 controllable power semiconductor element such as a MOSFET. Semiconductor
element 1 is included in a power converter such as an inverter that converts DC power
into AC power and a converter that converts AC power into DC power.
[0017] Semiconductor element 1 includes a collector electrode 1c, an emitter electrode
1e and a gate electrode 1g. A voltage higher than a voltage applied to emitter
20 electrode 1e is applied to collector electrode 1c. Gate electrode 1g corresponds to
"gate electrode", collector electrode 1c corresponds to "first main electrode", and
emitter electrode 1e corresponds to "second main electrode".
[0018] Drive circuit 100 is connected to gate electrode 1g of semiconductor element 1
and drives semiconductor element 1. Drive circuit 100 includes a controller 2, a short
25 circuit determination unit 3 and a filter 4.
[0019] Controller 2 receives an external command and controls an opened/closed state
of semiconductor element 1. Specifically, when an on-command is input externally,
controller 2 applies, to gate electrode 1g of semiconductor element 1, a gate voltage Vg
for bringing semiconductor element 1 into the closed state (on state) (hereinafter,
- 7 -
referred to as "turn-on") (hereinafter, referred to as "on gate voltage Vg_on"). As a
result, semiconductor element 1 is turned on and is in the closed state.
[0020] When an off-command is input externally, controller 2 applies, to gate electrode
1g of semiconductor element 1, gate voltage Vg for bringing semiconductor element 1
5 into the opened state (off state) (hereinafter, referred to as "turn-off") (hereinafter,
referred to as "off gate voltage Vg_off"). As a result, semiconductor element 1 is
turned off and is in the opened state.
[0021] Short circuit determination unit 3 is connected to gate electrode 1g of
semiconductor element 1 and determines whether semiconductor element 1 is in a
10 short-circuited state, based on a physical quantity detected at gate electrode 1g.
"Short-circuited state" herein refers to a state in which semiconductor element 1 is
connected to a voltage source at a low resistance and an excessive short circuit current
flows due to the factors such as failure or malfunction of a peripheral component of
semiconductor element 1.
15 [0022] The physical quantity obtained from gate electrode 1g includes gate voltage Vg
between gate electrode 1g and emitter electrode 1e, and a gate current Ig that flows into
gate electrode 1g. Short circuit determination unit 3 determines the short-circuited
state of semiconductor element 1 by making the use of the fact that there is a difference
in waveform of the physical quantity in the turn-on operation between the normal state
20 and the short-circuited state.
[0023] Specifically, in the normal state, "Miller period", which is a time period during
which gate voltage Vg is constant, appears in the waveform of gate voltage Vg in the
turn-on operation, before gate voltage Vg reaches on gate voltage Vg_on. In contrast,
in the short-circuited state, the Miller period does not appear in the waveform of gate
25 voltage Vg and gate voltage Vg rises to on gate voltage Vg_on all at once.
[0024] Short circuit determination unit 3 is configured to determine the short-circuited
state of semiconductor element 1 by making the use of the fact that in the shortcircuited state, the Miller period disappears in gate voltage Vg in the turn-on operation.
Short circuit determination unit 3 outputs a determination signal Sj indicating a
- 8 -
determination result. Specifically, short circuit determination unit 3 outputs
determination signal Sj having a "L (logic low)" level when semiconductor element 1 is
normal, and outputs determination signal Sj having a "H (logic high)" level when
semiconductor element 1 is in the short-circuited state. That is, when it is determined
5 that semiconductor element 1 is in the short-circuited state, short circuit determination
unit 3 outputs determination signal Sj having the H level. A specific configuration of
short circuit determination unit 3 will be described below.
[0025] Filter 4 generates a delay signal Sd obtained by delaying determination signal Sj
output from short circuit determination unit 3, and outputs generated delay signal Sd to
10 controller 2. Filter 4 has a delay time longer than a Miller period T_miller of
semiconductor element 1. A specific configuration of filter 4 will be described below.
[0026] When noise is applied to gate electrode 1g during the Miller period in the turnon operation of semiconductor element 1, or when a turn-off operation is started during
the Miller period, the physical quantity of gate electrode 1g may change abruptly.
15 The abrupt change in physical quantity during the Miller period may cause short circuit
determination unit 3 to wrongly determine that semiconductor element 1 is in the shortcircuited state. Thus, in drive circuit 100 according to the first embodiment, the delay
time of filter 4 is set to be longer than the Miller period, which makes it possible for
filter 4 to attenuate or cut off wrong determination signal Sj output from short circuit
20 determination unit 3.
[0027] Fig. 2 shows a second configuration example of the semiconductor device
including the drive circuit according to the first embodiment. The semiconductor
device according to the second configuration example is different in configuration of
drive circuit 100 from the semiconductor device according to the first configuration
25 example. Drive circuit 100 according to the second configuration example is different
from drive circuit 100 shown in Fig. 1 in that a buffer circuit 5, an on gate resistor 6a
and an off gate resistor 6b are added. Since the remaining configuration of drive
circuit 100 is the same as that of drive circuit 100 according to the first configuration
example, detailed description will not be repeated here.
- 9 -
[0028] Buffer circuit 5 applies on gate voltage Vg_on input from controller 2 to gate
electrode 1g of semiconductor element 1 through on gate resistor 6a. Buffer circuit 5
applies off gate voltage Vg_off input from controller 2 to gate electrode 1g of
semiconductor element 1 through off gate resistor 6b.
5 [0029] Next, an operation of filter 4 in drive circuit 100 according to the first
embodiment will be described with reference to Figs. 3 to 5.
[0030] Fig. 3 shows waveform diagrams schematically showing time variation in gate
voltage Vg and gate current Ig in the turn-on operation of semiconductor element 1.
In Fig. 3, the waveforms of gate voltage Vg and gate current Ig in the normal state are
10 indicated by solid lines, and the waveforms of gate voltage Vg and gate current Ig in
the short-circuited state are indicated by broken lines.
[0031] First, gate voltage Vg and gate current Ig in the turn-on operation in the normal
state will be described.
[0032] As shown in Fig. 3, when a command input to controller 2 changes from the
15 off-command to the on-command at time t0, controller 2 applies on gate voltage Vg_on
to gate electrode 1g of semiconductor element 1. As a result, gate voltage Vg of
semiconductor element 1 starts to shift from off gate voltage Vg_off to on gate voltage
Vg_on.
[0033] Specifically, after time t0, gate current Ig flows from controller 2 into gate
20 electrode 1g, and a parasitic capacitance component between gate electrode 1g and
emitter electrode 1e (hereinafter, referred to as "gate-to-emitter capacitance Cge") is
thereby charged. Therefore, gate voltage Vg rises gradually. A time period from
time t0 to time t1 corresponds to a charging time period of gate-to-emitter capacitance
Cge.
25 [0034] Next, when gate voltage Vg exceeds a threshold voltage at time t1,
semiconductor element 1 starts to be turned on. When semiconductor element 1 turns
on, a collector current starts to flow between collector electrode 1c and emitter
electrode 1e, and thus, a potential of collector electrode 1c starts to decrease. As a
result, an electric charge stored in a parasitic capacitance component between gate
- 10 -
electrode 1g and collector electrode 1c (hereinafter, referred to as "gate-to-collector
capacitance Cgc") is discharged. During a time period from time t1 to time t4, most
of gate current Ig flows through gate-to-collector capacitance Cgc and does not flow
through gate-to-emitter capacitance Cge, and thus, gate voltage Vg does not rise and is
5 maintained constant.
[0035] The time period during which gate voltage Vg is constant, like the time period
from time t1 to time t4, is referred to as "Miller period". In addition, this constant
voltage value (corresponding to Vm in the figure) is referred to as "Miller voltage".
The Miller period is a time period for discharging the electric charge stored in gate-to10 collector capacitance Cgc. Gate-to-collector capacitance Cgc corresponds to a
feedback capacitance in semiconductor element 1. The length of the Miller period
T_miller and the magnitude of Miller voltage Vm vary depending on operating
conditions such as a voltage Vce between collector electrode 1c and emitter electrode
1e of semiconductor element 1, and the collector current.
15 [0036] When the discharging of gate-to-collector capacitance Cgc ends, gate voltage
Vg rises again while gate-to-emitter capacitance Cge is charged, and then, gate voltage
Vg reaches on gate voltage Vg_on. At this time, gate-to-collector capacitance Cgc
(feedback capacitance) is in a state of being charged in a direction opposite to that
before the turn-on operation. When the shift of semiconductor element 1 to the on
20 state is completed, gate current Ig becomes zero.
[0037] Next, gate voltage Vg and gate current Ig in the turn-on operation in the shortcircuited state will be described.
[0038] At time t0, in response to the externally input on-command, controller 2 applies
on gate voltage Vg_on to gate electrode 1g of semiconductor element 1. As a result,
25 gate voltage Vg of semiconductor element 1 starts to shift from off gate voltage Vg_off
to on gate voltage Vg_on. At this time, gate current Ig flows from controller 2 into
gate electrode 1g of semiconductor element 1.
[0039] When semiconductor element 1 is in the short-circuited state, a peripheral
circuit connected to collector electrode 1c of semiconductor element 1 is short-circuited,
- 11 -
and thus, a high voltage is applied between collector electrode 1c and emitter electrode
1e. Thus, the potential of collector electrode 1c of semiconductor element 1 becomes
higher than a potential of gate electrode 1g and gate-to-collector capacitance Cgc
(feedback capacitance) is not charged. Therefore, the Miller period does not appear in
5 gate voltage Vg. As a result, gate voltage Vg rises to on gate voltage Vg_on all at
once. Since gate current Ig for charging the feedback capacitance does not flow,
either, gate current Ig rises immediately after time t0, and then, converges to zero
earlier than the normal state.
[0040] The length of the Miller period T_miller can be given by T_millerQgc/Ig,
10 assuming that Qgc represents an electric charge quantity stored in gate-to-collector
capacitance Cgc and gate current Ig during the Miller period is constant.
[0041] When controller 2 uses on gate resistor 6a to control on gate voltage Vg_on
applied to gate electrode 1g as in the second configuration example (see Fig. 2), gate
current Ig can be calculated using Ig(Vg_onVm)/Rg_on, where Rg_on represents a
15 resistance value of on gate resistor 6a. According to this, T_miller can be expressed
like the following equation (1):
[0042]
⋯ (1).
[0043] Gate-to-collector capacitance Cgc (feedback capacitance) has a dependence on
the voltage between gate electrode 1g and collector electrode 1c. Therefore, when this
20 is represented as Cgc(V), electric charge quantity Qgc can be given by the following
equation (2):
[0044]
⋯ (2).
[0045] Finally, determination signal Sj and delay signal Sd will be described.
Fig. 3 further shows waveforms of determination signal Sj and delay signal Sd
25 obtained by delaying determination signal Sj. The solid lines indicate the waveforms
- 12 -
of determination signal Sj and delay signal Sd in the normal state, and the broken lines
indicate the waveforms of determination signal Sj and delay signal Sd in the shortcircuited state. Depending on an internal configuration of filter 4, delay signal Sd
may have the waveform shown in a first or second output example.
5 [0046] As shown in Fig. 3, when short circuit determination unit 3 detects
disappearance of the Miller period in gate voltage Vg at time t2 during the turn-on
operation, short circuit determination unit 3 outputs determination signal Sj having the
H level. In the example of Fig. 3, short circuit determination unit 3 is configured to
output determination signal Sj having the H level during a predetermined time period
10 from time t2 at which disappearance of the Miller period is detected to time t5.
However, short circuit determination unit 3 may be configured to output determination
signal Sj fixed to the H level, after time t2 at which disappearance of the Miller period
is detected.
[0047] In the first output example of filter 4, delay signal Sd rises slowly after time t2
15 at which determination signal Sj shifts from the L level to the H level. Furthermore,
delay signal Sd falls slowly after time t5 at which determination signal Sj shifts to the L
level. The rising time and the falling time of delay signal Sd are determined by the
delay time of filter 4. A time period during which delay signal Sd has the H level is
shorter than a time period during which determination signal Sj has the H level.
20 [0048] The second output example of filter 4 is obtained by shaping delay signal Sd
according to the first output example. Specifically, in filter 4, delay signal Sd
according to the first output example is input to a comparator, where delay signal Sd is
compared with a predetermined reference value REF. The comparator is configured
to output delay signal Sd having the H level when delay signal Sd according to the first
25 output example is equal to or higher than reference value REF, and output delay signal
Sd having the L level when delay signal Sd is lower than reference value REF.
[0049] As a result, in the second output example, delay signal Sd is a pulsed signal
showing the H level during a certain time period, similarly to determination signal Sj.
However, the timing at which delay signal Sd rises to the H level and the timing at
- 13 -
which delay signal Sd falls to the L level are later than the timing at which
determination signal Sj rises to the H level and the timing at which determination signal
Sj falls to the L level, respectively.
[0050] Filter 4 outputs generated delay signal Sd to controller 2. Based on delay
5 signal Sd having the H level, controller 2 detects that semiconductor element 1 is in the
short-circuited state. When it is detected that semiconductor element 1 is in the shortcircuited state, controller 2 generates off gate voltage Vg_off regardless of an
externally received command and applies off gate voltage Vg_off to gate electrode 1g
of semiconductor element 1. As a result, semiconductor element 1 is controlled to the
10 off state at high speed, and thus, semiconductor element 1 can be protected at high
speed.
[0051] According to short circuit determination unit 3 of the first embodiment, a sense
cell of the semiconductor element is not required, and thus, short circuit determination
unit 3 is also applicable to a semiconductor element that does not include a sense cell
15 and a resistor, and can simply determine the short-circuited state of the semiconductor
element. Furthermore, when semiconductor element 1 is short-circuited, the Miller
period is not present during the turn-on operation, and thus, short circuit determination
unit 3 can quickly determine the short-circuited state of semiconductor element 1 after
the start of the turn-on operation. As described above, short circuit determination unit
20 3 is applicable to a wide variety of semiconductor elements and capable of simply
detecting the short-circuited state of semiconductor element 1 at high speed.
[0052] During the turn-on operation, noise may be applied to gate electrode 1g of
semiconductor element 1. Or, in response to controller 2 that receives the external
off-command during the turn-on operation, the turn-off operation of semiconductor
25 element 1 may be started. In either case, a physical quantity different from the
physical quantity obtained in the normal state of semiconductor element 1 is obtained at
gate electrode 1g. In such a case, short circuit determination unit 3 may determine
that the Miller period in gate voltage Vg disappears, and wrongly output determination
signal Sj having the H level.
- 14 -
[0053] Fig. 4 shows waveform diagrams schematically showing time variation in gate
voltage Vg, gate current Ig, determination signal Sj, and delay signal Sd when noise is
applied to gate electrode 1g during the turn-on operation of semiconductor element 1.
In Fig. 4, a first output example of delay signal Sd corresponds to the same output
5 signal of filter 4 as the first output example shown in Fig. 3. A second output example
of delay signal Sd corresponds to the same output signal of filter 4 as the second output
example shown in Fig. 3.
[0054] In the example of Fig. 4, it is assumed that the turn-on operation of
semiconductor element 1 is started at time t0, and then, noise is applied to gate
10 electrode 1g during the Miller period from time t1 to time t4.
[0055] In this case, oscillations occur in the waveform of each of gate voltage Vg and
gate current Ig during the Miller period. These oscillations are input to short circuit
determination unit 3 as noise, which may cause short circuit determination unit 3 to
malfunction.
15 [0056] In the example of Fig. 4, short circuit determination unit 3 detects the
oscillations of gate voltage Vg and/or gate current Ig, determines that semiconductor
element 1 is in the short-circuited state, and outputs determination signal Sj having the
H level. Normally, determination signal Sj output from short circuit determination
unit 3 in such a case is a short-pulse signal due to instantaneous false recognition that
20 semiconductor element 1 is in the short-circuited state. A pulse width of
determination signal Sj in this case is shorter than the length of the Miller period
T_miller.
[0057] In the first output example of filter 4, filter 4 delays short-pulse determination
signal Sj. As described above, filter 4 has a delay time longer than the Miller period.
25 Therefore, the delay time of filter 4 is longer than the pulse width of determination
signal Sj.
[0058] Delay signal Sd rises slowly after time t2 at which determination signal Sj shifts
from the L level to the H level, and falls slowly after time t3 at which determination
signal Sj shifts to the L level. However, since the pulse width of determination signal
- 15 -
Sj is shorter than the delay time, delay signal Sd starts to attenuate before delay signal
Sd reaches the H level. Therefore, no pulse is seen in delay signal Sd.
[0059] In the second output example of filter 4, delay signal Sd is generated based on
comparison between delay signal Sd in the first output example and reference value
5 REF. Since delay signal Sd in the first output example is lower than reference value
REF, delay signal Sd in the second output example is also kept at the L level after time
t2.
[0060] As described above, determination signal Sj wrongly output due to the noise
applied during the Miller period is delayed or cut off by filter 4. Therefore, input of
10 wrong determination signal Sj to controller 2 is blocked. Thus, it is possible to
prevent such a malfunction that controller 2 controls semiconductor element 1 to the off
state based on wrong determination signal Sj.
[0061] Fig. 5 shows waveform diagrams schematically showing time variation in gate
voltage Vg, gate current Ig, determination signal Sj, and delay signal Sd when the turn15 off operation is started during the turn-on operation of semiconductor element 1. In
Fig. 5, a first output example of delay signal Sd corresponds to the same output signal
of filter 4 as the first output example shown in Fig. 3. A second output example of
delay signal Sd corresponds to the same output signal of filter 4 as the second output
example shown in Fig. 3.
20 [0062] In the example of Fig. 5, it is assumed that the turn-on operation of
semiconductor element 1 is started at time t0, and then, the turn-off operation is started
at time t2 during the Miller period from time t1 to time t4.
[0063] In this case, gate voltage Vg decreases abruptly from Miller voltage Vm after
time t2 and reaches off gate voltage Vg_off. Gate current Ig decreases abruptly after
25 time t2 and converges to zero.
[0064] In the second configuration example (see Fig. 2) in which on gate resistor 6a
and off gate resistor 6b are separated from each other, gate current Ig converges to zero.
However, in the case where on gate resistor 6a and off gate resistor 6b are commonly
used, gate current Ig flows in a direction opposite to that in the turn-on operation when
- 16 -
the turn-off operation is started at time t2.
[0065] As described above, when the turn-off operation is started during the Miller
period, gate voltage Vg and gate current Ig change abruptly, and thus, short circuit
determination unit 3 determines that semiconductor element 1 is in the short-circuited
5 state, and outputs determination signal Sj having the H level. In the example of Fig. 4,
determination signal Sj is output at the moment of the start of the turn-off operation
(time t2).
[0066] Determination signal Sj is caused by the abrupt change in physical quantity that
occurs during the Miller period in which the short circuit determination is made.
10 Therefore, even if the turn-off operation is started after the end of the short circuit
determination, i.e., after the end of the Miller period, determination signal Sj is not
output.
[0067] In addition, determination signal Sj output from short circuit determination unit
3 is a short-pulse signal due to instantaneous false recognition that semiconductor
15 element 1 is in the short-circuited state. A pulse width of determination signal Sj in
this case is shorter than the length of the Miller period T_miller.
[0068] In the first output example of filter 4, filter 4 delays short-pulse determination
signal Sj. Delay signal Sd rises slowly after time t2 at which determination signal Sj
shifts from the L level to the H level, and falls slowly after time t3 at which
20 determination signal Sj shifts to the L level. However, since the pulse width of
determination signal Sj is shorter than the delay time, delay signal Sd starts to attenuate
before delay signal Sd reaches the H level. Therefore, no pulse is seen in delay signal
Sd.
[0069] In the second output example of filter 4, delay signal Sd is generated based on
25 comparison between delay signal Sd in the first output example and reference value
REF. Since delay signal Sd in the first output example is lower than reference value
REF, delay signal Sd in the second output example is also kept at the L level after time
t2.
[0070] As described above, determination signal Sj wrongly output due to the turn-off
- 17 -
operation during the Miller period is delayed or cut off by filter 4. Therefore, input of
wrong determination signal Sj to controller 2 is blocked. Thus, it is possible to
prevent such a malfunction that controller 2 controls semiconductor element 1 to the off
state based on wrong determination signal Sj.
5 [0071] As described above, when noise is applied to gate electrode 1g during the Miller
period in the turn-on operation (see Fig. 3), or when the turn-off operation is started
during the Miller period (see Fig. 4), short circuit determination unit 3 may wrongly
output determination signal Sj having the H level due to the abrupt change in physical
quantity at gate electrode 1g. Normally, this wrong determination signal Sj is a short10 pulse signal, and a length of a time period during which determination signal Sj has the
H level is shorter than the length of the Miller period T_miller.
[0072] In drive circuit 100 according to the first embodiment, filter 4 is provided
between short circuit determination unit 3 and controller 2, and the length of the delay
time of filter 4 is set to be longer than the length of the Miller period T_miller.
15 Therefore, determination signal Sj wrongly output by short circuit determination unit 3
can be delayed or cut off by filter 4. That is, when  represents the delay time of filter
4, the relationship given by the following equation (3) is satisfied between delay time 
and the length of the Miller period T_miller given by the equation (1).
[0073]
⋯ (3)
20 [0074] According to drive circuit 100 of the first embodiment, it is possible to suppress
a malfunction caused by a wrong determination signal in a drive circuit configured to
be applicable to a wide variety of semiconductor elements and capable of simply
detecting a short-circuited state of semiconductor element 1 at high speed.
[0075] In the first embodiment, description has been given of the configuration
25 example in which short circuit determination unit 3 outputs determination signal Sj
having the L level when semiconductor element 1 is in the normal state, and outputs
determination signal Sj having the H level when semiconductor element 1 is in the
- 18 -
short-circuited state. However, short circuit determination unit 3 may be configured
to output determination signal Sj having the H level when semiconductor element 1 is
in the normal state, and output determination signal Sj having the L level when
semiconductor element 1 is in the short-circuited state.
5 [0076] Second Embodiment
In a second embodiment, description will be given of a first configuration
example of filter 4 applied to drive circuit 100 according to the first embodiment (see
Figs. 1 and 2).
[0077] Fig. 6 shows a first configuration example of filter 4. As shown in Fig. 6,
10 filter 4 according to the first configuration example is an RC circuit including a resistor
R1 and a capacitor C1. Resistor R1 and capacitor C1 are connected in series between
an input terminal 41 and a ground 11. A connection point of resistor R1 and capacitor
C1 is connected to an output terminal 42. Input terminal 41 receives determination
signal Sj from short circuit determination unit 3. Output terminal 42 outputs delay
15 signal Sd of determination signal Sj.
[0078] In the first configuration example, a delay signal A' output from output terminal
42 with respect to an input signal A received by input terminal 41 can be expressed like
the following equation (4):
[0079]
⋯ (4),
20 [0080] where R1 represents a resistance value of resistor R1, C1 represents a
capacitance value of capacitor C1, and t represents a time period from the time when
input signal A is received.
[0081] R1C1 in the equation (4) corresponds to a time constant of the RC circuit.
By using this time constant (R1C1) as delay time  of filter 4 and setting the values of
25 R1 and C1 to satisfy the relationship of the equation (3) above, the operation of filter 4
described in the first embodiment can be achieved. Filter 4 is not limited to the
configuration shown in Fig. 6, and may be formed of a plurality of resistors and a
- 19 -
plurality of capacitors.
[0082] According to the circuit configuration shown in Fig. 6, delay signal Sd shown in
the first output example in Figs. 4 and 5 can be generated. Furthermore, in the circuit
configuration shown in Fig. 6, filter 4 can generate delay signal Sd shown in the second
5 output example in Figs. 4 and 5 by connecting a comparator between the connection
point of resistor 1 and capacitor C1 and output terminal 42.
[0083] Third Embodiment
In a third embodiment, description will be given of a second configuration
example of filter 4 applied to the drive circuit according to the first embodiment (see
10 Figs. 1 and 2).
[0084] Figs. 7A and 7B are circuit diagrams showing the second configuration example
of filter 4. Filter 4 according to the second configuration example includes at least
one RC circuit and an optocoupler 7. Fig. 7A shows a configuration example of a
circuit for driving optocoupler 7. Fig. 7B shows a configuration example of a circuit
15 in which at least one RC circuit is added to the circuit shown in Fig. 7A.
[0085] In filter 4 according to the second configuration example, input terminal 41 that
receives determination signal Sj is electrically insulated from output terminal 42 that
outputs delay signal Sd. Therefore, filter 4 can transmit delay signal Sd of
determination signal Sj to controller 2 while electrically insulating short circuit
20 determination unit 3 from controller 2.
[0086] According to this, when short circuit determination unit 3 is connected to gate
electrode 1g of semiconductor element 1 on the high side (on the high-voltage side) in a
power converter, for example, it is possible to prevent controller 2 from receiving a
high voltage and being destroyed, because short circuit determination unit 3 is
25 electrically insulated from controller 2. Normally, when semiconductor element 1 on
the high side is driven, controller 2 ensures electric insulation between the externally
received input and the gate voltage by including an insulation circuit. Thus, instead of
the present configuration example in which optocoupler 7 is provided in filter 4,
controller 2 may be further provided with an insulation circuit for the determination
- 20 -
signal and this insulation circuit may receive delay signal Sd from filter 4.
[0087] As shown in Fig. 7A, on the primary side of optocoupler 7, resistors R2 and R3
and a MOSFET 8 are connected in series in this order between a power supply node 15
that supplies a power supply potential VDD and a ground 12 having a ground potential
5 GND1. A light emitting element (light emitting diode) of optocoupler 7 is connected
between a first terminal and a second terminal of resistor R3. A resistor R4 and a
resistor R5 are connected in series between input terminal 41 and ground 12. A
connection point of resistor R4 and resistor R5 is connected to a gate of MOSFET 8.
[0088] On the secondary side of optocoupler 7, a light receiving element is connected
10 between a power supply node 13 that supplies a power supply potential VCC and a
ground 14 having a ground potential GND2. An output node 71 of the light receiving
element is connected to output terminal 42.
[0089] When determination signal Sj having the H level is received at input terminal 41,
MOSFET 8 is in the on state and a current flows through resistor R2 and resistor R3.
15 When a voltage across the terminals of resistor R3 becomes equal to or higher than a
reference voltage, optocoupler 7 operates and outputs power supply potential VCC of
power supply node 13 to output node 71. In contrast, when determination signal Sj
having the L level is received at input terminal 41, MOSFET 8 is in the off state, and
thus, optocoupler 7 does not operate. In this case, optocoupler 7 outputs ground
20 potential GND of ground 14 to output node 71. That is, optocoupler 7 outputs a signal
having power supply potential VCC when determination signal Sj having the H level is
received, and outputs a signal having ground potential GND2 when determination
signal Sj having the L level is received.
[0090] In the circuit diagram shown in Fig. 7B, capacitors C2 and C3 are connected to
25 the primary side of optocoupler 7, and a resistor R6 and a capacitor C4 are connected to
the secondary side of optocoupler 7. Capacitor C2 is connected in parallel to resistor
R3. Capacitor C3 is connected in parallel to resistor R5. Resistor R6 and capacitor
C4 are connected in series between output node 71 and ground 14. A connection
point of resistor R6 and capacitor C4 is connected to output terminal 42.
- 21 -
[0091] Capacitor C2 is for delaying an input signal received by the primary side of
optocoupler 7. A time constant in a delay of the input signal is C2/(1/R21/R3),
where C2 represents a capacitance value of capacitor C2, R2 represents a resistance
value of resistor R2, and R3 represents a resistance value of resistor R3.
5 [0092] Capacitor C3 is for delaying an input signal received by MOSFET 8. A time
constant in a delay of the input signal is C3/(1/R41/R5), where C3 represents a
capacitance value of capacitor C3, R4 represents a resistance value of resistor R4, and
R5 represents a resistance value of resistor R5.
[0093] Resistor R6 and capacitor C4 are for delaying an output signal output from
10 output node 71 of optocoupler 7 to output terminal 42. A time constant in a delay of
the output signal is R6C4, where C4 represents a capacitance value of capacitor C4
and R6 represents a resistance value of resistor R6.
[0094] In the circuit configuration in Fig. 7B, the delay time of filter 4 can be set using
the above-described three types of time constants. A configuration for setting the
15 delay time of filter 4 is not limited to the configuration shown in Fig. 7B, and the delay
time of filter 4 may be set using at least one of the above-described three types of time
constants. That is, the delay time of filter 4 can be set by adding at least one of
capacitors C2 and C3 and/or a series circuit of resistor R6 and capacitor C4 to the
circuit shown in Fig. 7A.
20 [0095] According to the circuit configuration in Fig. 7B, delay signal Sd shown in the
first output example in Fig. 3 can be generated. Furthermore, in the circuit
configuration in Fig. 7B, delay signal Sd shown in the second output example in Fig. 3
can be generated by connecting a comparator between the connection point of resistor 6
and capacitor C4 and output terminal 42.
25 [0096] In a configuration in which resistor 6 and capacitor C4 are removed from the
circuit configuration in Fig. 7B, optocoupler 7 itself operates like a comparator, and
thus, delay signal Sd shown in the second output example in Fig. 3 can be generated.
However, a comparator may be further connected between output node 71 of
optocoupler 7 and output terminal 42.
- 22 -
[0097] Fourth Embodiment
In a fourth embodiment, description will be given of a first configuration
example of short circuit determination unit 3 applied to drive circuit 100 according to
the first embodiment.
5 [0098] Fig. 8 shows the first configuration example of short circuit determination unit 3
shown in Fig. 1.
As shown in Fig. 8, short circuit determination unit 3 according to the first
configuration example includes a gate electrode physical quantity operation circuit 31
(hereinafter, simply referred to as "operation circuit 31") and a short circuit
10 determination circuit 32.
[0099] Operation circuit 31 is connected to gate electrode 1g of semiconductor element
1 and obtains a physical quantity at gate electrode 1g. The physical quantity obtained
by operation circuit 31 includes, for example, gate voltage Vg, gate current Ig, a
differential signal of gate voltage Vg, and gate electric charge quantity Qg. The
15 differential signal of gate voltage Vg can be obtained by time differentiation of gate
voltage Vg. Gate electric charge quantity Qg can be obtained by time integration of
gate current Ig. These physical quantities may be further subjected to delay
processing, differentiation processing or integration processing.
[0100] Short circuit determination circuit 32 determines whether semiconductor
20 element 1 is in the short-circuited state, based on the physical quantity obtained by
operation circuit 31, and outputs determination signal Sj indicating a determination
result to filter 4.
[0101] An example of the physical quantity detected by operation circuit 31 shown in
Fig. 8 will be described with reference to Fig. 9.
25 [0102] Fig. 9 shows waveform diagrams schematically showing time variation in
differential signal of gate voltage Vg and gate electric charge quantity Qg. In Fig. 9,
the waveforms in the normal state are indicated by solid lines, and the waveforms in the
short-circuited state are indicated by broken lines.
[0103] The Miller period is seen in gate voltage Vg in the normal state (see Fig. 3).
- 23 -
Therefore, as shown in Fig. 9, the differential signal in the normal state is maintained at
a constant value from time t0 at which the on-command is received to the start of the
Miller period, and then, temporarily becomes zero during the Miller period.
Thereafter, the differential signal rises again after the end of the Miller period, and then,
5 converges to zero.
[0104] In contrast, gate voltage Vg in the short-circuited state increases monotonically
and reaches on gate voltage Vg_on after time t0. Therefore, as shown in Fig. 9, the
differential signal is kept at a constant value immediately after time t0, and then,
decreases and converges to zero.
10 [0105] Gate current Ig in the normal state rises abruptly at time t0 at which the oncommand is received, and then, starts to fall. Gate current Ig is maintained at a
constant value during the Miller period, and then, falls again and converges to zero (see
Fig. 3). Therefore, as shown in Fig. 9, gate electric charge quantity Qg in the normal
state rises gradually and converges to a constant value after time t0.
15 [0106] In contrast, gate current Ig in the short-circuited state rises abruptly at time t0,
and then, starts to fall and converges to zero (see Fig. 3). Therefore, as shown in Fig.
9, gate electric charge quantity Qg in the short-circuited state rises and converges to a
constant value after time t0. A convergence value is lower than that in the normal
state.
20 [0107] As shown in Fig. 9, a difference in waveform also appears in the differential
signal of gate voltage Vg and gate electric charge quantity Qg, based on the presence or
absence of the Miller period. Therefore, short circuit determination circuit 32 can
determine that semiconductor element 1 is in the short-circuited state, by detecting a
difference in waveform of the detected physical quantity from the waveform in the
25 normal state.
[0108] When noise is applied to gate electrode 1g during the Miller period, oscillations
occur in gate voltage Vg and gate current Ig during the Miller period (see Fig. 4).
Since oscillations also occur in the differential signal of gate voltage Vg and gate
electric charge quantity Qg during the Miller period, these oscillations may cause short
- 24 -
circuit determination circuit 32 to wrongly determine that semiconductor element 1 is
in the short-circuited state. However, as described above, wrong determination signal
Sj output from short circuit determination circuit 32 is delayed or cut off by filter 4.
Therefore, it is possible to prevent a malfunction of controller 2 based on wrong
5 determination signal Sj.
[0109] Fig. 10 shows waveform diagrams schematically showing time variation in
differential signal of gate voltage Vg and gate electric charge quantity Qg when the
turn-off operation is started during the turn-on operation of semiconductor element 1.
When the turn-off operation is started at time t2 during the Miller period, gate voltage
10 Vg and gate current Ig during the Miller period decreases abruptly (see Fig. 5).
Therefore, as shown in Fig. 10, an abrupt decrease also appears in the waveform of the
differential signal of gate voltage Vg during the Miller period. In contrast, gate
electric charge quantity Qg stops rising at time t2, and then, is maintained at a constant
value.
15 [0110] Due to the abrupt change in differential signal and gate electric charge quantity
Qg, short circuit determination circuit 32 may wrongly determine that semiconductor
element 1 is in the short-circuited state. However, as described above, wrong
determination signal Sj output from short circuit determination circuit 32 is delayed or
cut off by filter 4. Therefore, it is possible to prevent a malfunction of controller 2
20 based on wrong determination signal Sj.
[0111] Fifth Embodiment
In a fifth embodiment, description will be given of a second configuration
example of short circuit determination unit 3 applied to drive circuit 100 according to
the first embodiment (see Figs. 1 and 2).
25 [0112] Fig. 11 shows the second configuration example of short circuit determination
unit 3.
As shown in Fig. 11, short circuit determination unit 3 according to the second
configuration example includes a first gate electrode physical quantity operation circuit
31a (hereinafter, simply referred to as "first operation circuit 31a"), a second gate
- 25 -
electrode physical quantity operation circuit 31b (hereinafter, simply referred to as
"second operation circuit 31b"), a first comparator 33a, a second comparator 33b, and
an AND circuit 34.
[0113] First operation circuit 31a is connected to gate electrode 1g of semiconductor
5 element 1 and obtains a first physical quantity at gate electrode 1g. The first physical
quantity obtained by first operation circuit 31a is, for example, any one of gate voltage
Vg, gate current Ig, the differential signal of gate voltage Vg, and gate electric charge
quantity Qg.
[0114] First comparator 33a compares the first physical quantity obtained by first
10 operation circuit 31a with a first reference value REF1, and outputs a signal Sc1
indicating a comparison result. For example, in the case where the first physical
quantity is the differential signal of gate voltage Vg, first comparator 33a outputs signal
Sc1 having the H level when the first physical quantity is higher than first reference
value REF1, and outputs signal Sc1 having the L level when the first physical quantity
15 is equal to or lower than first reference value REF1.
[0115] Second operation circuit 31b is connected to gate electrode 1g of semiconductor
element 1 and obtains a second physical quantity at gate electrode 1g. The second
physical quantity obtained by second operation circuit 31b is different from the first
physical quantity, and is, for example, any one of gate voltage Vg, gate current Ig, the
20 differential signal of gate voltage Vg, and gate electric charge quantity Qg.
[0116] Second comparator 33b compares the second physical quantity obtained by
second operation circuit 31b with a second reference value REF2, and outputs a signal
Sc2 indicating a comparison result. For example, in the case where the second
physical quantity is gate electric charge quantity Qg, second comparator 33b outputs
25 signal Sc2 having the H level when the second physical quantity is lower than second
reference value REF2, and outputs signal Sc2 having the L level when the second
physical quantity is equal to or higher than second reference value REF2.
[0117] AND circuit 34 performs an AND operation between output signal Sc1 of first
comparator 33a and output signal Sc2 of second comparator 33b, to thereby generate
- 26 -
determination signal Sj. When output signal Sc1 of first comparator 33a and output
signal Sc2 of second comparator 33b both have the H level, AND circuit 34 determines
that semiconductor element 1 is in the short-circuited state, and outputs determination
signal Sj having the H level. Otherwise, AND circuit 34 outputs determination signal
5 Sj having the L level. In the present configuration example, when the differential
signal of gate voltage Vg is higher than first reference value REF1 and gate electric
charge quantity Qg is lower than second reference value REF2, AND circuit 34
determines that semiconductor element 1 is in the short-circuited state, and outputs
determination signal Sj having the H level. AND circuit 34 may be formed of a
10 combination of NAND circuits.
[0118] As described above, when both the first and second physical quantities satisfy
the predetermined condition (when signals Sc1 and Sc2 both have the H level), short
circuit determination unit 3 according to the second configuration example determines
that semiconductor element 1 is in the short-circuited state. That is, short circuit
15 determination unit 3 may be configured to determine the short-circuited state of
semiconductor element 1 based on a correlation between the first and second physical
quantities.
[0119] Short circuit determination unit 3 according to the second configuration
example may also output wrong determination signal Sj when the above-described
20 correlation between the two physical quantities changes abruptly due to the application
of noise during the Miller period in the turn-on operation or the start of the turn-off
operation. Since this wrong determination signal Sj is attenuated or cut off by filter 4
in the subsequent stage, input of wrong determination signal Sj to controller 2 is
blocked. Thus, it is possible to prevent such a malfunction that controller 2 controls
25 semiconductor element 1 to the off state based on wrong determination signal Sj.
[0120] Sixth Embodiment
In a sixth embodiment, the semiconductor device according to the first
embodiment is applied to a power conversion device. The following is a description
of the case in which the present disclosure is applied to a three-phase inverter.
- 27 -
[0121] Fig. 12 is a block diagram showing a configuration of a power conversion
system to which the power conversion device according to the sixth embodiment is
applied.
[0122] As shown in Fig. 12, the power conversion system includes a power supply
5 1000, a power conversion device 2000 and a load 3000. Power supply 1000 is a DC
power supply and supplies DC power to power conversion device 2000. Power
supply 1000 can be implemented by various components, e.g., a DC system, a
photovoltaic cell and a storage battery. Alternatively, power supply 1000 may be
implemented by a rectifier circuit or an AC/DC converter connected to an AC system.
10 Alternatively, power supply 1000 may be implemented by a DC/DC converter that
converts current power supplied from the DC system into electric power made
available to load 3000.
[0123] Power conversion device 2000 is a three-phase inverter connected between
power supply 1000 and load 3000, and converts DC power supplied from power supply
15 1000 into three-phase AC power and supplies the three-phase AC power to load 3000.
As shown in Fig. 12, power conversion device 2000 includes a main conversion circuit
2010 that converts DC power into AC power, and a control circuit 2030 that outputs, to
main conversion circuit 2010, a control signal for controlling main conversion circuit
2010.
20 [0124] Load 3000 is a three-phase motor driven by the AC power supplied from power
conversion device 2000, and is used, for example, as a motor for a hybrid vehicle, an
electric vehicle, a rolling stock, an elevator, or an air conditioner.
[0125] Details of power conversion device 2000 will be described below. Main
conversion circuit 2010 includes a switching element (not shown), and switching of the
25 switching element causes main conversion circuit 2010 to convert the DC power
supplied from power supply 1000 into AC power and supply the AC power to load
3000. Although there are various specific circuit configurations of main conversion
circuit 2010, main conversion circuit 2010 according to the present embodiment is a
two-level three-phase full-bridge circuit and can be formed of six switching elements
- 28 -
and six freewheeling diodes connected in antiparallel to the switching elements,
respectively. Main conversion circuit 2010 includes a semiconductor device 2020
including each switching element and a drive circuit that drives each switching element.
Each switching element and each drive circuit included in semiconductor device 2020
5 correspond to semiconductor element 1 and drive circuit 100 of the semiconductor
device according to the first embodiment described above. The six switching
elements are connected in series in pairs to form upper and lower arms, and each pair of
the upper and lower arms forms each phase (U phase, V phase and W phase) of the
full-bridge circuit. Output terminals of each pair of the upper and lower arms, i.e.,
10 three output terminals of main conversion circuit 2010 are connected to load 3000.
[0126] Control circuit 2030 controls the switching elements of main conversion circuit
2010 such that desired electric power is supplied to load 3000. Specifically, based on
the electric power to be supplied to load 3000, the time (on time) at which each
switching element of main conversion circuit 2010 should be turned on is calculated.
15 For example, main conversion circuit 2010 can be controlled by PWM control in which
the on time of each switching element is modulated in accordance with a voltage to be
output. A control command (control signal) is output to the drive circuit of main
conversion circuit 2010 such that an on signal is output to a switching element that
should be turned on and an off signal is output to a switching element that should be
20 turned off at each point in time. In accordance with this control signal, the drive
circuit outputs the on signal or the off signal to the gate electrode of each switching
element as a drive signal.
[0127] In the power conversion device according to the sixth embodiment, the
semiconductor device according to the first embodiment is applied as semiconductor
25 device 2020 that forms main conversion circuit 2010. Therefore, the short-circuited
state of the semiconductor element can be detected with a simple circuit, similarly to
the first embodiment.
[0128] Although the example in which the present disclosure is applied to the two-level
three-phase inverter has been described in the sixth embodiment, the present disclosure
- 29 -
is not limited thereto and is applicable to various power conversion devices. Although
the present disclosure is applied to the two-level power conversion device in the sixth
embodiment, the present disclosure may be applied to a three-level or multi-level
power conversion device, or may be applied to a single-phase inverter when electric
5 power is supplied to a single-phase load. The present disclosure is also applicable to a
DC/DC converter or an AC/DC converter when electric power is supplied to a DC load
or the like.
[0129] In addition, the power conversion device to which the present disclosure is
applied is not limited to the above-described case in which the load is a motor, and can
10 also be used, for example, as a power supply device for an electric discharge machining
apparatus, a laser processing machine, an induction heating cooker, or a wireless power
transfer system. Furthermore, the power conversion device to which the present
disclosure is applied can also be used as a power conditioner for a photovoltaic power
generation system, a power storage system or the like.
15 [0130] It should be understood that the embodiments disclosed herein are illustrative
and non-restrictive in every respect. The scope of the present disclosure is defined by
the terms of the claims, rather than the description above, and is intended to include any
modifications within the scope and meaning equivalent to the terms of the claims.
REFERENCE SIGNS LIST
20 [0131] 1 power semiconductor element; 1c collector electrode; 1e emitter electrode; 1g
gate electrode; 2 controller; 3 short circuit determination unit; 4 filter; 5 buffer circuit;
6a on gate resistor; 6b off gate resistor; 7 optocoupler; 8 MOSFET; 11, 12, 14 ground;
13, 15 power supply node; 31 gate electrode physical quantity operation circuit; 31a
first gate electrode physical quantity operation circuit; 31b second gate electrode
25 physical quantity operation circuit; 32 short circuit determination circuit; 33a first
comparator; 33b second comparator; 34 AND circuit; 41 input terminal; 42 output
terminal; 100 drive circuit; 1000 power supply; 2000 power conversion device; 2010
main conversion circuit; 2020 semiconductor device; 2030 control circuit; 3000 load;
R1 to R6 resistor; C1 to C4 capacitor.

- 30 -
We Claim:
1. A drive circuit for a power semiconductor element that drives a power
semiconductor element including a gate electrode, a first main electrode and a second
5 main electrode, the drive circuit comprising:
a controller to control an opened/closed state of the power semiconductor
element based on an externally received command;
a short circuit determination circuitry to determine whether the power
semiconductor element is in a short-circuited state in a turn-on operation of the power
10 semiconductor element, and output a determination signal indicating a determination
result; and
a filter to receive the determination signal from the short circuit determination
circuitry, generate a delay signal of the determination signal, and output the delay
signal to the controller, wherein
15 a delay time of the filter is set to be longer than a length of a Miller period in the
turn-on operation of the power semiconductor element.
2. The drive circuit for the power semiconductor element according to claim 1,
further comprising
20 an on gate resistor connected between the controller and the gate electrode,
wherein
the delay time satisfies a relational equation given by an equation (1) below:
⋯ (1),
where  represents the delay time of the filter, Vg_on represents an on gate
25 voltage applied from the controller to the gate electrode, Vm represents a Miller
voltage of the power semiconductor element, Qgc represents an electric charge quantity
stored in a parasitic capacitance between the gate electrode and the first main electrode,
and Rg_on represents a resistance value of the on gate resistor.
- 31 -
3. The drive circuit for the power semiconductor element according to claim 1
or 2, wherein
the filter includes an RC circuit including a resistor and a capacitor, and
the delay time is set by using a time constant of the RC circuit.
5
4. The drive circuit for the power semiconductor element according to claim 3,
wherein
the filter further includes:
an input terminal to receive the determination signal;
10 an output terminal to output the delay signal; and
an optocoupler connected between the input terminal and the output
terminal, and
the resistor and the capacitor are connected at least one of between the input
terminal and the optocoupler and between the optocoupler and the output terminal.
15
5. The drive circuit for the power semiconductor element according to any
one of claims 1 to 4, wherein
the short circuit determination circuitry is connected to the gate electrode, and
determines whether the power semiconductor element is in the short-circuited state,
20 based on at least one physical quantity obtained at the gate electrode in the turn-on
operation.
6. The drive circuit for the power semiconductor element according to claim 5,
wherein
25 the at least one physical quantity includes a first physical quantity and a second
physical quantity, and
the short circuit determination circuitry determines whether the power
semiconductor element is in the short-circuited state, based on a correlation between
the first physical quantity and the second physical quantity.
- 32 -
7. The drive circuit for the power semiconductor element according to any
one of claims 1 to 6, wherein
the power semiconductor element is an element made of any one of silicon,
5 silicon carbide, gallium nitride, and gallium oxide.
8. A semiconductor device comprising the drive circuit and the power
semiconductor element as recited in any one of claims 1 to 7.
10 9. A power conversion device comprising:
a main conversion circuit including the drive circuit and the power
semiconductor element as recited in any one of claims 1 to 7, to convert input electric
power and output the electric power; and
a control circuit to output, to the main conversion circuit, a control signal for
15 controlling the main conversion circuit.