Claims:1. An apparatus comprising:
a port comprising circuitry to implement one or more layers of an interconnect protocol, wherein the port comprises an agent to:
obtain data to be transmitted to another device over a link based on the interconnect protocol via a packet, wherein the packet is to comprise a header;
determine that a value for a particular header field of the packet can be inferred by the other device based on one or more header field values for a previously transmitted packet; and
cause a header to be constructed for the packet, wherein the header is to be constructed to omit the particular header field from the packet header based on determining that the value for the particular header field may be inferred by the other device;
wherein the port is to use the circuitry to transmit the packet with the header to the other device.
, Description:CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of and priority from U.S. Provisional Patent Application No. 62/866,396 entitled “Predictive Packet Header Compression” and filed June 25, 2019, the entire disclosure of which is incorporated herein by reference.

FIELD
[0002] This disclosure pertains to computing systems, and in particular (but not exclusively) to predictive header compression for packets.

BACKGROUND
[0003] Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.
[0004] As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. Servers may also be implemented using distributed computing, in rack scale architectures, and other alternative implementations. As the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.
[0005] In fact, interconnects have grown from more traditional multi-drop buses that primarily handled electrical communications to full blown interconnect architectures that facilitate fast communication. Unfortunately, as the demand for future processors to consume at even higher-rates corresponding demand is placed on the capabilities of existing interconnect architectures.

BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 illustrates an embodiment of a computing system including an interconnect architecture.
[0007] FIG. 2 illustrates an embodiment of a interconnect architecture including a layered stack.
[0008] FIG. 3 illustrates an embodiment of a request or packet to be generated or received within an interconnect architecture.
[0009] FIG. 4 illustrates an embodiment of a transmitter and receiver pair for an interconnect architecture.
[0010] FIG. 5 is a diagram illustrating an example packet compression technique.
[0011] FIGS. 6A-6D are flow diagrams illustrating example processes for the packet compression technique shown in FIG. 5.
[0012] FIG. 7 is a diagram illustrating another example packet compression technique.
[0013] FIGS. 8A-8D are flow diagrams illustrating example processes for the packet compression technique shown in FIG. 7.
[0014] FIG. 9 is a diagram showing an example PCIe-based memory request packet header format.
[0015] FIG. 10 is a diagram showing an example PCIe-based completion packet header format.
[0016] FIG. 11 is a diagram showing another example PCIe-based memory request packet header format.
[0017] FIG. 12 is a diagram showing another example PCIe-based completion packet header format.
[0018] FIG. 13 is a diagram showing an example PCIe-based packet header format that has been compressed.
[0019] FIG. 14 is a diagram showing an example PCIe-based packet header format that has been compressed.
[0020] FIG. 15 is a diagram showing an example PCIe-based packet header format that has been compressed.
[0021] FIG. 16 is a flow diagram of an example process of compressing a packet.
[0022] FIG. 17 is a flow diagram of an example process of decompressing a packet.
[0023] FIG. 18 illustrates an embodiment of a block diagram for a computing system including a multicore processor.
[0024] FIG. 19 illustrates an embodiment of a block for a computing system including multiple processors.

DETAILED DESCRIPTION
[0025] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system haven’t been described in detail in order to avoid unnecessarily obscuring the present invention.