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Printed Board

Abstract: A printed circuit substrate (1) includes a circuit unit (2), a first main frame ground interconnection (10), a first sub frame ground interconnection (15) spaced away from the first main frame ground interconnection (10) in a first direction, and a first conductive via (20) connecting the first main frame ground interconnection (10) and the first sub frame ground interconnection (15) to each other.    In plan view from the first direction, a second outer periphery of the first sub frame ground interconnection (15) is surrounded by a first outer periphery of the first main frame ground interconnection (10). Thus, a printed circuit substrate (1) that can prevent the circuit unit (2) from malfunctioning can be provided. FIGURE 1

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Patent Information

Application #
Filing Date
04 December 2018
Publication Number
08/2019
Publication Type
INA
Invention Field
PHYSICS
Status
Email
patent@depenning.com
Parent Application
Patent Number
Legal Status
Grant Date
2022-03-25
Renewal Date

Applicants

MITSUBISHI ELECTRIC CORPORATION
7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.

Inventors

1. AKASHI, Norihiko
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
2. ONO, Hiroyuki
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
3. MIHARA, Hiroshi
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
4. IRIFUNE, Yoshiaki
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
5. KOYAMA, Daisuke
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
6. YONEOKA, Yudai
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
7. MIYASAKA, Takashi
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.
8. KASAHARA, Shimpei
c/o MITSUBISHI ELECTRIC CORPORATION, 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310, Japan.

Specification

WE CLAIM:
1. A printed circuit substrate comprising:
an external interface;
a case containing the external interface;
a circuit unit electrically connected to the external interface;
a first main frame ground interconnection electrically connected to the case;
a first sub frame ground interconnection spaced away from the first main frame ground interconnection in a first direction so as to be opposite to the first main frame ground interconnection; and
a first conductive via connecting the first main frame ground interconnection and the first sub frame ground interconnection to each other,
the circuit unit being spaced away from the first main frame ground interconnection, the first sub frame ground interconnection, and the first conductive via in a second direction intersecting the first direction,
in plan view from the first direction, a second outer periphery of the first sub frame ground interconnection being surrounded by a first outer periphery of the first main frame ground interconnection.
2. The printed circuit substrate according to claim 1, wherein
the first sub frame ground interconnection is configured so that an
electromagnetic noise propagating on the first main frame ground interconnection is resonantly coupled to the first sub frame ground interconnection.
3. The printed circuit substrate according to claim 1 or 2, further comprising a second conductive via connecting the first main frame ground interconnection and the first sub frame ground interconnection to each other.
4. The printed circuit substrate according to claim 1 or 2, further comprising:

a second sub frame ground interconnection spaced away from the first sub frame ground interconnection in the first direction so as to be opposite to the first sub frame ground interconnection; and
a third conductive via connecting the first sub frame ground interconnection and the second sub frame ground interconnection to each other,
the first sub frame ground interconnection being disposed between the first main frame ground interconnection and the second sub frame ground interconnection,
in the plan view from the first direction, a third outer periphery of the second sub frame ground interconnection being surrounded by the first outer periphery of the first main frame ground interconnection.
5. The printed circuit substrate according to claim 1 or 2, further comprising:
a second sub frame ground interconnection spaced away from the first main
frame ground interconnection in the first direction so as to be opposite to the first main frame ground interconnection; and
a third conductive via connecting the first main frame ground interconnection and the second sub frame ground interconnection to each other,
the second sub frame ground interconnection being spaced away from the first sub frame ground interconnection in a third direction intersecting the first direction and the second direction,
in the plan view from the first direction, a third outer periphery of the second sub frame ground interconnection being surrounded by the first outer periphery of the first main frame ground interconnection.
6. The printed circuit substrate according to claim 4 or 5, wherein, in the plan view from the first direction, the second sub frame ground interconnection is different in shape from the first sub frame ground interconnection.
7. The printed circuit substrate according to claim 1 or 2, further comprising:

a second main frame ground interconnection spaced away from the first sub frame ground interconnection in the first direction so as to be opposite to the first sub frame ground interconnection; and
a plurality of fourth conductive vias connecting the first main frame ground interconnection and the second main frame ground interconnection to each other,
the first sub frame ground interconnection being disposed between the first main frame ground interconnection and the second main frame ground interconnection,
in the plan view from the first direction, the second outer periphery of the first sub frame ground interconnection being surrounded by a fourth outer periphery of the second main frame ground interconnection,
in the plan view from the first direction, the plurality of fourth conductive vias surrounding the first sub frame ground interconnection.
8. The printed circuit substrate according to claim 7, further comprising a fifth conductive via connecting the first sub frame ground interconnection and the second main frame ground interconnection to each other.
9. The printed circuit substrate according to any one of claims 1 to 8, wherein the first sub frame ground interconnection has a meandering shape.
10. The printed circuit substrate according to any one of claims 1 to 9, further
comprising a first electronic component,
the first main frame ground interconnection being connected to the first conductive via through the first electronic component.
11. The printed circuit substrate according to any one of claims 1 to 10,
further comprising a second electronic component,
the first main frame ground interconnection including:
a first main frame ground interconnection portion; and

a second main frame ground interconnection portion spaced away from the first main frame ground interconnection portion,
the first main frame ground interconnection portion being connected to the second main frame ground interconnection portion through the second electronic component.

Documents

Application Documents

# Name Date
1 201847045725.pdf 2018-12-04
2 201847045725-TRANSLATIOIN OF PRIOIRTY DOCUMENTS ETC. [04-12-2018(online)].pdf 2018-12-04
3 201847045725-STATEMENT OF UNDERTAKING (FORM 3) [04-12-2018(online)].pdf 2018-12-04
4 201847045725-REQUEST FOR EXAMINATION (FORM-18) [04-12-2018(online)].pdf 2018-12-04
5 201847045725-PROOF OF RIGHT [04-12-2018(online)].pdf 2018-12-04
6 201847045725-PRIORITY DOCUMENTS [04-12-2018(online)].pdf 2018-12-04
7 201847045725-POWER OF AUTHORITY [04-12-2018(online)].pdf 2018-12-04
8 201847045725-FORM 18 [04-12-2018(online)].pdf 2018-12-04
9 201847045725-FORM 1 [04-12-2018(online)].pdf 2018-12-04
10 201847045725-FIGURE OF ABSTRACT [04-12-2018].jpg 2018-12-04
11 201847045725-DRAWINGS [04-12-2018(online)].pdf 2018-12-04
12 201847045725-DECLARATION OF INVENTORSHIP (FORM 5) [04-12-2018(online)].pdf 2018-12-04
13 201847045725-COMPLETE SPECIFICATION [04-12-2018(online)].pdf 2018-12-04
14 201847045725-CLAIMS UNDER RULE 1 (PROVISIO) OF RULE 20 [04-12-2018(online)].pdf 2018-12-04
15 Correspondence by Agent_Form1_06-12-2018.pdf 2018-12-06
16 201847045725-RELEVANT DOCUMENTS [12-12-2018(online)].pdf 2018-12-12
17 201847045725-MARKED COPIES OF AMENDEMENTS [12-12-2018(online)].pdf 2018-12-12
18 201847045725-FORM 13 [12-12-2018(online)].pdf 2018-12-12
19 201847045725-AMMENDED DOCUMENTS [12-12-2018(online)].pdf 2018-12-12
20 201847045725-Retyped Pages under Rule 14(1) (MANDATORY) [10-01-2019(online)].pdf 2019-01-10
21 201847045725-2. Marked Copy under Rule 14(2) (MANDATORY) [10-01-2019(online)].pdf 2019-01-10
22 201847045725-FORM 3 [13-02-2019(online)].pdf 2019-02-13
23 201847045725-FER.pdf 2020-07-13
24 201847045725-OTHERS [10-12-2020(online)].pdf 2020-12-10
25 201847045725-Information under section 8(2) [10-12-2020(online)].pdf 2020-12-10
26 201847045725-FORM-26 [10-12-2020(online)].pdf 2020-12-10
27 201847045725-FORM 3 [10-12-2020(online)].pdf 2020-12-10
28 201847045725-FER_SER_REPLY [10-12-2020(online)].pdf 2020-12-10
29 201847045725-DRAWING [10-12-2020(online)].pdf 2020-12-10
30 201847045725-CLAIMS [10-12-2020(online)].pdf 2020-12-10
31 201847045725-ABSTRACT [10-12-2020(online)].pdf 2020-12-10
32 201847045725-FORM 3 [01-03-2021(online)].pdf 2021-03-01
33 201847045725-FORM 3 [11-01-2022(online)].pdf 2022-01-11
34 201847045725-PatentCertificate25-03-2022.pdf 2022-03-25
35 201847045725-IntimationOfGrant25-03-2022.pdf 2022-03-25

Search Strategy

1 search_201847045725E_04-06-2020.pdf

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