[001] The present invention relates to a process for
fabricating a microelectromechanical systems devices (MEMSDs) with a die-to-die isolation of the MEMSDs.
Background of the invention
[002] Micro-Electro-Mechanical Systems (MEMS) include
miniaturized mechanical and electro-mechanical elements (i.e., devices and structures) that are microfabricated. MEMS structures are designed specifically to perform necessary actions under stimuli effect. These MEMS structures transduce physical, optical, chemical effects to electrical signals, are called sensors and vice-versa are called actuators. The mechanical elements of MEMS include beams, proof-mass, anchors, and perforations. Whereas, the electrical elements, which form conductive parts in these structures, are used to integrate with actuation and sensing functionalities of the MEMS structure. Capacitance or Electrostatic-based MEMS structures possess deformable dielectric media between the electro-mechanical parts. These are predominantly used in various applications, where under stimuli, one of the parts vibrates or deforms against other stationary parts of the structure, causing deformation of a dielectric medium, resulting in the change in the capacitance as a sensor and the parts with different electrical potentials cause an electrostatic force between them, resulting deformation or vibration of one of the part, called as electrostatic actuator.

[003] These devices (or systems) have the ability to sense,
control and actuate on the micro scale, and generate effects on the macro scale.
[004] Generally, micro fabrication of micro-electro-
mechanical systems (MEMS) devices involves surface micromachining that is limited by structural layer thickness for a device, thereby compromising the performance of the device. In this micromachining process, even though the fabrication is carried out at a wafer scale, but the release of MEMSDs are achieved at the die level (individual MEMSDs are released), which happens after dicing process.
[005] In an alternate method of as bulk micromachining of
silicon on insulator (SOI) based structures to obtain the
corresponding MEMS structures, such a method demonstrates
parasitic effects affecting the performance of the MEMSDs.
Parasitic capacitance or effect is an unavoidable and usually
unwanted capacitance that exists between the parts of an
electronics components. In MEMSDs, the insulation material and
substrate are the main media that cause unwanted capacitances.
This capacitance directly affect the signal level over noise floor.
Whereas, in this known method of micromachining, in spite of
the release of MEMSDs at wafer level, the step of dicing that is
used to isolate MEMSDs dies, is expensive (laser dicing) and
requires additional polymer coating process.
[006] Whereas, in other methods for protecting MEMSDs
wafer by adhesive bonding of cap wafer during the dicing process, these methods require cap wafer fabrication resulting in extra cost in the fabrication process.

[007] In wafer level release method, multiple and different
MEMS devices are created on a same substrate and released all
suspended structures in batch process at wafer level. Whereas,
in die level release method though several structures are created
on substrate, the devices are released individually after dicing.
[008] One of essential design parameters of MEMS based
inertial sensors (gyroscopes, accelerometers), is mass of the
structure. The heavier structures are achieved by higher thick
structure without compromising increase in lateral area.
However, the surface micromachining fabrication method limits
the thickness of MEMS structures, typically to less than 6 µm and
this method also induces intrinsic stresses and suffers from
stiction phenomenon. There have been wafer dissolving wafer
processes in combination with wafer bonding process for
realizing large MEMS devices. However, the structural thickness
is limited by the depth of boron doping but lot of intrinsic
stresses are induced by this doping process.
[009] In a publication (J. Micromech. Microeng. 27 (2017)
015005 (8pp)), titled "Si-gold-glass hybrid wafer bond for 3D-MEMS and wafer level packaging", by the inventors of the present invention, a hybrid bonding process was disclosed where the process combines anodic bond and eutectic bond processes at a low temperature of 3900C. However, the fabricated devices (MEMSDs) as obtained under this process, require a prior dicing before release of the devices. In other words, the release of MEMSDs is performed at a die level.

Objects of the present invention
[010] The primary object of the present invention is to
provide a process for fabricating a microelectromechanical
systems devices (MEMSDs), with negligible parasitic effects.
[011] An object of the present invention is to provide a
process for fabricating a microelectromechanical systems devices (MEMSDs) from a semiconductor base and a substrate, through a hybrid bonding.
[012] It is an object of the present invention is to provide a
process for micro fabricating a microelectromechanical systems devices (MEMSDs), where a dicing of only peripheral areas of structural patterns is performed.
[013] Another object of the present invention is to provide
a process for micro fabricating a microelectromechanical systems devices (MEMSDs), where the MEMSDs are released with die-to-die isolation, at wafer level.
Summary of the present invention
A process for fabricating a microelectromechanical systems devices (MEMSDs) is provided by initially forming at least a dimple on a semiconductor base. Electrode patterns are formed on a substrate and aligning the structural and electrode patterns and inverting the semiconductor base and adhering the inverted semiconductor base to the substrate through a hybrid bonding, to form a hybrid stack. The peripheral areas of the electrode patterns of the substrate are diced and the hybrid stack with the structural patterns and electrode patterns is disposed on a carrier wafer and the handle layer of the semiconductor base is removed. Finally, the silicon dioxide layer of the semiconductor base is etched and die-to-die removal of individual

microelectromechanical systems devices (MEMSDs) from the carrier wafer is performed, to obtain the microelectromechanical systems devices (MEMSDs) with movable and stationary electrode structures.
Brief description of the drawings
[014] FIG.1 is a schematic illustration of a SOI wafer as an
exemplary semiconductor base for fabricating MEMSDs, in
accordance with the process steps of the present invention.
[015] FIG.2(a) and 2(b) are schematic illustrations of the
exemplary semiconductor base for fabricating MEMSDs with a
dimple mask and a dimple pattern, respectively, on a device
silicon layer.
[016] FIG.3(a) and FIG.3b are schematic illustrations of
the exemplary semiconductor base for fabricating MEMSDs with
a structural mask and a structure pattern, respectively, on the
device silicon layer.
[017] FIG.4 is a schematic illustration of an exemplary
substrate, which is a sodium enriched glass wafer.
[018] FIG.5(a) and FIG.5(b) are schematic illustrations of
the exemplary substrate with an electrode mask and an
electrode pattern.
[019] FIG.6 is a schematic illustration of a hybrid wafer
bond between the substrate and the SOI wafer.
[020] FIG.7 is a schematic illustration of a step of dicing of
only the substrate.
[021] FIG.8 is a schematic illustration of an arrangement
of the diced substrate on a carrier wafer.
[022] FIG.9 is a schematic illustration of the MEMSDs
device subsequent to the removal of silicon handle layer.

[023] FIG.10 is a schematic illustration of the MEMSDs of
the present invention depicting the removal buried oxide layer.
[024] FIG.11(a) is a schematic illustration of the MEMSDs
as obtained by using the process steps of the present invention after its die-to-die isolation at wafer scale.
[025] FIG.11(b) is a perspective view of the MEMSDs of
the present invention depicting die-to-die isolation at wafer scale.
[026] FIG.12 is a schematic illustration of the flow chart
for the process of MEMSDs of the present invention after its die-to-die isolation at wafer scale.
[027] FIGs.13-16 illustrate exemplary applications of the
MEMSDs as obtained by the process steps of the present invention.
Detailed description of the invention
[028] Accordingly, the present invention provides a process
for fabricating a microelectromechanical systems devices (MEMSDs), where the MEMSDs are released at wafer level, with a die-to-die isolation.
[029] The process steps of the present invention can be
suitably used to overcome the limitations in achieving a thicker MEMSDs, since the MEMSDs with higher thickness are desirable achieve a higher inertia sensitivity, which is the deflection sensitivity of the MEMSDs when they are subjected to acceleration or force.
[030] The process steps of the present invention are now
described in conjunction with the accompanied drawings, where FIG.1 illustrates a semiconductor base 1. In the present invention silicon on insulator (SOI) wafer, is used as a preferred

structural material for the fabrication of MEMSDs of the present invention. Alternately, in place of a SOI wafer, the semiconductor base 1 can also be formed from a silicon dioxide layer and a device silicon layer, where the silicon dioxide layer is formed by any suitable methods such as deposition-plasma enhanced chemical vapour deposition (PECVD), chemical vapour deposition (CVD), low-pressure chemical vapour deposition (LP-CVD) and grown further with a dry or wet oxidation step. The thickness of the semiconductor base 1 can be in the range of 200µm to 350µm. The semiconductor base 1 includes a device silicon layer 2, a handle layer 4 and a silicon dioxide layer 3 disposed in between device silicon layer 2 and handle layer 4. The diameter of the semiconductor base 1 can be in the range of 1-18 inches.
[031] SOI wafer as a semiconductor base 1, the device
silicon layer 2 is formed from a monocrystalline silicon having a
thickness, preferably in the range of 2µm to 500 µm. The device
silicon layer 2 is also doped with suitable dopants such as N-type
or P-type dopants, in order to enable metal-free contacts and to
achieve an optimal electrical conductivity for the device silicon
layer 2. The thickness of the device silicon layer 2.
[032] In a SOI wafer as a semiconductor base 1, the
handle layer 4 is preferably made of a monocrystalline silicon, having a thickness in the range of 100 µm to 350 µm. The electrical resistivity can be less than 0.1-100 ohm-cm. The handle layer 4 is also doped with suitable dopants such as N-type or P-type dopants, so as to achieve an optimal electrical conductivity. In a schematic illustration as shown in drawings the handle layer 4 is shown as thicker than the device silicon layer

2. Whereas, the thickness of the handle layer 4 is preferred to have a smaller thickness as compared with the thickness of device silicon layer 2.
[033] In a SOI wafer as a semiconductor base 1, the silicon
dioxide layer 3 is formed between the device silicon layer 2 and the handle layer 4. The thickness of the buried silicon dioxide layer 3, is preferably in the range of 250 nm to 5 µm. The buried silicon dioxide layer 3 of lesser thickness is preferred, which is sufficient to act as an etch stopper during the etching of the device silicon layer 2. The buried silicon dioxide layer 3 can be formed by suitable methods such as separation by implantation of oxygen (SIMOX) method or by methods. The electrical resistivity of the buried silicon dioxide layer 3 is about 1017 Ohm-cm.
[034] Now, turning to FIG.2(a), an initial step of
formation of a dimple mask 5 are described. The dimple mask 5 is formed with at least a dimple pattern 6(a), where a photoresist polymer is used as a soft masking material. The desired dimple pattern 6(a) is transferred on to the device silicon layer 2 as dimples 6(b) by photolithography by etching the device silicon layer 2 as shown in FIG2(b). The shapes of the dimples 6(b) can be in the form of polygon, circular and other suitable non-circular geometries. It is understood here that the selection of suitable masking material is made based on the selectivity between the dimple mask 5 and the required level of depth of the dimples 6(b) on the device silicon layer 2. Usually, the masking material thus used is silicon dioxide or silicon nitride. Whereas, in the present process step, advantageously, a photoresist, a light sensitive material (for example AZ4562,

S1813) is used as a masking material for etching device silicon
layer 2, to form the desired dimples 6(b), using a reactive-ion-
etching method (RIE). The depth of the etched dimples 6(b)
thus formed, defines an electrostatic gap between the device
silicon layer 2 and a bottom electrode 21, which in turns
determines the effective electrostatic gap 22, as particularly
shown in FIG.11(a). The effective electrostatic gap 22 is true
gap between device silicon layer 2 and bottom electrode 21 after
considering the thickness of electrode pattern 11.
[035] Once the dimple patterns 6(b) are formed on the
device silicon layer 2, a pre-defined mask 7, as shown in
FIG.3(a), is prepared to form a template for the desired
functional elements, for the resultant MEMSDs, where the
functional elements include structural shapes, beams, proof-
mass, and comb-fingers etc., which respond to an external
stimuli or an applied electrical potential. The mask 7 is used to
form structure patterns 8(a) as shown in FIG.3(a). This
structure pattern 8(a) of the mask 7, is transferred on to the
device silicon layer 2, by etching, preferably as deeply etched
structure patterns 8(b), to accommodate the desired functional
elements for the resultant microelectromechanical systems
(MEMSDs). The structure patterns 8(b) in device silicon layer 2
are achieved by deep-reactive-ion etching (DRIE). In this step,
the silicon dioxide layer 3 acts as an etch stopper during DRIE.
The structure mask 7 is aligned with the dimple pattern 6(a)
and the device silicon layer 2 is etched by deep reactive ion
etching till the buried oxide layer 3 is exposed.
[036] The dimples 6(b) thus formed define an anchor
region 17 and the depth of the etch defines the electrostatic gap

between the structure, which is a moving part 20 and the electrode, which is a stationary part 21, of the MEMSD, as particularly shown in FIG.11(a).
[037] The device silicon layer 2 of the semiconductor base
1 is highly doped with boron impurities to obtain holes as
majority charge carries and high electrical conductivity to act as
conductive moving part 20. The hole majority enhances the
speed of anodic process during hybrid bonding process.
[038] Thereafter, as shown in FIG.4, a substrate 9, which
is preferably made of a sodium enriched glass (Pyrex), having a
sodium oxide, boron trioxide, aluminium oxide, magnesium
oxide, zinc oxide, and arsenic oxide. These compounds in the
glass substrate 9 are essential in an anodic bond formation at
the interface of the device silicon layer 2 and the substrate 9.
[039] The suitable material for the substrate 9 is required
to possess a thermal coefficient of expansion that matches with device silicon layer 2, in order to provide an anchor region 17 with negligible stresses to result in enhancement of the device performance.
[040] Other suitable materials, which can be suitably
adopted for use for the substrate 9 include, silicon with a
borosilicate glass layer, quartz wafer and a low temperature co-
fired ceramic(LTCC). In the present invention the use of
preferred glass substrate 9 provides several advantages such as,
high wafer bond strength, high electrical insulation, negligible
parasitic effects in signal conditioning and a low cost as
compared to other substrate materials as listed above.
[041] An electrode mask 10 is prepared as shown in
FIG.5(a) and the corresponding electrode patterns 11 are

transferred on the surface of the glass substrate 9, as particularly shown in FIG.5(b). The electrode patterns 11 include electrical connections for moving and stationary electrodes 20 and 21 of the MEMSDs. The electrode pattern 11 or the formation of the electrodes, is preferably formed by a lift¬off method or by a metal etching method, by disposing at least a seed layer on the substrate and depositing at least a conductive layer of on the seed layer. The seed layer is selected from the group consisting of chromium, titanium, nickel, copper oxide, aluminum oxide or a combination thereof. Whereas, the conductive layer is selected from the group consisting of gold, aluminum, copper, titanium, magnesium or a combination thereof. In an exemplary embodiment, the electrode pattern 11, is formed preferably with a stack of chromium (Cr) and gold (Au) layers (seed and conductive layers), having thicknesses in the range of 10-30nm and 55-110nm, respectively. The seed layer (chromium layer) is advantageously used for impart adhesion between the substrate 9 (glass) and the layer of gold (conductive layer) 11.
[042] Once, the electrode pattern 11 is formed on the
substrate 9, the step of bonding of the substrate 9 with the processed semiconductor base 1 is performed, as shown in FIG.6. In this step the semiconductor base 1 and the substrate 9 are inverted and aligned at die level with EVG-620 double side aligner, where peripheral areas of structural patterns 8(b) on the semiconductor base 1 and the substrate 9 are monitored for alignment. The aligned semiconductor base 1 and the substrate 9 is loaded into a wafer bonder (EVG-501) and bonded using a hybrid wafer bonding method, at a temperature of about 390oC.

The bonding method is a heterogeneous wafer bonding, where anodic and eutectic bonds are bonded simultaneously at different regions of interfaces. The anodic bond is formed at an interface of glass substrate 7 and device silicon layer 2 and whereas the eutectic bond is formed at the interface of the device silicon layer 2 and the electrode pattern 11.
[043] Anodic bond interface creates a mechanically strong
support 19 in the anchor region 17 and the eutectic interface 23
forms an electrical connection between device silicon layer 2 and
electrode pattern 11. By using hybrid wafer bonding process, the
semiconductor base 1 and the substrate 9 are permanently
bonded together to form a bonded wafer stack 12.
[044] The bonded wafer stack 12 is partially diced, as
shown in FIG.7 to form dicing grooves 13. In this step, the bonded wafer stack 12 is mounted on a dicing tape 14 to hold firmly during the dicing process refer to FIG.8. The dicing tape 14 is an adhesive tape with ultraviolet light sensitive glue. Using mechanical dicing process, a part of the glass wafer 9 is completely diced through the thickness by creating the grooves 13. The electrode pattern 11 defines the dicing area and it is visible through the glass substrate 9 during dicing. The dicing depth is estimated using the thickness of individual wafers and the dicing tape 14 thickness.
[045] After separating the partially diced wafer stack 12
from the dicing tape 14, the wafer stack 12 is cleaned with organic contamination, in the presence of removal agents such as acetone, PG removal, isopropyl alcohol or a piranha solution. Further, the handle layer 4 is etched completely as shown in FIG.9.

[046] Subsequent to the etching of the handle layer 4 the
buried silicon dioxide layer 3 is also etched by reactive ion
etching (RIE). The MEMSD as obtained after the complete
etching of the buried silicon dioxide layer 3 is as shown in
FIG.10. The released MEMS structures are isolated with die-to-
die separation at the wafer level after buried oxide layer etch.
The individual dies are un-mounted from the carrier wafer 16.
[047] FIG.11(a) shows the illustration of completely
realized capacitance based MEMS device with electrostatic gap
22. Under external stimuli, the moving part 20 moves against
stationary part 21, resulting in the deflection causing variation in
electrostatic gap 22. The change gap produce equivalent
electrical signal corresponding to effect of stimuli.
[048] FIG.11(b) shows the realization of MEMSDs
realization using the presented innovation. Top row of MEMSDs are separated from the carrier wafer 16.
[049] A sequential process flow of the process steps of the
present invention is now described by particularly referring to FIG.12. In the process steps of the present invention for the fabrication of microelectromechanical systems devices (MEMSDs), the process steps comprising, initially forming the dimple or dimples on the semiconductor base and aligning the structural patterns within the dimple or dimples, where the semiconductor base having the device silicon layer, the handle layer and the silicon dioxide layer, where the silicon dioxide layer is disposed between the device silicon layer and the handle layer. Subsequently, the electrode patterns are formed on the substrate. Once the electrode patterns with electrodes are formed on the substrate, the structural and electrode patterns

are aligned and the semiconductor base is inverted and adhered
to the substrate through a hybrid bonding, resulting in a hybrid
stack of the semiconductor base and the substrate. The bonded
hybrid stack is then diced and the dicing is performed in
peripheral areas of the electrode patterns of the substrate. The
diced hybrid stack with the structural patterns and electrode
patterns is then disposed on the carrier wafer and the handle
layer of the semiconductor base is removed. Only the silicon
dioxide layer of the semiconductor base is then etched, to
facilitate die-to-die removal of individual microelectromechanical
systems devices (MEMSDs) from the carrier wafer.
[050] In yet another aspect of the process steps of the
present invention, the material for the semiconductor base is
preferably a SOI wafer. Alternately, the material for the
semiconductor base can be sapphire, germanium, silicon carbide
or a quartz having a silicon oxide layer and a device silicon layer.
[051] In another aspect of the process steps of the present
invention, the shape of the dimples on the semiconductor base can be one of polygon, a circle or an ellipse or a combination of these shapes.
[052] In yet another aspect of the process steps of the
present invention, the step of forming of the dimples is performed by a reactive ion etching and the step of aligning the structure pattern within the dimple is performed by plasma etching.
[053] In a further aspect of the process steps of the
present invention, the material for the substrate is selected from the group consisting of sodium enriched glass, silicon with a

borosilicate glass layer, quartz wafer and a low temperature co-
fired ceramic(LTCC), preferably sodium enriched glass.
[054] In yet another aspect of the process steps of the
present invention, the forming of the electrode patterns on the substrate is performed by disposing at least a seed layer on the substrate and depositing at least a conductive layer of on at least the seed layer. The material for the seed layer is selected from the group consisting of chromium, titanium, nickel, copper oxide, aluminum oxide or a combination thereof and whereas the material for the conductive layer is selected from the group consisting of gold, aluminum, copper, titanium, magnesium or a combination thereof.
[055] It is also an aspect of the process steps of the
present invention where at least one of the electrodes of the
electrode patterns of the substrate is stationary.
[056] The fabrication process of the present invention is
implemented to realize various MEMS structures having the MEMSDs of the present invention. For instance, a doubly clamped beam is as shown in FIG.13(a), which is SEM (Scanning Electron Microscope) image of double clamped beam and FIG.13(b) depicts the fundamental mode shape of beam. The beam actuated at its fundamental frequency to operate as a mass sensing MEMSDs. When the movable part is loaded with an external mass or analyte causing shift in fundamental frequency of the MEMSDs. The measure of change in frequency equivalent to mass of the analyte on movable part. The glass substrate being highly electrical insulator causing minimal parasitic capacitances resulting high resolution mass sensing MEMSDs.

[057] FIGs.14(a) is SEM image of an accelerometer and
FIG.14(b) depicts fundamental mode shape of the accelerometer. The accelerometer is used to measure the intensity of acceleration or shock or impact. Under the external acceleration, the movable part of the accelerometer experiences force causing deflection of the moving part towards stationary part resulting change in electrostatic gap. The gap change cause capacitance change of the accelerometer. The measure of change in capacitance is equivalent to intensity of acceleration or shock or impact. The higher thick moving part having better deflection sensitivity for external force resulting higher sensitive accelerometers.
[058] FIG.15(a) is SEM image of capacitive
micromachined ultrasound transducer (CMUT) and FIG.15(b) is a fundamental mode shape of CMUT. The CMUT is membrane or plate like structure anchored peripherally maintaining electrostatic gap between moving part and stationary part. The CMUT MEMSDs are used as actuators and sensors. Under applied oscillating electrical potential between the moving and stationary part produce ultrasound waves transmit in acoustic medium, these waves reflects at the interface of discontinuity of the acoustic medium. The reflected waves on CMUT sensor cause deflection of moving part result in change in capacitance. The measure of capacitance is equivalent to intensity of the reflected waves.
[059] FIG.16(a) is an SEM image of gyroscope and
FIG.16(b) is a mode shape in sense direction. The gyroscope MEMSDs are used to measure the angular rate of rotation. The vibratory gyroscopes works on the principles of Coriolis

acceleration. It combines lateral actuator and transverse accelerometer. The higher thick moving part enhance the electrostatic force due to increased in cross-sectional area. The external rotation on the gyroscope produce Coriolis acceleration in transverse direction causing deflection of moving part resulting change in capacitance. Similar to the accelerometer, thicker moving part enhance the deflection sensitivity. The present innovation advantageously produce thicker moving parts to obtain better sensitive MEMSDs.
[060] In case of an accelerometer, a capacitive
micromachined ultrasound transducer and a Coriolis vibratory
gyroscope, as an example, a 10 µm device silicon SOI wafer is
used to create 8.2 µm thick structures with 1.8 µm electrostatic
gap. These MEMS devices are electrostatically excited. A non-
contact Laser Doppler Vibrometer (LDV)—MSA 500 (Polytec
GmbH) is used to measure the dynamic response of these MEMS
devices. To minimize the effects of squeeze film damping, we
have developed in-house vacuum chamber system integrated
with the LDV. These devices are electrostatically actuated with
swept frequency and the frequency response is measured and
modal frequencies are analysed. Further, the accelerometer
structure is characterized for stiffness using Atomic Force
Microscopy (AFM). Tables 1 and 2 show a comparison between
the experimental and the simulated parameters. The error
percentage implies that the modified SOI-on-glass process
results in devices free from residual stresses.
[061] TABLE 1. Static Stiffness of the Accelerometer

Advantages of the present invention
[063] The process steps of the present invention offer die-
to-die isolation of the MEMSDs at wafer level. The microfabrication process of the present invention renders very compact devices with enhanced efficiency along with an ease of batch production. Compactness and performance of these MEMSDs having a lower power consumption, find applications IoT-based technologies. The process steps of the present invention avoids a physical damage to the hybrid stack during the course dicing, as it requires only a mechanical dicing and the yield of MEMSDs is also increased due to isolation of MEMSSDs at wafer level.

1. A process for fabricating a microelectromechanical systems
devices (MEMSDs), comprising:
- forming at least a dimple on a semiconductor base and aligning structural patterns within at least the dimple, where the semiconductor base includes a device silicon layer, handle layer and a silicon dioxide layer disposed between the device silicon layer and the handle layer;
- forming electrode patterns on a substrate;
- aligning the structural and electrode patterns and inverting the semiconductor base and adhering the inverted semiconductor base to the substrate through a hybrid bonding, to form a hybrid stack;
- dicing peripheral areas of the electrode patterns of the substrate;
- disposing the hybrid stack with the structural patterns and electrode patterns on a carrier wafer and removing the handle layer of the semiconductor base; and
- etching only the silicon dioxide layer of the semiconductor base to facilitate die-to-die removal of individual microelectromechanical systems devices (MEMSDs) from the carrier wafer.
2. The process as claimed in claim 1, wherein the material for
the semiconductor base is preferably a SOI wafer.

3. The process as claimed in claim 1, wherein the material for the semiconductor base is sapphire, germanium, silicon carbide or a quartz having a silicon oxide layer and a device silicon layer.
4. The process as claimed in claim 1, wherein the shape of the dimple is a polygon, a circle, an ellipse or a combination thereof.
5. The process as claimed in claim 1, wherein the step of forming of the dimple or dimples is performed by a reactive ion etching and the step of aligning the structure pattern within the dimple is performed by plasma etching.
6. The process as claimed in claim 1, wherein the material for the substrate is selected from the group consisting of sodium enriched glass, silicon with a borosilicate glass layer, quartz wafer and a low temperature co-fired ceramic(LTCC), preferably sodium enriched glass.
7. The process as claimed in claim 1, wherein the forming of the electrode patterns on the substrate is performed by disposing at least a seed layer on the substrate and depositing at least a conductive layer of on at least the seed layer.
8. The process as claimed in claim 7, wherein the material for the seed layer is selected from the group consisting of chromium, titanium, nickel, copper oxide, aluminum oxide or a combination thereof.
9. The process as claimed in claim 7, wherein material for the conductive layer is selected from the group consisting of

gold, aluminum, copper, titanium, magnesium or a combination thereof.
10. The process as claimed in claim 1, wherein at least one of the electrodes of the electrode patterns of the substrate is stationary.