Process for producing a printed circuit board
The invention relates to the field of printed circuit boards, and more
particularly to the mode of connection between various elementary circuit
5 boards.
Each elementary metallized circuit board forms a portion of the printed
circuit board. Conventionally, metallized holes passing through the
elementary circuit boards are produced so as to guarantee electrical contact
between the various elementary circuit boards. Preferably, the holes are only
10 drilled between the elementary circuit boards to be connected. For example,
for a printed circuit board comprising five elementary circuit boards, if only
the third and the fifth circuit board must be connected, only the third, fourth
and fifth circuit boards are perforated before being stacked to form a printed
circuit board.
15 It is known to use an intermediate layer preimpregnated with an
adhesive substance to adhesively bond the various elementary metallized
circuit boards together. Each intermediate layer must also be perforated,,
facing the metallized holes to be electrically connected, with a larger
diameter in order to take flow of the adhesive substance into account; in
20 other words, the diameter of the through-holes in the intermediate layers
must take into account the fact that deformation of the adhesive material
could obstruct some of the hole. With the increase in the number of
connections to be made, each intermediate layer is perforated with a
multitude of very closely spaced holes, thereby making it very difficult to
25 handle and limiting the possible density of connections.
A partial solution was provided by European patent EP 2 205 053.
This document describes the production of a printed circuit board
comprising at least two superposed elementary circuit boards that are
metallized on their two faces and at least one intermediate layer placed
between said circuit boards. The intermediate layer comprises a
thermoplastic material that is insensitive to chemical elements. With this type
of intermediate layer, there is no risk of the thermoplastic material flowing.
The process for producing the printed circuit board according to
5 document EP 2 205 053 may thus be summarized as follows. A ~1 first step consists in creating facing perforations in said elementary circuit boards and
in the intermediate layer in order to connect said circuit boards together. A
second step consists in lining the interior of the holes passing through the
elementary circuit boards and the intermediate layer with a metal surface. A
10 third step consists in covering the opening of the holes in the elementary
circuit boards to be connected with a first metal, and the opening of the holes
in the intermediate layer with a second metal. The first and second metal are
the constituents of an alloy. After stacking, a fourth step consists in applying
pressure so as to solder the metal surfaces that cover the openings of the
15 holes in the elementary circuit boards with the metal surfaces that cover the
I openings of the holes in the intermediate layer. The solder is achieved by
j
j
diffusion of the metals that then form an alloy.
One of the drawbacks of the embodiment provided in document EP 2
205 053 is that it runs into problems with mechanical tolerances. Specifically,
20 the height of the metallized surfaces that cover the opening of the holes is
greater than the height of the rest of the elementary circuit board. In order to
remove these height differences, the pressure applied to the stack must be
increased. The Increase in the pressure applied prevents presses that are
standard in the field of printed circuit boards from being used, and th~sty pe of
25 board from being manufactured on an industrial scale.
One aim of the invention is to compensate for these height differences
without increasing the pressure used to assemble the device.
According to one aspect of the invention, a process is provided for
producing a printed circuit board comprising at least two elementary circuit
30 boards drilled with metallized holes the mouth of which is covered with a first
metal, and at least one first intermediate layer, made of a compressible
material, drilled with holes facing the elementary circuit boards and the mouth
of which is covered with a second metal, which layer is placed between the
two elementary circuit boards and soldered to each of the circuits by
thermodifFusion of the two metals forming an alloy at a formation temperature
5 of the alloy, characterized in that at least two second intermediate layers, the
second intermediate layers not covering the first and second metal, being
thermoplastics and having a melting point above the formation temperature
of the alloy, are placed between the first intermediate layer and said
elementary circuit boards.
10 Adding at least two second intermediate thermoplastic layers having a
melting point above the formation temperature of the alloy by thermodiffusion
allows problems with mechanical tolerances to be limited and assembly
pressures that are standard in the printed circuit board industry to once more
be employed.
15 The invention will be better understood on studying a few embodiments
described by way of completely nonlimiting examples, and illustrated by the
appended drawings in which:
- figure 1 illustrates a method of implementing a process for producing a
printed circuit board according to one aspect of the invention;
20 - figure 2a shows a stack of the various constituent elements of a
printed circu~bt oard, according to one aspect of the invention;
- figure 2b shows the stack of the various constituent elements of a
printed circuit board in a press at a formation temperature T of the
alloy, according to one aspect of the invention; and
figure 2c shows the stack of the various constituent elements of a
printed circuit board in a press at a melting point Tf of the material of
the second intermediate layers, according to one aspect of the
invention.
Figure 1 succinctly summarizes the process for producing a printed circuit
board, according to the invention.
For example, a printed circuit board comprising at least two
5 elementary circuit boards, at least one first intermediate layer and at least
two second intermediate layers. Of course, this example is completely
nonlimiting.
A first step 10 comprises drilling facing holes TCEI, TcE2 in the
elementary circuit boards CEI, CE2 to be connected. Advantageously, the
lo elementary circuit boards CEI, CE2 may be composed of "RO 4003
(registered trademark), for example, and are covered, on at least one of their
faces, with a metallization layer CM, preferably a layer containing copper.
This step also comprises drilling a first intermediate layer that is placed
between the elementary circuit boards CEI, CE2 to be connected. The holes
is Tell formed are located facing the holes TcE1, TCE2 in the elementary circuit
boards CEI, CE2 to be connected. The first intermediate layer CI1 may be
made of "RT Duroid 6002" (registered trademark), for example, and is
covered with a metallization layer CMcll,, preferably a layer containing
copper.
20 A step 20 comprises covering, with a metal compound, the inside of
the holes formed in the elementary circuit boards CEI, CE2 and the first
intermediate layer CI1. In other words, the interior of the holes is metallized in
order to make them conductive, thereby allowing the elementary circuit
boards CEI, CE2 to be electrically connected.
25 A step 30 comprises applying a first metal pad A to the mouth of the
holes TcE~T,C Ed~ril led through the elementary circuit boards CEI, CE2. The
first metal A is a constituent of a binary alloy AxBy created by therrnodiffusion
at a formation temperature T of the alloy.
Likewise, a step 40 comprises applying a second metal pad B to the
mouth of the holes Tcl, drilled through the first intermediate layers CI1. The
second metal B is a constituent of a binary alloy AxBy created by
thermodiffusion at a formation temperature T of the alloy.
5 Advantageously, the composition of the alloy comprises silver and tin,
indium and tin, or gold and tin, thereby allowing a formation temperature T
that is clearly higher than the melting point of at least one of the constituents
of the alloy, in this case tin, to be obtained for the alloy forming the electrical
connections. The melting point of said alloy must be higher than the melting
10 point of the solder used for the electrical connections of the electronic
components mounted on the elementary circuit boards CE1 , CE2.
A step 50 comprises machining the second intermediate layers C12a,
C12b that do not cover the first and second metal. The second layers are
made of thermoplastic and have a melting point Tf above the formation
1s temperature T of the alloy. The second intermediate layers C12a, C12b are
machined in order to guarantee sufficient clearance of the metal pads A and
B to be joined by soldering. The thickness of the second intermediate layers
C12a, C12b is slightly smaller, advantageously by 20 Dm, than the sum of the
thicknesses of the metallization layers CMCEI of one of the elementary circuit
i 20 boards CEI, of one of the metallization layers CMcrza of a first intermediate ~ layer CIA and of the metal pads A and B.
A step 60 comprises stacking the elementary circuit boards CEI, CE2,
the first intermediate layers CI1 and the second intermediate layers C12a,
C12b that make it possible to limit indentation of the compressible material
25 CI1 due to height differences of the metallization layers.
A step 70 comprises applying pressure P, conventionally 20 bars, at a
i formation temperature T of the alloy, typically 235°C for a tinlsilver or golditin
1
:\ alloy. The temperature T applied allows the metal pads to be soldered by
'1 thermodiffusion. The constituent metals A and B of the pads diffuse to form
30 the alloy AxBy. The pressure exerted compresses the first intermediate
layers CI1 until they butt against the material of the second intermediate
layers C12a, C12b, which is still stiff at this temperature. The use of a
thickness of the second intermediate layers C12a, C12b smaller by 20 pm
than the sum of the thicknesses of the metallization layers of one of the
elementary circuit boards, of one of the two metallization layers of a first
5 intermediate layer and of the metal pads A and B, makes it possible to
emboss the first intermediate layer CII, by about 20 pm per face, thereby
making it possible to compensate for the thickness of the metallization layer
under a metal pad.
A step 80 comprises heating the material of the second intermediate
10 layers C12a, C12b to a melting point Tf, typically 290°C for liquid-crystal
polymers (LCP), while maintaining the pressure, typically 20 bars. At this
temperature, the material of the second intermediate layers C12a, C12b melts
and flows so as to fill available spaces and to adhesively bond the printed
circuit boards CE1 and CE2 and the intermediate layer CII.
15 Figures 2a, 2b and 2c illustrate the following steps of the process for
producing a printed circuit board, according to the invention:
Figure 2a shows a stack comprising two elementary clrcuit boards
CE1 and CE2, for example made of "RO 4003" (registered trademark), a f~rst
intermediate layer CII, for example made of "RT Duroid 6002" (registered
20 trademark), which is placed between the two elementary circuit boards CE1
and CE2 to be connected, and two second intermediate layers C12a and
C12b, for example made of LCP and of melting point Tf.
The two elementary circuit boards CE1 and CE2 are covered on at
least one of their faces with a metallization layer CMCEI and CMCE~,
25 advantageously a copper layer. Said circuit boards CE1 and CE2 are
perforated with facing holes T C ~ain d TCE2a, llowing said circuit boards to be
connected together. The walls of said holes T C ~aln d TCEa~re lined with a
metal layer (not shown in the figure).
The first intermediate layer CI1 is covered with a metallization layer
30 CMcll, and CM~llb on its two faces, advantageously a layer containing
copper. The first intermediate layer CI1 is drilled with a hole Tell facing the
holes TCEl and TC~d2r illed through the elementary circuit boards CE1 and
CE2. In the same way as for said holes T C ~aln d TcE2,t he walls of the hole
Tell are lined with a metallization layer (not shown in the figures).
5 The mouths of the holes TCEI and TCE2w, hich holes TCEa~n d TC~a2r e
located facing and pass through the elementary circuit boards CE1 and CE2,
are covered with a pad made of a first metal A, and the mouths of the hole
Tell are covered with a pad made of a second metal B.
The metals A and B are the constituents of an alloy AxBy formed by
10 thermodiffusion at the temperature T. Advantageously, the composition of the
alloy comprises tin and silver, tin and indium, or gold and tin.
The second intermediate layers C12a and C12b are placed so as to
compensate for height differences of the metallization layers and to limit the
deformation of the compressible material M2 of the layer CI1 between the
15 metal pads and the rest of the surface of the elementary circuit board or of
the first intermediate layer, in order to guarantee an intimate connection of
the assembly. The thickness of the second intermediate layers C12a is, for
example, smaller, preferably by 20 pm, than the sum of the thicknesses of
one of the two metallization layers of the first intermediate layer CMclla, of
20 the metallization layer of the elementary circuit board CMCEI and of the metal
pads A and B.
Figure 2b shows the stack in figure 2a in a press at constant
temperature. The pressure, typically 20 bars, is applied at the formation
temperature T of the alloy, for example 235°C for a tinlsilver or goldltin alloy.
25 The metals A and B diffuse to form the alloy AxBy, thus creating an electrical
connection between the metallized holes TCEI, TCEa~nd TCII.
The pressure exerted compresses the first intermediate layer CI1 until
it butts against the material of the second intermediate layers C12a and C12b,
which is still stiff at the formation temperature T of the alloy. On account of
30 the thickness chosen for the second intermediate layers, the embossing of
the first intermediate layer has the advantage of compensating for the height
difference due to the metallization layer CMCE~of the elementary circuit
board CE1 under the metal pad A
Figure 2c shows the stack shown in figure 2b after it has been heated
5 to the melting point Tf of the material of the second intermediate layers C12a
and C12b. At the melting point of the second intermediate layers C12a and
C12b, the material forming these layers melts and flows to fill available
spaces, in order to adhesively bond the circuit boards CE1 and CE2 of the
intermediate layer CI1 and to compensate for height differences.
10 The production of a printed circuit board, according to the invention,
allows height differences inside printed circuit boards to be compensated for,
and thus presses that are standard in the printed circuit board industry to be
used for their manufacture.
9
Claims
1. A process for producing a printed circuit board comprising at least two
elementary circuit boards (CEI, CE2) drilled with metallized holes
(TC~jt)h e mouth of which is covered with a first metal, and at least
one first intermediate layer (CIA), made of a compressible material,
drilled with holes (Tell) facing the elementary circuit boards (CEI,
CE2) and the mouth of which is covered with a second metal, which
layer is placed between the two elementary circuit boards (CEI, CE2)
and soldered to each of the circuits (CEI, CE2) by thermodiffusion of
the two metals forming an alloy at a formation temperature (T) of the
alloy, characterized in that at least two second intermediate layers
(C12a, C12b), the second intermediate layers (C12a, C12b) not covering
the first and second metal, being thermoplastics and having a melting
point (Tf) above the formation temperature (T) of the alloy, are placed
between the first intermediate layer (CII) and said elementary circuit
boards (CEI , CE2).
2. The process as claimed in claim 1, comprising the following steps:
- perforating the elementary circuit boards and the first
intermediate layer (CII) in order to create facing holes in
order to electrically connect the elementary circuit boards
(CEI, CE2);
- coating the holes formed in the elementary circuit boards
(CEI, CE2) and the first intermediate layer (CII) with a
metal surface;
- covering the orifice of the holes formed in the elementary
circuit boards (CEI, CE2) with a pad made of one of the
metals of a binary alloy;
- covering the orifice of the holes formed in the first
intermediate layer (Cll) with a pad made of the second
metal of the binary alloy;
- machining second intermediate layers (C12a, C12b) in order
to guarantee that the metal pads are not covered by said
second intermediate layers (C12a, C12b); and
- stacking the elementary circuit boards (CEI, CE2) and
intermediate layers (CII), (C12a, C12b).
3. The process as claimed in claim 2, comprising a step of applying
pressure (P) to the stack at a temperature (T) corresponding to the
formation temperature of the alloy, until the material forming the two
15 intermediate layers (C12a, C12b), which material is still stiff at the
temperature (T), is butted against.
4. The process as claimed in claim 3, comprising a step of heating the
stack to a melting point (T9 of the second intermediate layers (C12a,
C12b).
20 5. A printed circuit board comprising at least two elementary circuit
boards (CEI, CE2) drilled with metallized holes (TcE~t)h e mouth of
which is covered with a first metal, and at least one first intermediate
layer (Cll), made of a compressible material, drilled with holes (Tc17)
facing the elementary circuit boards (CEI, CE2) and the mouth of
25 which is covered with a second metal, which layer is placed between
the two elementary circuit boards (CEI, CE2) and soldered to each of
the circuits (CEI, CE2) by thermodiffusion of the two metals forming
an alloy at a formation temperature (T) of the alloy, characterized in
that at least two second intermediate layers (C12a, C12b), the second
intermediate layers (C12a, C12b) being thermoplastics and having a
melting point (Tf) above the formation temperature (T) of the alloy, are
placed between the first intermediate layer (CIA) and said elementary
circuit boards (CEI , CE2).