Field of the Invention
The present invention relates to a phase generator for introducing phase shift in a signal.
Background of the Invention
Fundamentally in electronic design, synchronous operation is essential for ensuring that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. Differences in clock signal arrival across the chip, which is called clock-skew, must be avoided. In order to ensure proper operation, it is often important to reduce clock skew for the internal clock of the integrated circuit. Conventionally, more hardware is put into a single chip due to which the complexity on the chip is increasing. It is a fundamental design principle that timing must satisfy register setup hold time requirement. So the clock-skew can potentially cause timing violations or even functional failure of a chip.
Clock skew being a major problem PLL (Phase Locked Loop) is becoming an integral part of the System on Chips (SOCs). In FPGA or SOC chips, PLLs are generally employed to provide clock synchronization or to eliminate the clock skew. The other features which PLL supports are the frequency multiplication, programmable duty cycle or programmable phase shift. Programmable phase shift circuit provides an output clock, which has a phase difference with respect to the input clock.
US patent 6667641 Bl provides a programmable phase shift feature for phase locked loop circuit. The phase shift may be adjusted with equal steps. Each step may be fixed percentage of the clock period.
Figure 1 shows a conventional phase generator for a phase locked loop. The outputs of the VCO stages are mixed together with a multiplexer. The multiplexer is configurable, which is controlled by configuration bits. The output of multiplexer is fed back to the phase detector through a frequency divider. The output clock of the PLL is connected to stage A of the VCO. If the feedback is not mixed from stage A, the output clock will have
a phase shift compared with the input clock. The amount of the phase shift is determined by number of stages between A and feedback.
Referring to the figure 2, it describes an 8-phase Voltage controlled oscillator. It consists of four differential delay cells '31'. 'Ctrl' is the control voltage to each differential delay cell. The outputs of each stage are applied to the inputs of the next stage, but the output 'out' of the forth delay cell is applied to 'in2' of the first input and output 'outbar' of the last delay cell is applied to the input 'inl' of the first delay cell. The eight outputs OT1, OT2, ,OT8 are the eight phases each 45-degree apart.
By programming MUXl, a user can adjust the phase difference between the output clock and input clock. This phase difference will be a fixed percentage of the output clock period. It is therefore required that additional phase shift is induced in the output of the PLL besides said fixed percentage of output clock period.
Brief description of the drawings
Figure 1 illustrates a conventional phase shift generator.
Figure 2 illustrates the internal structure of the conventional multiphase voltage controlled oscillator.
Figure 3 illustrates the input output waveforms of the conventional multiphase voltage controlled oscillator.
Figure 4 illustrates a phase generator in accordance with the instant invention.
Figure 5 illustrates the input and output waveforms of the phase generator in accordance with the instant invention.
Figure 6 illustrates the phase locked loop where the phase shift is introduced by said phase generator in accordance with the instant invention.
Object and Summary of the Invention
It is an object of the present invention to provide a phase shift generator.
It is another object of the present invention to induce phase shift in the input signal. It is further an object of the present invention to induce additional phase shift in a phase shifted signal.
To achieve said objectives the present invention provides a phase generator for introducing phase shift in a signal comprising:
-a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; said configuration bits corresponding to the phase shift required;
- a logic signal generation device connected at its control input to the output of said phase- shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and
- a feedback element connected between the output of said logic signal generation device and control input of said phase-shift enable and disable signal generator for providing controlled clock signal to said phase-shift enable and disable signal generator.
Detailed Description
Figure 4 describes the phase generator in accordance with the present invention. It contains a programmable down counter '51'. The configuration bits to the counter are shown by 'C. The value of configuration bits depends on the number of VCO cycle phase shift required. It is the binary equivalent of the number of VCO cycles (Phase shift required).
The outputs of the down counter '501a' to '501n' are connected to a NAND gate '54'. The down counter is a simple synchronous down counter. The bits are directly loaded into the Flop Flops of the down counter, and the counter starts counting onwards. The outputs '501a' to '501n' are the 'Qbar' of each FF in the counter. The clock is connected to one terminal of AND gate ('52'), the other terminal of the NAD gate is connected to the output of D Flip Flop '56' through inverter '53'. The output of '52' ('502') is connected to clock of the counter '51' and the input of NOR gate '55'. The output of the NOR gate '55' ('504') is connected to clock of the DFF '56'.
The working of this block is; while the whole block is reset, the down counter is loaded with the configuration bits 'C\ Initially the output '505' of the DFF '56' is 0. So the clock directly passes from the AND gate '52' to Down counter '51'. At the first rising edge of the clock, the down counter starts counting down from the binary value 'C. The outputs 501a to 501n are initially invert of loaded value 'C (inverted outputs). So as the counter reaches to zero from the initial count value, all outputs 501a to 501n reaches 1, the output '503' of the NAND gate '54' is 0, at the falling edge of the clock or '502', output '504' of the OR gate '5'is 1, and the output '505' of the DFF '56' is 1. This disables the clock from the NAND gate '52' from reaching the counter '51'. This 505 goes to the RSTB of the output divider '27' in fig. 2, which enables the divider and at next rising edge it starts dividing.
From figure 5, let us assume that the input clock frequency to the PLL is lOOMHz, and the VCO is operating at 600MHz after locking. Let the output divider is set to divide by 6. So the output frequency is also lOOMHz. Let us suppose that we want to introduce a phase shift of 45-degree with respect to the input clock. To do this the load bits to the phase generator are set as binary equivalent of decimal value 1 and then VCO output OT4 is selected. As a result, the phase generator counter will enable the output divider after one cycle of the VCO clock and half VCO cycle phase will come from the VCO TAP.
Thus, it is seen that if the phase shift is to be achieved for more than one cycle, the configuration bits of phase generators are programmed for the desired number. Once the same number of cycles lapse, the required phase shift output is obtained. In case the phase shift is required for less than a cycle, the required fraction is obtained from the multiplexer giving the desired fractional phase shift. Also in case fractional as well as N VCO cycles phase shift is required, the two arrangements can be used simultaneously.
Figure 6 describes frequency & phase synthesis. The input clock is connected to one terminal of PFD '21'. Feedback clock '202' is connected to the other input of PFD. Block '22' contains charge pump and low pass filter. The error signals in terms of outputs of PFD (UP & DN) '201' are connected to the input of charge pump. The output of charge pump is connected to Low Pass filter. The low pass filter output '203' is the control voltage of VCO '24'. VCO generates clock, whose frequency is dependent on the control voltage. As the control voltage changes, the frequency of the VCO also changes. This circuit employs a multi-phase VCO '24', which is described in figure 3. The VCO generates multiple phases (A, B,..H) whose frequency is same but they are phase shifted with respect to each other.
The VCO output 'A' is connected to the input of programmable divider '23'. The output of the divider is connected to the input of PFD '21'. The divider '23' in the feedback is used get a frequency multiplication.
If 'A' were taken as the reference phase, then the other outputs would have phase difference with respect to 'A'. Let us take an example of 8-phase VCO. The outputs 'A' to 'FT are 45-degree phase shifted with respect to the consecutive one. So a phase shift of 0-degree to 360-degree can be obtained with respect to the input clock if the input clock is within the range of VCO frequency range, by selecting a TAP (A to G) from Multiplexer'25'.
If a divider at the output of VCO is used, then one cannot get up to 360-degree phase shift with respect to the output clock frequency or the input clock if the frequency of the input clock is lower than the range supported by VCO.
To eliminate this limitation, phase generator '26' is used at the output of the multiplexer '25'. This block is programmable. This introduces the phase shift in terms of VCO cycles. So the block can be programmed to provide one VCO cycle phase shift or any number of VCO cycles as per programming bits 'C3'
Output of phase generator '205' is connected to the reset terminal of output divider '27' while the output of the multiplexer '25' ('204') is directly connected to the clock input of the divider'27'.
The basic principle is that the phase generator '26' keeps the output divider '27' reset for as many number of VCO cycles as the phase shift is required.
'CI, C2, C3 & C4' are the programming bits required to program the feedback divider '23', VCO Multiplexer '25', Phase generator '26' & output divider '27' respectively.

We Claim:
1. A Phase Generator for introducing phase shift in a signal comprising:
a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; said configuration bits corresponding to the phase shift required;
a logic signal generation device connected at its control input to the output of said phase- shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of said logic signal generation device and control input of said phase-shift enable and disable signal generator for providing controlled clock signal to said phase-shift enable and disable signal generator.
2. A Phase Generator for introducing phase shift in a signal as claimed in claim 1,
wherein said phase-shift enable and disable signal generator comprising:
a counter connected to configuration bits at its first input, to the output of
said feedback element at its second input and receiving said reset signal at
its reset input for generating a count sequence, said configuration bits
correspond to the phase shift required in said signal;
a first logic element connected to said count sequence at its input for
generating a first enable or disable signal; and
a second logic element connected to said first enable or disable signal at
its first input and connected to the output of said feedback element at its
second input for generating a second enable or disable signal.
3. A Phase Generator as claimed in claim 1, wherein said logic signal generation
device is a data flip flop connected to a higher voltage supply at its data input.
4. A Phase Generator as claimed in claim 1, wherein said feedback element
comprising:
a logic inverter; and
a two input logic and gate connected to the output of said logic inverter at its first input and connected to a clock signal at its second input for generating said controlled clock signal.
5. A Phase Generator as claimed in claim 2, wherein said counter is a down counter.
6. A Phase Generator as claimed in claim 1, wherein phase locked loop where the phase shift is introduced by said phase generator comprising:
a phase difference detector connected to an input signal at its first input and a reference signal at its second input for detecting the phase difference between said input signal frequency and reference signal frequency; a regulator coupled to the output of said phase difference detector for regulating the detected phase difference;
a filter connected at the output of said regulator to minimize spurious signals in said regulated phase difference;
an oscillator connected to the output of said filter for generating at least two non-overlapping phase signals, said non-overlapping phase signals being phase shifted with respect to said input signal; a selector connected to the output of said oscillator for generating one non-overlapping phase signal;
said phase generator is coupled to the output of said selector for producing said configurable phase generating signal, and
a divider coupled to the output of said phase generator and to the output of said selector at its first and second input terminals, and receiving configuration bits at its control input for incorporating additional phase shift of at least one cycle in non-overlapping phase signal.
7. A Phase generator as claimed in claim 6, wherein said regulator is a charge pump.
8. A Phase generator as claimed in claim 6, wherein said filter is a low pass filter.
9. A Phase generator as claimed in claim 6, wherein said oscillator is a multiphase voltage controlled oscillator.
10. A Phase generator as claimed in claim 6, wherein said selector is an eight input multiplexer.
11. A method of introducing phase shift in a signal comprising steps of:
applying a reset signal to the phase enable and disable signal generator for enabling configuration corresponding to the phase shift required; controlling a logic signal generation device for producing a phase generating signal; and
feeding back the output of said logic signal generation device through a feedback element to provide a controlled clock signal to said phase enable and disable signal generator to thereby enable controlled phase shift incorporation in said signal.
12. A method as claimed in claim 11, wherein said applying a reset signal and
enabling configuration is:
loading a down counter with the configuration bits corresponding to the
phase shift required;
generating a down count sequence from the value of configuration bits to
zero value;
combining said down count sequence for producing a first enable or disable
signal; and
combining said first enable or disable signal and the output of said feedback
element for generating a second phase enable or disable signal.
13. A method as claimed in claim 11, wherein said controlling logic signal generation
device is:
applying a reset signal to said logic signal generation device;
applying control signal at control input of said logic signal generation
device; and
connecting data input of said logic generation device to a higher voltage
supply.
14. A method as claimed in claim 11, wherein said feeding back the output is:
logically inverting the output of said logic signal generation device; combining said inverted output with an external clock signal; and connecting the combined output to said phase signal enable and disable signal generation device.
15. A Phase Generator for introducing phase shift in a signal substantially as herein described with reference to the accompanying drawings
16. A method of introducing phase shift in a signal substantially as herein described with reference to the accompanying drawings