Abstract: Disclosed is a process of serial communication over GPIO port pin. The process provides multiple port pins which can be used for communication without absorbing bandwidth of a microcontroller. Further, the process provides communication in the electrical devices which is done effectively by configuring one timer for set value and detecting the transition in this routine.
FORM 2
THE PATENT ACT 1970
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10 and rule 13)
1. TITLE OF THE INVENTION:
"Process Of Serial Communication In The Electrical Devices"
2. APPLICANT:
(a) NAME: Larsen & Toubro Limited
(b) NATIONALITY: Indian Company registered under the
provisions of the Companies Act-1956.
(c) ADDRESS: LARSEN & TOUBRO LIMITED,
L&T House, Ballard Estate, P. O. Box: 278, Mumbai 400 001, India
3. PREAMBLE TO THE DESCRIPTION:
COMPLETE
The following specification particularly describes the invention and the manner in which it is to be performed.
Process Of Serial Communication In The Electrical Devices
Field of the invention
The present invention relates to electrical devices, such as electronic trip unit for circuit breaker and electronic energy meters, and more particularly, to use of general purpose input/output (GPIO) port pin for serial communication in the electrical devices.
Background of the invention
Generally micro controllers have Universal Asynchronous Receiver/Transmitter (UART) engine or Interrupt sensing (IS) engine assigned to general purpose Input/output GPIO Pins. During initialization of the microcontroller, the GPIO is configured to work as UART or INT or GPIO pin based on the system requirement.
Serial communication is required for dialog between two devices with reduced pin counts. These devices could be set in peer-to-peer network for data exchange. Specifically, half duplex mode is preferred for limited data exchange with acknowledgement.
Further, the GPIO is generally used only to sense one data bit, either high or low, and is not used for communicating streams of data. And hence, there is dependency on microcontroller architecture (UART and Interrupt Pins) to prepare the process for serial communication.
Accordingly, there exists a need to provide a system and process of communication for electrical devices which overcomes drawbacks of the prior art.
Objects of the invention
An object of the present invention is to provide multiple port pins which can be used for communication without absorbing bandwidth of a microcontroller.
Another object of the present invention to provide communication in the electrical devices which is done effectively by configuring one timer for set value and detecting the transition in this routine.
Summary of the invention
Accordingly, the present invention provides a process for serial communication over general purpose port pin (GPIO) between a master device capable of initiating the communication and other device is a slave device capable of acknowledging received data. The process includes configuring GPIO pin of the master device as output and configuring GPIO pin of the slave device as input, determining logic detection level of data based on its frequency in analogues to frequency shift keying(FSK), keeping the slave device in polling mode to detect any change of level at the configured input pin, wherein when the master device sends data to the slave device, the master device starts toggling the GPIO pin at predetermined frequency and for predetermined time based on data bit to be sent, detecting transition at the input GPIO pin by the slave device, decoding the processed data by the slave device for sending acknowledgement, reconfiguring the GPIO pin thereof as input by the master device and the GPIO pin thereof as output by the slave device after sending the data, sending acknowledgement by the slave device by providing transition of high to low at the GPIO pin detected by the master device as acknowledgment transition, wherein if the acknowledgement is not received by the master device, the master device resends the earlier transmitted bit and waits for acceptance and reconfiguring of the master device GPIO pin as output and the slave device GPIO pin as input enabling the master device send remaining data bits.
Brief description of the drawings
Figure 1 shows a representation of data bits in terms of frequency;
Figure 2 shows various states of master and slave for configuration of general purpose port pin (GPIO), in accordance with the present invention;
Figure 3 shows a flowchart for a master module of general purpose port pin (GPIO) in accordance with the present invention;
Figure 4 shows a flowchart for a slave module of general purpose port pin (GPIO) in accordance with the present invention; and
Figure 5 shows a frequency shift keying logic.
Detailed description of the invention
The foregoing objects of the present invention are accomplished and the problems and shortcomings associated with the prior art, techniques and approaches are overcome by the present invention as described below in the preferred embodiments.
The present invention provides a process of serial communication over GPIO port pin. The process provides multiple port pins which can be used for communication without absorbing bandwidth of a microcontroller. Further, the process provides communication in the electrical devices which is done effectively by configuring one timer for set value and detecting the transition in this routine.
Referring now to figure 1 to 5, there is shown a process (100) for serial communication over GPIO port pin, in accordance with the present invention. The process (100) provides for exchange of data between two devices where one device acts as master device capable of initiating the communication and other device acts as slave the slave device which acknowledges the received data. The process is over single wire (GPIO Pin) for reception and transmission of data.
The process (100) includes configuring a GPIO pin of the master device as output and a GPIO pin of the slave device is configured as input. Specifically, figure 2 shows various states of the master device and the slave device for configuration of the GPIO pins.
Further, the process includes determining logic detection level of data based on its frequency in analogues to frequency shift keying (FSK) as shown in figure 5. The reason for going dual frequency detection is that since the GPIO pin is not edge triggered, the GPIO pin level needs to be frequently checked in order to determine the data bit as zero or one. Figure 1 shows a representation of data bits in terms of frequency which represents one of the ways to convert data bit in corresponding frequency. This is predetermined frequency for data bit representation between the master device and the slave device.
Furthermore, the process includes keeping the slave device in polling mode to detect any change of level at this configured input pin. When the master device needs to send data, the master device starts toggling the GPIO pin at pre determined frequency and for .pre determined time based on data bit to be sent. The slave device then detects this transition at input GPIO pin and decodes the data which is processed for sending acknowledgement.
Thereafter, the process includes reconfiguring the GPIO pin thereof as input by the master device and the GPIO pin thereof as output by the slave device after sending the data. The slave device then sends acknowledgement by providing transition of high to low at GPIO pin which is detected by the master device as acknowledgment transition. If this acknowledgement is not received, the master device resends the earlier transmitted bit and waits for acceptance. This is attempted several fime before time out and subsequent warning to the user.
The process (100) is repeated again with configuration of the master GPIO pin as output and the slave GPIO pin as input so that master device can send remaining data bits. This process is repeated till all the data is sent successfully. Specifically, figure 3 shows an algorithm of the master device module and figure 4 shows an algorithm for the slave device module.
The decoding logic of received data bit by the slave device is initiated once the data is received and no further data is available by calling the time out routine.
The purpose of present invention is to make two devices for example the master device and the slave device talk over the GPIO pin which was not possible otherwise. The GPIO is generally used only to sense one data bit, either high or low, and is not used for communicating streams of data.
Advantages of the invention
1. The process (100) provides conversion of GPIO Port pins into UART.
2. The process (100) provides development of UART engine with acknowledgement
3. The process (100) Single wire communication which is configured in Half duplex mode
4. The process (100) provides transmission of streams of data over port pin which was otherwise capable of sending only one bit.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present invention and its practical application, to thereby enable others skilled in the art to best utilize the present invention and various embodiments with various modifications as are suited to the particular use contemplated. It is understood that various omission and substitutions of equivalents are contemplated as circumstance may suggest or render expedient, but such are intended to cover the application or implementation without departing from the spirit or scope of the present invention.
We claim
1. A process for serial communication over general purpose port pin
(GPIO) between two electrical devices, wherein one device is a master device capable
of initiating the communication and other device is a slave device capable of
acknowledging received data, the process comprising:
configuring GPIO pin of the master device as output;
configuring GPIO pin of the slave device as input;
determining logic detection level of data based on its frequency in analogues to frequency shift keying(FSK);
keeping the slave device in polling mode to detect any change of level at the configured input pin, wherein when the master device sends data to the slave device, the master device starts toggling the GPIO pin at predetermined frequency and for predetermined time based on data bit to be sent;
detecting transition at the input GPIO pin by the slave device;
decoding the processed data by the slave device for sending acknowledgement;
reconfiguring the GPIO pin thereof as input by the master device and the GPIO pin thereof as output by the slave device after sending the data;
sending acknowledgement by the slave device by providing transition of high to low at the GPIO pin detected by the master device as acknowledgment transition, wherein if the acknowledgement is not received by the master device, the master device resends the earlier transmitted bit and waits for acceptance; and
reconfiguring of the master device GPIO pin as output and the slave device GPIO pin as input enabling the master device send remaining data bits.
2. The process as claimed in claim 1, wherein the decoding logic of
received data bit by the slave device is initiated once the data is received and no further
data is available by calling the time out routine.
| # | Name | Date |
|---|---|---|
| 1 | 784-MUM-2013-FER.pdf | 2019-09-18 |
| 1 | Form-18(Online).pdf | 2018-08-11 |
| 2 | 784-MUM-2013-ABSTRACT.pdf | 2018-08-11 |
| 2 | ABSTRACT1.jpg | 2018-08-11 |
| 3 | 784-MUM-2013-POWER OF ATTORNEY(7-3-2014).pdf | 2018-08-11 |
| 3 | 784-MUM-2013-CLAIMS.pdf | 2018-08-11 |
| 4 | 784-MUM-2013-GENERAL POWER OF ATTORNEY(20-6-2013).pdf | 2018-08-11 |
| 4 | 784-MUM-2013-CORRESPONDENCE(20-6-2013).pdf | 2018-08-11 |
| 5 | 784-MUM-2013-FORM 5.pdf | 2018-08-11 |
| 5 | 784-MUM-2013-CORRESPONDENCE.pdf | 2018-08-11 |
| 6 | 784-MUM-2013-FORM 3.pdf | 2018-08-11 |
| 6 | 784-MUM-2013-DESCRIPTION(COMPLETE).pdf | 2018-08-11 |
| 7 | 784-MUM-2013-FORM 2.pdf | 2018-08-11 |
| 7 | 784-MUM-2013-DRAWING.pdf | 2018-08-11 |
| 8 | 784-MUM-2013-FORM 1(20-6-2013).pdf | 2018-08-11 |
| 8 | 784-MUM-2013-FORM 2(TITLE PAGE).pdf | 2018-08-11 |
| 9 | 784-MUM-2013-FORM 1.pdf | 2018-08-11 |
| 10 | 784-MUM-2013-FORM 2(TITLE PAGE).pdf | 2018-08-11 |
| 10 | 784-MUM-2013-FORM 1(20-6-2013).pdf | 2018-08-11 |
| 11 | 784-MUM-2013-FORM 2.pdf | 2018-08-11 |
| 11 | 784-MUM-2013-DRAWING.pdf | 2018-08-11 |
| 12 | 784-MUM-2013-FORM 3.pdf | 2018-08-11 |
| 12 | 784-MUM-2013-DESCRIPTION(COMPLETE).pdf | 2018-08-11 |
| 13 | 784-MUM-2013-FORM 5.pdf | 2018-08-11 |
| 13 | 784-MUM-2013-CORRESPONDENCE.pdf | 2018-08-11 |
| 14 | 784-MUM-2013-GENERAL POWER OF ATTORNEY(20-6-2013).pdf | 2018-08-11 |
| 14 | 784-MUM-2013-CORRESPONDENCE(20-6-2013).pdf | 2018-08-11 |
| 15 | 784-MUM-2013-POWER OF ATTORNEY(7-3-2014).pdf | 2018-08-11 |
| 15 | 784-MUM-2013-CLAIMS.pdf | 2018-08-11 |
| 16 | ABSTRACT1.jpg | 2018-08-11 |
| 16 | 784-MUM-2013-ABSTRACT.pdf | 2018-08-11 |
| 17 | Form-18(Online).pdf | 2018-08-11 |
| 17 | 784-MUM-2013-FER.pdf | 2019-09-18 |
| 1 | searchstrategy_invention_17-09-2019.pdf |