CLIAMS:1. A processor comprising:
a decode unit to map a packed data instruction that is to indicate at least a first narrower source packed data operand and a narrower destination operand to a masked packed data operation that is to indicate at least a first wider source packed data operand that is to be wider than and is to include the first narrower source packed data operand, and that is to indicate a wider destination operand that is to be wider than and is to include the narrower destination operand; and
an execution unit coupled with the decode unit, the execution unit to perform the masked packed data operation with a packed data operation mask, the packed data operation mask to include a mask element for each corresponding result data element of a packed data result that is to be stored by the masked packed data operation, wherein all mask elements that correspond to result data elements to be stored by the masked packed data operation that would not be stored by the packed data instruction are to be masking out, the execution unit to store the packed data result in the wider destination operand.
,TagSPECI:BACKGROUND
Technical Field
[0001] Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to accessing registers in processors.
Background Information
[0002] Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements or multiple pairs of data elements simultaneously or in parallel. The processor may have parallel execution hardware responsive to the packed data instruction to perform the multiple operations simultaneously or in parallel.