FORM 2 THE PATENT ACT, 1970 (39 of 1970) & THE PATENT RULES, 2003 (SECTION 10 & RULE 13) COMPLETE SPECIFICATION TITLE: PROGRAMMABLE CLOCK SPREADING NAME OF THE INVENTORS: VINEET SREEKUMAR RANJIT YASHWANTE NATIONALITY: INDIAN & NAME OE THE INVENTOR: JAMES G. MONTHIE NATIONALITY: USA NAME OF THE APPLICANT: LSI CORPORATION ADDRESS: 1320 RIDDER PARK DRIVE SAN JOSE, CA 95131 UNITED STATES OF AMERICA The following specification particularly describes the invention and the manner in which it is to be performed PROGRAMMABLE CLOCK SPREADING FIELD The present disclosure relates generally to integrated circuits and. more specifically but not exclusively, to power-supply noise reduction techniques. BACKGROUND In a synchronous integrated circuit, substantially simultaneous triggering of many circuit elements leads to short duration but large amplitude current demands concentrated around the active clock edges. The relatively high current peaks typically cause transient power-supply voltage droops in various parts of the circuit. These transient voltage droops (also sometimes referred to as power-supply noise) are a major concern, for example, because, for a power-supply voltage of about 1 V, a power-supply noise level on the order of about 100 mV might cause the integrated circuit to malfunction. SUMMARY Disclosed herein are various embodiments of an integrated circuit having a programmable clock spreader con figured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g.. based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit. Also disclosed herein are various embodiments of a method of clock spreading that uses the circuit's spectral impedance profile to identify a configuration of the programmable clock spreader that enables the integrated circuit to attain desired current-demand characteristics. Some embodiments are directed to a non-transilory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine performs the above-mentioned method of clock spreading. BRIEF DESCRIPTION OF THE FIGURES Other embodiments of the disclosure will become more fully apparent from the following detailed description and the accompanying drawings, in which: FIG. 1 shows a block diagram of an integrated circuit according to an embodiment of the disclosure; FlGs. 2A-2C graphically show certain characteristics of the integrated circuit shown in FIG. 1 according to an embodiment of the disclosure; FIG. 3 shows a block diagram of a programmable clock spreader that can be used in the integrated circuit of FIG.1 according to an embodiment of the disclosure: and FIG. 4 shows a flowchart of a method of programming an integrated circuit analogous to the integrated circuit shown in FIG. 1 to perform clock spreading according to an embodiment of the disclosure. DETAILED DESCRIPTION As indicated above, conventional, low-skew clock-lree designs may disadvantageously lead to relatively large current spikes in the power-supply network of an integrated circuit (chip) over relatively short time periods. Various embodiments disclosed herein are generally directed at reducing these current spikes, as well as fluctuations in instantaneous power consumption in the integrated circuit and the associated power-supply noise. Peak-current reduction is considered to be beneficial for one or more of the following exemplary reasons: (1) it reduces the IR voltage drop within the circuit die. where the ohmic resistance (R) is a major impedance component; (2) it reduces the inductive power-supply noise, -L(d//dt). at the circuit's package level, where inductance (/,) is a significant impedance component; (3) it reduces clock jitter because the clock jitter is generally directly related to the magnitude of the power-supply voltage droops; and (4) it reduces requirements to the capacitance of decoupling capacitors, which tends to reduce the cost of the integrated circuit. Embodiments of the present disclosure tend to reduce power-supply noise using clock-skew engineering. More specifically, the integrated circuit has an architecture that enables it to reduce current spikes by providing, to different clock regions within the circuit, respective differently skewed clock signals, e.g.. derived from the same (common) master clock. As used herein, the term "clock region" refers to a block of circuitry, such as a logic block, a processor core, a data path, a circuit island, a clock domain, or a sub-circuit, whose circuit elements arc triggered off the same provided clock signal. In some embodiments, different clock regions may be configured to operate in parallel with one another or in quasi-independent manner. Division of the integrated circuit into clock regions may follow the natural functional and/or logical partitions dictated by the circuit design, function, and/or structure. For example, each of the clock regions may include a different respective data-path structure from one I/O (input/output) register to another I/O register. To achieve desired circuit performance characteristics, the controllably introduced clock-skew amount for each clock region can be individually programmed, e.g.. based on the frequency dependence of the circuit's impedance and on the exhibited power-supply noise frequencies. In one embodiment, the introduced clock-skew amounts for different clock regions can be selected from a set of values consisting of different integer multiples of the common skew increment. For example, the integer multiple corresponding to a clock region can be continuously programmable, e.g.. from 0 (no skew) to N, where N is a predetermined positive integer. In various alternative embodiments, various respective hardware features (such as clock inverters, clock-delay cells, positive and negative edge registers, high-speed clock sources, programmable fuses, signal selectors, etc.), provided on-chip, can be used to enable programmability of the clock skew for various clock regions. The clock-skew amounts can be (i) static, e.g.. set once in hardware at the fabrication facility, (ii) adjusted dynamically, e.g.. in real-lime, based on the effective operating mode of the integrated circuit, or (iii) reprogrammed on demand, e.g.. when the circuit configuration is changed by the user/customer. In embodiments that require signal crossing from one clock region to another clock region, signal-transfer paths between the corresponding clock regions can be engineered to ensure that no liming (e.g., late or early mode) violations occur after the clock-skew amounts have been programmed or reprogrammed. FIG. I shows a block diagram of an integrated circuit 100 according to an embodiment of the disclosure. Circuit 100 is illustratively shown in FIG. 1 as having four clock regions, labeled 1021-1024. However, one of ordinary skill in the art will understand that, in various alternative embodiments, circuit 100 can similarly be designed to have fewer or more than four clock regions. Bach clock region 102; (i=1. 2, 3, 4) is illustratively shown in FIG. 1 as comprising clocked registers 104i, 108i, and 112i and logic blocks 106i and 110;. At least some of registers 104i. 108i, and 112i can be configured to operate as input and/or output registers that receive signals from and/or output signals to external circuits (not explicitly shown in FIG. 1). In various alternative embodiments, different clock regions 102i can be designed to (i) have other and/or additional circuit elements and/or (ii) be dissimilar to one another and include different respective sets of circuit elements. Circuit 100 further comprises a programmable clock spreader 120 configured to apply different respective clock signals, labeled CLKA, CLKB, CLKC. and CLKD. to clock regions 1021 -1024, respectively. Clock spreader 120 generates clock signals CLKA, CLKB. CLKC, and CLKD based on a master-clock signal, labeled CLK, and a relatively high-speed clock signal, labeled MS CLK. Depending on how clock spreader 120 is programmed, the clock spreader may generate clock signals CLKA, CLKB, CLKC, and CLKD so that (i)-each of these four clock signals has a different respective (e.g.. unique) programmed skew amount with respect to master-clock signal CLK or (ii) the programmed skew amounts for these four clock signals are selected from a set of clock-skew values consisting of fewer than four different values. In the latter case, at least two of clock signals CLKA, CLKB, CLKC, and CLKD will have the same programmed skew amount. FIGs. 2A-2C graphically show certain characteristics of circuit 100 (FIG. 1) according to an embodiment of the disclosure. More specifically. FIG. 2A shows a spectral impedance profile 210 that demonstrates the frequency dependence of the impedance of circuit 100. The data shown in FIGs. 2B-2C correspond to an operating mode of circuit 100 in which master-clock signal CLK has a frequency of 50 MHz. The current-demand characteristic that is graphically depicted in PIG. 213 as a curve 220 demonstrates the frequency dependence of the current demand presented by circuit 100 to the power supply when clock spreader 120 is programmed to generate clock signals CLKA, CLKB, CLKC, and CLKD so that none of them is skewed with respect to master-clock signal CLK. This configuration of circuit 100 models the operation of a conventional integrated circuit that does not have multiple clock regions analogous to clock regions 1021-1024 and, as such, lacks the capability to controllably skew the clock signals in a programmable manner. The current-demand characteristic that is graphically depicted in FIG. 2C as a curve 230 demonstrates the frequency dependence of the current demand presented by circuit 100 to the power supply when clock spreader 120 is programmed to generate clock signals CLKA, CLKB, CLKC. and CLKD so that: (i) clock signal CLKA is not skewed with respect to master-clock signal CLK; (ii) clock signal CLKB is skewed with respect to master-clock signal CLK by an amount approximately equal to one quarter of a clock cycle; (iii) clock signal CLKC is skewed with respect to master-clock signal CLK by an amount approximately equal to one half of a clock cycle: and (iv) clock signal CLKD is skewed with respect to master-clock signal CLK by an amount approximately equal to three quarters of a clock cycle. Referring to FIG. 2A, spectral impedance profile 210 has a global maximum located at approximately 50 MHz. Spectral impedance profile 210 further has several local maxima located in the frequency range between approximately 5 MHz and approximately 90 MHz. The local maxima located next to each other are separated by a corresponding local minimum of spectral impedance profile 210. At frequencies higher than approximately 90 MHz, the circuit's impedance gradually decreases, with the frequency increase, down to about 10% of the maximum value. Referring to FIG. 2B, current-demand curve 220 has its most-prominent (also sometimes referred to as the dominant) frequency band located at 50 MHz primarily because master-clock signal CLK has this frequency. The other frequency bands of current-demand curve 220 are the spectral harmonics of the master-clock frequency. with the eighth harmonic (located at approximately 400 MHz) being the second most-prominent frequency band. Note that the dominant frequency band of current-demand curve 220 lines up with a peak of spectral impedance profile 210 {FIG. 2A). This property is detrimental to the circuit's performance, e.g., because it can cause a relatively large transient power-supply voltage drop due to the fact that the voltage drop is approximately proportional to the product of the current and the impedance. Referring to FIG. 2C, current-demand curve 230 has its dominant frequency band located at 200 MHz primarily because the current demand is now staggered over four different, equally spaced phases of master-clock signal CLK. The fundamental (50 MHz) master-clock frequency band is now substantially fully suppressed, while the other frequency bands of current-demand curve 230 are similar to the corresponding frequency bands of current-demand curve 220 (FIG. 213). Note that, unlike the dominant frequency band of current-demand curve 220. which lines up with a peak in spectral impedance profile 2.10. the dominant frequency band of current-demand curve 230 corresponds to an impedance value that is only about 30% ofthe maximum impedance value in spectral impedance profile 210 (see FIG. 2A). The latter property results in an improvement in the circuit performance compared to the previous configuration, e.g., because the transient power-supply voltage drops are now significantly reduced due to both the lower instantaneous current-demand level and the lower effective circuit impedance. In an alternative embodiment, the circuit configuration to be achieved by programming clock spreader 120 can be determined by measuring or simulating the spectral impedance profile (such as spectral impedance profile 210, FIG. 2A) of integrated circuit 100 and then choosing a configuration for the programmable clock spreader that causes the dominant frequency band of the current-demand curve (such as current-demand curve 230, FIG. 2C) exhibited by the integrated circuit during operation to be at a spectral location corresponding to either (i) a null or a minimum of the spectral impedance profile or (ii) an impedance value in the spectral impedance profile that docs not exceed about 40% of the maximum impedance value in the spectral impedance profile. In some embodiments, it may be possible to choose a configuration that results in a spectral location of the dominant frequency band that is characterized by both (i) and (ii). FIG. 3 shows a block diagram of a programmable clock spreader 300 thai can be used as clock spreader 120 (FIG. 1) according to an embodiment of the disclosure. Clock spreader 300 is illustratively shown in FIG. 3 as being configured to: (i) receive master-clock signal CLK and high-speed clock signal HS_CLK and (ii) generate clock signals CLKA. CLKB. CLKC, and CLKD. In the embodiment of FIG. 3: high-speed clock signal HSCLK has a frequency that is four times higher than the frequency of master-clock signal CLK. For example, if master clock signal CLK has a frequency of 50 MHz, then high-speed clock signal MS CLK. has a frequency of 200 MHz. Clock spreader 300 includes a shift register having four D flip-flops 3IOo3103 serially connected to one another as indicated in FIG. 3. Each of D flip-flops 3100-3103 is clocked by clock signal FIS_CLK and. as such, operates to update its output signal, based on its input signal, four times per clock cycle of master-clock signal CLK. Master-clock signal CLK serves as the input signal for D flip-flop 3100. The output signal of D flip-flop 310o- labeled CLK PFIASEO. serves as the input signal for D Rip-Hop 3101. The output signal of D flip-Hop 310,, labeled CLK PHASEL serves as the input signal for D flip-Hop 3102. The output signal of D flip-flop 3102. labeled CLK PHASE2. serves as the input signal for D flip-flop 3103. The output signal of D Hip-Hop 3103 is labeled CLK PFIASE3. Each of signals CLK PHASE0; CLK_PHASEL CLK PHASE2, and CLK PHASE3 has the same frequency as master-clock signal CLK. Flowcver. the phases of signals CLK_PHASE0, CLK_PHASEL CLK PHASE2, and CLK PHASE3 differ from one another. More specifically, signal CLK_PHASEI is skewed with respect to signal CLK_PHASE0 by an amount approximately equal to one quarter of a clock cycle. Signal CLK_PHASE2 is skewed with respect to signal CLK PHASE0 by an amount approximately equal to one half of a clock cycle. Signal CLK_ PHASE3 is skewed with respect to signal CLK PHASE0 by an amount approximately equal to three quarters of a clock cycle. Clock spreader 300 further comprises four signal selectors 320A-320D. Each signal selector 320 is configured to (i) receive, as its inputs, signals CLK_PHASE0. CLK PHASE 1, CLK PHASE2, and CLK_PHASE3 and (ii) select and transfer one of the received signals to the selector's output. A configuration register 330 operates to set the configuration of each of signal selectors 320A-320D. thereby controlling which of signals CLK PHASEO, CLK_ PHASE1, CLK PHASE2, and CLK_PHASE3 is selected and transferred to the output in each of the signal selectors. The signal selected and transferred by signal selector 320A is output by clock spreader 300 as clock signal CLKA. The signal selected and transferred by signal selector 320B is output by clock spreader 300 as clock signal CLKB. The signal selected and transferred by signal selector 320C is output by clock spreader 300 as clock signal CLKC. The signal selected and transferred by signal selector 320D is output by clock spreader 300 as clock signal CLKD. In one embodiment, configuration register 330 is an 8-bit register configured to be programmed, using a write signal 332. to store a desired configuration value that determines the configurations of signal selectors 320A-320O. for example, the first two bits of the configuration value stored in configuration register 330 determine which of signals CLK PHASEO. CLK_PHASEL CLK PHASE2: and CLK_PHASE3 is transferred by signal selector 320A to serve as clock signal CLKA. The second two bits of the configuration value stored in configuration register 330 similarly determine which of signals CLK_PHASE0, CLK_PHASEL CLK_PHASE2, and CLK_PHASE3 is transferred by signal selector 3201$ to serve as clock signal CLKB, etc. Depending on the particular embodiment, configuration register 330 can be designed to be programmable using software, the circuit's firmware, or one or more on-chip fuses. In some embodiments, configuration register 330 can be designed to be one-time programmable, with the programming to be performed, e.g., at the fabrication facility, in some embodiments, configuration register 330 can be designed to be programmable multiple times so that it can be reprogrammed. as desired or necessary, by the customer or user in the field after the chip has been shipped out from the fabrication facility. In an alternative embodiment, clock spreader 300 can be modified to have a shift register having an arbitrary (but practical from the engineering viewpoint) number K of serially connected Hip-flops, where K is a positive integer greater than one. lf fo is the frequency of master-clock signal CLK, then high-speed clock signal MS CLK used in this alternative embodiment is generated to have a frequency of Kfo. As a resuh, the K output signals generated by the K serially connected flip-flops represent, in this embodiment; K different equally spaced phases of master-clock signal CLK. Clock spreader 300 can further be modified to have an arbitrary number L (1 < L< K) of signal selectors, each configured to receive some (e.g.. a subset) or all of the K different phases of master-clock signed CLK generated by the k serially connected flip-flops. Note that the embodiment of clock spreader 300 shown in FIG. 3 corresponds to L = K=4. However, in an alternative embodiment, K can be greater than four. If L< K, then fewer than all k available phases of master-clock signal CLK will be used in the output signals (e.g.. CLKA, CLKB. etc) generated by the corresponding embodiment of clock spreader 300. One of ordinary skill in the art will appreciate that, by changing the set of phases of master-clock signal CLK selected to serve as the output signals of clock spreader 300, one can controllably change the spectral content of the circuit's current-demand curve (such as current-demand curve 230 shown in FIG. 2C) in general and the spectral location of the curve's most-prominent frequency bands in particular. I he latter feature of clock spreader 300 advantageously enables customization of the circuit's current-demand curve for any given circuit-impedance profile in a manner that causes the power-supply noise to be lower than a predetermined and/or acceptable threshold level. In yet other alternative embodiments, various alternative circuit means (other than or in addition to the serially connected flip-Hops and high-speed clock) can be used in clock spreader 300 to generate different desired phases of master-clock signal CLK. for example, for clock signals having a 50% duty cycle, a signal inverter can be used to generate an inverted clock signal, which is equivalent to the clock signal that is phase shifted by one half of the clock cycle. As another example, a delay cell can be used to generate a delayed signal, which is equivalent to the clock signal that is phase shifted by the fractional portion of the clock cycle corresponding to the delay time imparted on the clock signal by the delay cell. The use of other alternative circuit means is similarly contemplated. The generated phases of master-clock signal CLK do not have to be equidistant. FIG. 4 shows a flowchart of a method 400 of programming an integrated circuit analogous to circuit 100 (FIG. 1) to perform clock spreading according to an embodiment of the disclosure. The provided description of method 400 assumes that the integrated circuit that is being programmed employs a programmable clock spreader that is similar to clock spreader 300 (FIG. 3) but has L signal selectors and is configured to generate k different phases of the master-clock signal, where L and K are positive integers greater than one. and 1