1. A programmable controller, which performs read and write of memory in a word unit composed of a plurality of one-bit data subject to a bit operation processing, comprising 5 a bit operation processor which performs in parallel a bit operation processing instruction sequence contained in a program by a pipeline processing mechanism, wherein the bit operation processor has a pipeline stage which includes a read stage in which a data subject to an operation 10 is read in the word unit from a memory, an operation stage following the read stage, and a write stage following the operation stage, and in the write stage a word data including a bit operation result calculated in the operation stage is written to the same address as the data read in the read stage. 15

2. The programmable controller as set forth in claim 1, wherein the memory is a cache memory of at least 2-way set-associative or full-associative, and comprises an address holding circuit that holds up to the 20 write stage, way information and index information in an cache entry which are read in the read stage.

3. The programmable controller as set forth in claim 1 or claim 2, wherein -35- when the bit operation processor performs a store instruction of the bit data in the bit operation processing instruction, the bit operation processor reads an original word data 5 including a bit to be stored in the read stage and holds the original word data in a storage unit, and merges a bit data which is the bit operation result calculated in the operation stage with the held original word data. 10

4. The programmable controller as set forth in claim 1 or claim 2, wherein the memory is a memory of two or more ports which is capable of performing one or more reads and one or more writes within a single pipeline stage processing cycle time. 15

5. The programmable controller as set forth in claim 2, which performs a cache hit determination in the read stage, and writes in the write stage a line data merged with the word data including the bit operation result to a cache entry 20 indicated by above described way information and index information which are held in the address holding circuit.

6. The programmable controller as set forth in claim 2, which switches a write-through mode and a write-back mode according -36-

*
{DESCRIPTION}
{Title of Invention}
PROGRAMMABLE CONTROLLER
{Technical Field}
5 {0001}
The present invention relates to a programmable
controller equipped with a bit operation processor which
performs high-speed sequence control for various machineries
and plants such as steel, power, water and sewerage.
10 {Background Art}
{0002}
In the programmable controller, there has been
conventionally used ladder language which is capable of writing
a sequence control efficiently. In the ladder language,
15 information such as an open or close state of a switch expressed
by one bit is inputted and information such as a relay output
expressed by one bit is outputted in many cases. Therefore,
the programmable controller is often equipped with a dedicated
bit operation processor for performing high-speed one-bit data
20 processing specific to the ladder language.
{0003}
The bit operation processor supports a dedicated
instruction set suitable for dealing with one-bit data, but must
adjust the data to an access unit size of a memory element such
-2-
as 8-bits or 16-bits because an operation result is stored in
a general-purpose memory element. To write one-bit data into
the general-purpose memory element, a read-modify-write
operation, which reads data in a memory at the access unit size,
5 modifies a part of the data read, and writes again the data
modified at the access unit size, is required. Therefore, a
ladder language processing has a characteristic that the number
of memory accesses is larger than that in a general-purpose
language processing.
10 {0004}
As a conventional technology related to speed-up of the
bit operation processor, Patent Document 1 describes a method
which stores in a high-speed accessible buffer a plurality of
past data and memory access addresses in word unit, and if an
15 address of word data including a bit to access matches an address
stored in the buffer, the number of memory accesses is reduced
by using data not in the memory but in the buffer.
{0005}
On the other hand, there have been conventionally used
20 cache memories for faster memory access in a field of
general-purpose computer. Due to semiconductor
miniaturization in recent years, countermeasures against
software errors of internal SRAM (Static Random Access Memory)
for cache memories are required, and thereby cases in which the
-3-
cache memories are protected by adding ECC (Error Check and
Correct) thereto have been increased. Since an additional unit
of ECC is designed with 4 bytes in many cases, a writing unit
to the cache memory becomes 4 bytes or more. Although writing
5 one byte or two bytes is also supported by an instruction of
general-purpose computer, a read-modify-write operation will
be performed to the cache memory if writing a data the size of
which is smaller than the additional unit of ECC is intended.
{0006}
10 If a read-modify-write operation is performed in a cache
memory of a simple configuration, the cache memory is occupied
by two or more cycles, meanwhile, a pipeline processing of the
processor is interrupted. As a method not to interrupt the
pipeline processing even with the read-modify-write operation,
15 there has been used a method to delay a store processing by
providing a plurality of store buffer stages. Patent Document
2 describes a configuration of the store buffer of the cache
memory added with ECC. Since delaying the store processing by
the store buffer is intended to perform the store processing
20 by utilizing free time of the cache memory while a load/store
instruction is not performed, it is a method which does not
surely eliminate the interruption of the pipeline processing
but reduces the probability of the interruption as much as
possible.
-4-
I
I
{0007}
Patent Document 3 describes a method for efficiently
performing instructions of data transmission between memories
by a multi-ported cache memory and separating the pipeline stage
5 of operand fetch (read) and the pipeline stage of operand write.
However, Patent Document 3 does not describe an operation when
a cache miss occurs or when an address contention of an operand
fetch with an operand write occurs, and does not describe the
read-modify-write operation at all.
10 {Citation List} I
{Patent Literature}
{0008}
{Patent Document 1}
Japanese Patent Application Publication No. Hll-039160
I 15 {Patent Document 2}
WO Publication No. 2007-088597
{Patent Document 3}
Japanese Patent Application Publication No. H04-040524
{Summary of Invention}
20 {Technical Problem}
{0009}
In the bit operation processor for ladder language
processing, it is considered to adopt a pipeline processing and
cache memories for speeding, however, it is required to prevent
-5-
a stall (an interruption) of the pipeline processing arising
from read-modify-write operations because the
read-modify-write operations occur many times in the ladder
language processing as described above. If a multistage store
5 buffer with an address comparator is used as in Patent Document
2, it is possible to reduce the probability that the pipeline
processing is interrupted, however, a program written by ladder
language tends to have higher ratio of store instructions in
bit unit than general-purpose languages, and it is required to
10 increase the number of store buffer stages, and thereby the
circuit scale required for implementation becomes large.
{0010}
On the other hand, since a concept of RISC (Reduced
Instruction Set Computer) is adopted into instruction sets of
15 almost all of current general-purpose processors, an operation
processing and a load/store processing are adapted to be
performed by different instructions respectively. In other
words, the operation processing is performed between
general-purpose registers by an operation instruction, and the
20 load/store processing between a memory and a register is adapted
to be performed by another instruction. Therefore, the
pipeline for the general-purpose processor is configured such
that suitable for a register-to-register operation, however,
the ladder language processing is mainly an operation between
-6-
I
the memory and an accumulator, and thereby the pipeline
configuration for the general-purpose processor is not
necessarily good in processing efficiency.
{0011}
5 Problems will be described by specific examples, when the
ladder language processing is performed by a pipeline and memory
configuration according to the prior art. FIG. 14 shows a
typical pipeline configuration of the RISC processor. PC
(Program Counter) is a stage calculating an instruction address,
10 IF (Instruction Fetch) is a stage fetching the instruction, D
(Decode) is a stage decoding the fetched instruction, EX
(Execute) is a stage executing the register-to-register
operation or memory address calculation, M (Memory) is a stage
reading data from a memory or writing data into a memory, and
15 WB (Write Back) is a stage writing back an operation result or
a read value. If the read-modify-write operation is performed
with a bit data operation, an M stage is divided into Ml and
M2, and reading is performed in Ml cycle and merging and writing
of bit data are performed in M2 cycle.
20 {0012}
Here is described a case in which a ladder diagram
illustrated in FIG. 7A is performed by the pipeline
configuration according to the prior art. FIG. 7B is an example
of a program which is converted to an instruction sequence of
-7-
i I
I
a normal ladder language from the ladder diagram illustrated
in FIG. 7A. FIG. 7C is an example of a program which is converted
from the ladder diagram illustrated in FIG. 7A to an instruction
sequence to be performed by the pipeline configuration
5 according to the prior art.
{0013}
Variables X0 to X3 represent inputs, variables Y2 to Y3
represent outputs, and it is assumed that they are stored
respectively in two word data in a memory as a one-bit length
10 data. FIG. 8 shows a state in which these variables are
allocated to and stored in the memory. In FIG. 7B, LD (Load)
is a load instruction from the memory to the accumulator, AND
is an instruction for storing in the accumulator a logical
product of an accumulator value and a value loaded from the
15 memory, ST (Store) is an instruction for storing the accumulator
value in the memory, and OR is an instruction for storing in
the accumulator a logical sum of the accumulator value and the
value loaded from the memory. In FIG. 7C, LD is a load
instruction from the memory to the register, AND is an
20 instruction for storing in the register a logical product of
two register values, ST is an instruction for storing the
register value in the memory, and OR is an instruction for
storing in the register a logical sum of two register values.
{0014}
-8-
i
I
FIG. 15 is a time chart showing operations when the
instruction sequence illustrated in FIG. 7C is performed by the
pipeline configuration in FIG. 14. As shown in FIG. 15, first
and second LD instructions are started respectively from cycle
5 tO and tl, and performed as it is respectively up to cycle t5
and t6, and then the data are loaded respectively to registers
Rl and R2 . A third AND instruction is performed as it is from
a cycle t2 to a cycle t4, however, the pipeline is stalled for
one cycle ("-" mark) because data of the variable XI required
10 in an EX stage of a cycle t5 has not been read yet. The data
of the variable XI is available in the next cycle t6 when the
performance of the second LD instruction in the M stage is
completed, and then the third AND instruction is performed as
it is up to a cycle t8. A fourth ST instruction is started from
15 a cycle t3, but the pipeline is stalled along with a stall of
the former instruction. After cycles of t6 and t7 are performed
subsequently, the read-modify-write operation is performed
over two cycles of t8 and t9 in the M stage. Therefore, a fifth
LD instruction is stalled in a cycle t9 in addition to the cycle
20 t5.
{0015}
In the same manner, a sixth LD instruction is stalled in
the cycles of t5 and t9, and a seventh OR instruction and a eighth
ST instruction are stalled respectively in cycles of t9 and til.
-9-
In the eighth ST instruction, the read-modify-write operation
is performed over two cycles of tl4 and tl5. As described above,
the pipeline configuration according to the prior art requires
eight instructions to perform the processing which is described
5 by six instructions written by the normal ladder language and
the pipeline is stalled in three cycles, thereby resulting in
that the pipeline configuration requires seventeen cycles in
total until all the processing is completed.
{0016}
10 The purpose of the present invention is to propose a
pipeline configuration which is suitable for a programmable
controller equipped with a bit operation processor for
processing the ladder language, and does not cause a stall of
the pipeline processing arising from the read-modify-write
15 operation and so on. Further, another purpose of the present
invention is to propose a configuration of a cache memory and
the pipeline suitable for the bit operation processor equipped
with the cache memory.
{Solution to Problem}
20 {0017}
In order to not cause a stall of the pipeline processing
in the bit operation processor for processing the ladder
language, it is sufficient that the operation result in an EX
stage is available in the EX stage of the next instruction
-10-
performed in the next cycle, while an R (Read) stage is provided
as a new stage for reading in advance a content in a memory which
is subject to a read-modify-write operation, the bit operation
and merging of the bit data are performed in the next EX stage,
5 and the results are stored in the memory in the last W (Write)
stage.
{0018}
To achieve the above object, one aspect of the present
invention provides a programmable controller, which performs
10 read and write of memory in a word unit composed of a plurality
of one-bit data subject to a bit operation processing,
comprising a bit operation processor which performs in parallel
a bit operation processing instruction sequence contained in
a program by a pipeline processing mechanism, wherein the bit
15 operation processor has a pipeline stage which includes a read
stage in which a data subject to a bit operation is read in the
word unit from a memory, an operation stage following the read
stage, and a write stage following the operation stage, and in
the write stage a word data including a bit operation result
20 calculated in the operation stage is written to the same address
| as the data read in the read stage.
{0019}
Another aspect of the present invention provides a
programmable controller, wherein the memory is a cache memory
-11-
of at least 2-way set-associative or full-associative, and
includes an index holding register and a way holding register
that hold up to the write stage, respectively index information
and way information in an cache entry which are read in the read
5 stage.
{0020}
Further, in order not to stall the pipeline processing
even if the instructions access the memory consecutively, the
memory is preferably a memory of two or more ports which is
10 capable of performing one or more reads and one or more writes
independently within a single pipeline processing cycle time.
{0021}
It should be noted that Patent Document 3 describes a
pipeline configuration composed of cache read, operation, and
15 cache write in this order, however, it is an object to perform
read and write independently, so that read and write can be
assigned at different addresses, and thereby a cache hit
determination is performed even when performing the cache write.
In other words, it is not considered that a read-modify-write
20 operation is performed, and the object and configuration of
Patent Document 3 are different from those of the present
invention in that, for example, a memory of 3-ports for 2-reads
plus 1-write is required.
{Advantageous Effects of Invention}
-12-
{0022}
i t
According to the present invention, a stall of pipeline
processing along with a read-modify-write operation does not
occur in a program performed in the programmable controller
5 equipped with the bit operation processor. Therefore, the
programmable controller is capable of efficiently processing
a program written by the ladder language. In addition, since
the stall of pipeline processing does not occur either in the
bit operation processor equipped with the cache memory, the
10 programmable controller is capable of efficiently processing
the program written by the ladder language. Further, a pipeline
control is simplified because a cache change processing in the
write stage is not necessary by performing the cache hit I
determination at a preceding read stage when performing a store
15 instruction.
{Brief Description of Drawings}
{0023}
FIG. 1 is a diagram showing a pipeline configuration and
an internal configuration of a bit operation processor included
20 in a programmable controller according to a first embodiment
of the present invention.
FIG. 2 is a diagram showing an entire configuration of
the programmable controller according to the first embodiment
of the present invention.
-13-
FIG. 3 is a block diagram showing a configuration in a
case of using a 2-port memory as a data memory.
FIG. 4 is a diagram showing a detailed configuration of
an operation stage of the bit operation processor according to
I 5 the first embodiment of the present invention.
FIG. 5 is a diagram showing a configuration of a cache
memory according to a second embodiment of the present
invention.
FIG. 6 is a diagram showing a detailed configuration of
10 an operation stage in the bit operation processor according to
the second embodiment of the present invention.
FIG. 7A is a ladder diagram for illustrating an operation
of the bit operation processor.
FIG. 7B is an example of a program converted to an
15 instruction sequence of ladder language from the ladder diagram
illustrated in FIG. 7A.
FIG. 7C is an example of a program converted from the
instruction sequence in FIG. 7B to an instruction sequence
performed by a pipeline configuration according to the prior
20 art.
FIG. 8 is a diagram showing an allocation of variables
used in the programs in FIGS. 7B and 7C to a memory.
FIG. 9 is a diagram showing formats of instructions
performed by the bit operation processor.
-14-
«
FIG. 10 is a diagram showing a state in which an
instruction code sequence for a program in FIG. 7B is stored
in a memory.
FIG. 11 is a time chart showing an operation example of
5 the bit operation processor according to the first and second
embodiments of the present invention.
FIG. 12 is a time chart showing an operation example in
a case where a cache miss occurs in the bit operation processor
according to the second embodiment of the present invention.
10 FIG. 13 is a diagram showing a pipeline configuration
according to the first embodiment in comparison with a pipeline
configuration in FIG. 14.
FIG. 14 is a diagram showing a pipeline configuration of
a typical RISC processor.
15 FIG. 15 is a time chart showing an operation example of
a bit operation processor according to the prior art.
{Description of Embodiments}
{0024}
Hereinafter, embodiments of the present invention will
20 be explained with reference to FIGS. 1 to 13.

FIG. 1 is a diagram showing a pipeline configuration and
an internal configuration of a bit operation processor included
in a programmable controller according to a first embodiment
-15-
of the present invention. FIG. 13 is a diagram showing a
pipeline configuration according to the first embodiment in
comparison with a pipeline configuration according to the prior
art in FIG. 14. As shown in FIGS. 1 and 13, the pipeline
5 configuration according to the first embodiment is composed of
six stages, i.e., (1) a program counter (PC) stage, (2) an
instruction fetch (IF) stage, (3) a decode (D) stage, (4) a
memory read (R) stage, (5) an operation execution (EX) stage,
and (6) a memory write (W) stage.
10 {0025}
The PC stage includes an adder 102 for adding a constant
"1" or a specified register value to a value of PC (program
counter) 101 indicating an instruction address just before, and
a selector 103 for selecting the added result or a register value
15 indicating a branch destination address. The PC stage sets an
address of an instruction to be performed following the selected
instruction just before, to an instruction address register 111
as an output of the PC stage. The IF stage reads an instruction
corresponding to the instruction address set in the instruction
20 address register 111 from an instruction buffer 30, and sets
the instruction to an instruction register 121.
{0026}
The D stage includes a decoder 122 interpreting the
instruction that is read, and an adder 123 for adding the
-16-
I
specified register value to an address extracted from the
instruction by the decoder 122. If the decoded instruction is
accompanied by a memory access, the D stage generates a data
address and sets it to a data address register 131. Further,
5 although not shown, control information required to control the
subsequent stages such as a register selection and an operation
function selection are extracted according to the decoded
result.
{0027}
10 The R stage reads a data corresponding to a data address
indicated by the data address register 131 from a data memory
20. The data that is read is set to a word buffer 141 via a
selector 132 for selecting the data and a bypass data from the
next EX stage. In addition, the data address indicated by the
15 data address register 131 is set to an address holding circuit
22 in the data memory 20 so that the data address can be used
again in the W stage. I
{0028}
The EX stage includes an ALU (Arithmetic Logic Unit) 142
20 and a bit merging mechanism 143, and executes an operation
indicated by an instruction by using the specified register
value and/or a data value set in the word buffer 141. At this
time, if the bit data operation is performed, the bit data
operation is performed by extracting a bit data at a bit position
-17-
ft
designated from among word data subject to an operation, and
a word data is generated by embedding the bit data of the
operation result in the bit position by using the bit merging
mechanism 143. If a destination to store the operation result
5 is a register, the result is written into a register file 152,
and if a destination to store the operation result is the data
memory 20, the data of the operation result to be stored is
written into a write buffer 151.
{0029}
10 The W stage stores the data set in the write buffer 151
to the data address set in the address holding circuit 22 in
the R stage, i.e., the data address in the data memory 20 the
same as the address of the data that is read in the R stage.
{0030}
15 FIG. 2 is a diagram showing an entire configuration of
the programmable controller according to the first embodiment
of the present invention. As shown in FIG. 2, a programmable
controller 1000 includes a CPU (Central Processing Unit) module
1, I/O (Input/Output) modules 2A and 2B, I/O buses 3 connecting
20 the CPU module and the I/O modules, and a program input device
4 which is detachably connected to the CPU module 1. The I/O
modules 2A and 2B are respectively provided with an I/O bus
connection circuit and an I/O interface circuit, and are adapted
to change the type and the number thereof depending on the
-18-
specification of the required I/O and the number of the
connections.
{0031}
The CPU module 1 includes a bit operation processor 10,
5 the data memory 20, the instruction buffer 30, an I/O bus control
circuit 40, a memory controller 50, an external RAM (Random
Access Memory) 60, a ROM (Read Only Memory) 70, a
general-purpose microprocessor 80, and an communication I/F
(interface) 90.
10 {0032}
Data groups of a predetermined address range stored in
the data memory 20 respectively corresponds to the input data
or the output data exchanged between external devices (not
shown) connected to the I/O modules 2A and 2B. The I/O bus
15 control circuit 40 controls the I/O buses 3, writes into the
data memory 20 the input data obtained from the external devices
connected to the I/O modules 2A and 2B, and output the output
data read from the data memory 20 to the external devices
connected to the I/O modules 2A and 2B via the I/O buses 3.
20 {0033}
If an instruction for an instruction address requested
from the bit operation processor 10 is stored in the buffer,
the instruction buffer 30 returns the instruction to the bit
operation processor 10, and if the instruction is not stored
-19-
*
in the buffer the instruction buffer 30 requests the memory
controller 50 to read the instruction from the external RAM 60.
The memory controller 50 performs read/write of the external
RAM 60 or read of the ROM 70 according to requests from the bit
5 operation processor 10, the instruction buffer 30, the I/O bus
control circuit 40, and the general-purpose microprocessor 80.
The general-purpose microprocessor 80 controls the entire
programmable controller 1000, for example, the general-purpose
microprocessor 80 writes to the external RAM 60 a ladder program
10 loaded from the program input device 4 via the communication
I/F 90. A program for operating the general-purpose
microprocessor 80 is stored in the ROM 70.
{0034}
In the present embodiment, the bit operation processor
15 10, the data memory 20, the instruction buffer 30, the I/O bus
control circuit 40, and the memory controller 50 are assumed
to be built in a system LSI (Large Scale Integration) 100.
{0035}
FIG. 3 is a block diagram showing a configuration in a
20 case of using a 2-port memory suitable for the data memory 20
according to the present invention. As shown in FIG. 3, the
data memory 20 includes an address selector 201, the address
holding circuit 22 having address holding registers 221 and 222,
a write address selector 215, a write data selector 204, and
-20-
a memory array 21.
{0036}
The address selector 201 selects one of a value in the
data address register 131 (see FIG. 1) of the bit operation
5 processor 10 and an I/O data address outputted from the I/O bus
control circuit 40. The address holding registers 221 and 222
hold the data address used to execute the R stage up to the W
stage after two cycles. In other words, the data address is
held in the first stage address holding register 221 as an output I
10 data of the R stage, and the value is copied to the second stage
address holding register 222 as an output data of the EX stage,
so that the value can be used in the W stage.
{0037}
The write address selector 215 selects one of a value in
15 the data address register 131 and a value in the address holding
register 222 . The write data selector 204 selects one of a value
in the write buffer 151 and a value of an I/O data outputted
from the I/O bus control circuit 40.
{0038}
20 The memory array 21 is configured with 2-port memories
such that both of a port 1 for reading and a port 2 for writing
are accessible in a single cycle. Therefore, a processing of
an instruction subject to a pipeline processing in the R stage
and a processing of another instruction in the W stage to be
-21-
•
performed in parallel with the R stage can be performed in
parallel in the same cycle. Here, the memory array 21 is
configured with 2-port memories, however, it may be configured
with memories of three or more ports such that one or more ports
5 for read and one or more ports for write are accessible in a
single cycle . Since read and write are performed independently
at the time of memory access from the I/O bus control circuit
40, the address holding circuit 22 is not used.
{0039}
10 FIG. 4 is a diagram showing a detailed configuration of
an operation stage (the EX stage, including some elements of
other stages) of the bit operation processor according to the
first embodiment. As shown in FIG. 4, the operation stage
includes an ALU 142, selectors 144 and 145 for selecting inputs
15 of the ALU 142, the selector 132 (the element of the R stage)
for selecting one of 1-word (16-bits) data read from the data
memory 20 and a bypass data for using an operation result of
the operation stage again for the operation at the next
instruction, and the word buffer 141 for holding the selected
20 word data. The operation stage further includes the bit merging
mechanism 143 for merging an output of the ALU 142 as the
operation result to an inputted word data, the write buffer 151
for holding the bit-merged data, and the register file 152 (the
element of the W stage) for holding data in an accumulator, a
-22-
general-purpose register, and the like. The ALU 142 is capable
of performing the operation of one-bit length or one-word, i.e.,
16-bits length.
{0040}
5 FIG. 9 is a diagram showing formats of instructions
performed by the bit operation processor 10. As shown in FIG.
9, the instruction has two formats but both have 32-bits fixed
length. An instruction format 1 includes 5-bits instruction
code (OP: Operation), 4-bits bit position field (BA: Bit
10 Address), and 23-bits word address field (WA: Word Address),
and is subject to a bit data. An instruction format 2 includes
5-bits instruction code (OP: Operation), 4-bits bit register
specification field (RA: Register Address), and 23-bits word
address field (WA: Word Address) , and is subject to a word data.
15 {0041}
Next, an operation of the bit operation processor 10
according to the present embodiment will be described by using
a time chart in FIG. 11, with reference to FIG. 1, with examples
of the ladder program shown in FIGS. 7B and 8. FIG. 10 is a
20 diagram showing a state in which an instruction code sequence
for the ladder program in FIG. 7B is stored in a program memory
(external RAM 60) , and the instruction code sequence is assumed
to be stored in order from address A.
{0042}
-23-
A first LD instruction is started from a cycle to, and
performed as it is up to a cycle t5. At this time, an address
of the LD instruction is calculated and set to the instruction
address register 111 in the cycle tO (PC stage). In a cycle
5 tl (IF stage), the instruction is read from the instruction
buffer 30 and set to the instruction register 121. In a cycle
t2 (D stage), the instruction is decoded and recognized that
it is the LD instruction. Since a word address to be read is
directly specified in the first LD instruction, the word address
10 is set to the data address register 131. In a cycle t3 (R stage),
1-word data including a bit data subject to an operation is read
from the data memory 20 and set to the word buffer 141. In a
cycle t4 (EX stage) , a bit of a variable X0 subject to an
operation is extracted and set to an accumulator included in
15 the register file 152. In a cycle t5 (W stage), no operation
is performed (a shaded area in FIG. 11).
{0043}
A second AND instruction is started from the cycle tl and
performed as it is up to a cycle t6. No operation is performed
20 in the cycle t6 (W stage) . At this time, the second AND
instruction is performed in the same manner as the first LD
instruction from the PC stage to the R stage. In the cycle t5
(EX stage) , after bits of a variable XI subject to an operation
are extracted, a logical product of the bits and a content in
-24-
an accumulator is calculated in the ALU 142 and set to the
accumulator again. In the present embodiment, a word data
including the variable XI is read in the R stage performed before
the EX stage, and thereby the pipeline processing is not stalled
5 in the EX stage of the AND instruction as the example (see FIG.
15) according to the prior art.
{0044}
A third ST instruction is started from the cycle t2 and
performed as it is up to a cycle t7. The third ST instruction
10 is performed in the same manner as the first LD instruction from I
the PC stage to the R stage. The present embodiment has a great
feature that data reading is performed in advance in the R stage,
also in the ST instruction. In the cycle t6 (EX stage), an
accumulator value (1 bit) is read, and a result merged with a
15 value (1 word) in the word buffer 141 is set to the write buffer
151. At the W stage in the cycle t7, contents in the write buffer
151 are stored in the data memory 20. At that time, as a memory
address of a storage destination, contents stored in the address
holding circuit 22 which holds a value used in the R stage are
20 used. As described above, according to the pipeline
configuration of the present embodiment, a stall of the pipeline
configuration does not occur even when one-bit data write is
performed.
{0045}
-25-
By the same operation as described above, a fourth LD
instruction is performed from the cycle t3 to a cycle t8, a fifth
OR instruction is performed from the cycle t4 to a cycle t9,
and a sixth ST instruction is performed from the cycle t5 to
5 a cycle tlO, respectively as it is in the pipeline processing.
As described above, according to the present embodiment, a stall
of the pipeline processing does not occur during performing the
six instructions at all, and it is possible to reduce the number
of cycles, which are required to perform the processing
10 described by the six instructions shown in FIG. 7B, to 11 cycles
from 17 cycles according to the prior art.
{0046}
As described above, according to the programmable
controller equipped with the bit operation processor according
15 to the present embodiment, a bit operation processing specific
to the ladder language processing can be performed in one cycle
pitch without a stall of the pipeline processing, thereby
performing a program written by the ladder language at high
speed.
20 {0047}

Subsequently, a second embodiment of the present
invention will be described. The second embodiment is
configured by replacing the data memory 20 (see FIG. 2) in the
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first embodiment to a cache memory. FIG. 5 is a diagram showing
a configuration of the cache memory according to the second
embodiment. As shown in FIG. 5, the cache memory 20A as the
data memory 20 is a two-way set-associative cache memory, and
5 includes an address selector 201A, index holding registers 221A
and 222A, a way selector 203, a write data selector 204A, a way
0 tag memory 205, a way 1 tag memory 206, a LRU (Least Recently
Used) memory 207, a way 0 data memory 208, a way 1 data memory
209, a hit determination circuit 210, a write-back control
10 circuit 211, a way data selector 212, and a way holding registers
213 and 214. The address holding circuit 22 in FIG. 1 is
configured by an address holding circuit 1 (22A) including the
index holding registers 221A, 222A, and an address holding
circuit 2 (22B) including the way holding registers 213, 214.
15 {0048}
The way data memories 208, 209 have 256 entries
respectively, and each entry holds 16 bytes (8 words) data. An
access unit of the cache memory is 16 bytes, and a data of the
16 bytes unit is referred to as 1 line.. The tag memories 205,
20 206 have 256 entries respectively, and each entry includes a
valid bit V (Valid), a dirty bit D (Dirty), and a tag address
(abbreviated as "TAG" in FIG. 5). The LRU memory 207 has 256
entries and holds the ways recently used.
{0049}
-27-
The address selector 201A selects one of a value of the
data address register 131 (see FIG. 1) in the bit operation
processor 10 and an I/O data address outputted from the I/O bus
control circuit 40, and extracts a 12 bits tag address and a
5 8 bits index value from among them. The index holding registers
221A, 222A hold the 8 bits index value extracted from the data
address used to execute the R stage up to the W stage after two
cycles. Similarly, the way holding registers 213, 214 hold the
way hit in the R stage up to the W stage.
10 {0050}
The way selector 203 outputs an index value stored in the
second stage index holding register 222A and a hit way stored
in the second stage way holding register 214 to the way data
memories 208, 209 as the index value and the way for writing 1
15 in the W stage. The write data selector 204A selects one of
a value in a write buffer 151A described later and one line I/O
data value outputted from the I/O bus control circuit 40.
{0051}
The hit determination circuit 210 compares the upper 12
20 bits of the data address to be accessed and a tag value outputted
from the tag memories 205, 206 with respect to each way, and
determines a hit or miss. The way data selector 212 selects
a line data of a way 0 data or a way 1 data according to the
output of the hit determination circuit 210. Since cache
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reading and writing are performed independently at the time of
cache access from the I/O bus control circuit 40, the address
holding circuits 1, 2 (22A, 22B) are not used.
{0052}
5 If a subject entry of an eviction way (a way which is not
used recently) indicated by an output of the LRU memory 207 at
the time of a cache miss is in an address range for a write-back
mode and "Dirty", in other words, if the data has been updated,
the write-back control circuit 211 transmits the data read at
10 the same time with the tag to the memory controller 50, and
updates stored contents in the external RAM 60 (see FIG. 2).
Note that the write-back operation is not performed for a
predetermined address range corresponding to the I/O data
address, because the operation is changed to a write-through
15 mode to immediately update the stored contents. In addition,
a line data which has been a cache miss is read into the evicted
subject entry by a read control circuit not shown.
{0053}
It is preferable that the tag memories 205, 206 and the
20 way data memories 208, 209 constituting the cache memory 20A
are configured by memories of two or more ports in which a port
for read and a port for write are accessible in parallel in a
single cycle, and thereby it is possible to eliminate a stall
of the pipeline processing caused by a competition of memory
-29-
accesses. Further, the cache memory 20A is the two-way
set-associative type in this case, but may be a set-associative
type of three-way or more, or a fully associative type.
{0054}
5 FIG. 6 is a diagram showing a detailed configuration of
an operation stage (the EX stage, including some elements of
other stages) in the bit operation processor according to the
second embodiment. As shown in FIG. 6, the configuration of
the operation stage is different from the configuration of the
10 operation stage (see FIG. 4) according to the first embodiment
in that the size of the input and output data is changed to 1
line length (16 bytes = 128 bits) and a unit which holds a data
of 1 line length and merges the data with a word data of an
operation result is added. Since the other configuration
15 elements are the same as those in FIG. 4, redundant descriptions
will be omitted.
{0055}
A selector 132A (an element of the R stage) selects one
of 1 word (16bits) among 1 line (16bytes) length data read from
20 the cache memory 20A and a bypass data for using an operation
result of the operation stage again for the operation at the
next instruction. A line buffer 146 holds 1 line length data
which has been read. A word merging mechanism 147 merges a word
data of an operation result which is the output of the bit merging
-30-
mechanism 143 with the line data held in the line buffer 146.
A write buffer 151A holds the 1 line data which has been merged.
{0056}
Here, similarly to the above, an operation of the bit
5 operation processor according to the present embodiment will
be described with reference to an example of the ladder program
shown in FIGS. 7B and 8. The operation is the same as the time
chart in FIG. 11 described above, if the cache memory 20A is
configured with a 2-port memory which is capable of performing
10 a read operation and a write operation in a single cycle and
the subject data is assumed to be all cache hit. The operation
according to the present embodiment is different from the first
embodiment described above in that read and write of data in
the R stage and the W stage is performed in 1 line unit, and
15 in the EX stage, the operation is performed for the subject word
extracted by the selector 132A and the word data of the operation
result is merged with a line data held in the line buffer 146
to generate a line data for the write operation.
{0057}
20 Next, an operation when a cache miss occurs at the third
ST instruction in the ladder program in FIG. 7B will be described
using a time chart in FIG. 12. The operations of the first LD
instruction and the second AND instruction are the same as FIG.
11. If a cache miss occurs in the R stage (cycle t5) of the
-31-
third ST instruction, the pipeline processing is stalled, for
example, from the cycle t5 to the cycle tl4, because a data in
the external RAM 60 is read via the memory controller 50.
However, the operation is performed without a stall of the
5 pipeline processing after the R stage is resumed in the cycle
tl5. In this manner, since it is enough to exchange cache lines
in the R stage even if a cache miss for the ST instruction occurs,
the cache control is simplified.
{0058}
10 Even if a data address accessed by the next instruction
of the ST instruction has the same index value with the ST
instruction and the next instruction is a cache miss, the entry
has never been purged before the ST instruction overwrites the
line data in the W stage if the cache memory is more than two-way
15 set-associative.
{0059}
As described above, according to the programmable
controller equipped with a bit operation processor with a
built-in cache memory according to the second embodiment, the
20 bit operation processing specific to the ladder language
processing can be performed in one cycle pitch without a stall
of the pipeline processing, thereby performing a program
written by the ladder language at high speed.
{0060}
-32-
The description of the embodiments according to the
present invention is finished, however, the aspect of the
embodiments according to the present invention is not limited
thereto, but can be variously changed in a range without
5 departing the spirit of the present invention.
{Reference Signs List}
{0061}
1: CPU module
2A, 2B: I/O module
10 3: I/O bus
4: program input device
10: bit operation processor
20: data memory
20A: cache memory
15 21: memory array
22, 22A, 22B: address holding circuit
30: instruction buffer
40: I/O bus control circuit
50: memory controller
20 60: external RAM
7 0: ROM
80: general-purpose microprocessor
90: communication I/F
100: system LSI
-33-
1000: programmable controller
-34-

j
WE CLAIM:
1. A programmable controller, which performs read and write of
memory in a word unit composed of a plurality of one-bit data
subject to a bit operation processing, comprising
5 a bit operation processor which performs in parallel a
bit operation processing instruction sequence contained in a
program by a pipeline processing mechanism, wherein
the bit operation processor has a pipeline stage which
includes a read stage in which a data subject to an operation
10 is read in the word unit from a memory, an operation stage
following the read stage, and a write stage following the
operation stage, and in the write stage a word data including
a bit operation result calculated in the operation stage is
written to the same address as the data read in the read stage.
15
2. The programmable controller as set forth in claim 1, wherein
the memory is a cache memory of at least 2-way
set-associative or full-associative, and
comprises an address holding circuit that holds up to the
20 write stage, way information and index information in an cache
entry which are read in the read stage.
3. The programmable controller as set forth in claim 1 or claim
2, wherein
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when the bit operation processor performs a store
instruction of the bit data in the bit operation processing
instruction,
the bit operation processor reads an original word data
5 including a bit to be stored in the read stage and holds the
original word data in a storage unit, and
merges a bit data which is the bit operation result
calculated in the operation stage with the held original word
data.
10
4. The programmable controller as set forth in claim 1 or claim
2, wherein the memory is a memory of two or more ports which
is capable of performing one or more reads and one or more
writes within a single pipeline stage processing cycle time.
15
5. The programmable controller as set forth in claim 2, which
performs a cache hit determination in the read stage, and
writes in the write stage a line data merged with the word
data including the bit operation result to a cache entry
20 indicated by above described way information and index
information which are held in the address holding circuit.
6. The programmable controller as set forth in claim 2, which
switches a write-through mode and a write-back mode according
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