Claims: 1. A programmable data width converter (pDWC) comprising: a control Finite State Machine (FSM) configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n, wherein the pDWC is configured to programmably convert width of ‘m’ k-bit word input to ‘n’ k-bit word output, and wherein 1 m M and 1 n N; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. 2. The converter of claim 1, wherein the pSRL is loaded based on value of the LL and by setting L=1, and wherein the pSRL is shifted by setting S=1 in a manner such that data is loaded in m bits and read out in n bits. 3. The converter of claim 1, wherein the pSRL is at least M+N bits wide. 4. The converter of claim 1, wherein the p is equal to n. 5. The converter of claim 1, wherein the load register width is M bits, and wherein m bits of said load register are used. 6. The converter of claim 1, wherein the control FSM loads at least n bits into the pSRL that has width W where W (M+N), and wherein if m > n, only one load is required, else if m < n, multiple load cycles are required with S=0. 7. The converter of claim 6, wherein the control FSM keeps a count C of bits that are currently in the pSRL, wherein each load increments the C by m such that when C n has been loaded into the pSRL, the control FSM initiates a shift that shifts out n bits and decrements C by n, and wherein when a load and shift happen together, (m-n) is added to C, and wherein whenever a free space exists in the pSRL as defined by (W-C) (m-n), the control FSM performs a load cycle, and wherein when L=S=1, loading happens while shifts are going on. 8. The converter of claim 1, wherein the pDWC is a k-bit pDWC with the control FSM being operatively coupled with either a large pSRL allowing m and n to be integral multiples of k, or being operatively coupled to control k single-bit pSRLs in parallel. 9. The converter of claim 8, wherein the pDWC requires a minimum of or equal to k×(M+N) number of flops. 10. The converter of claim 1, wherein the pSRL is any of a right shift register or a left shift register. 11. The converter of claim 1, wherein the LL defines where data D is loaded. 12. A method for programmably converting width of m k-bit word input into n k-bit word output by a programmable data width converter (pDWC), said method comprising: receiving, by a control Finite State Machine (FSM), input values of m and n; controlling, by the control FSM, any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; converting programmably, by the pDWC, width of ‘m’ k-bit word input to ‘n’ k-bit word output, and wherein 1 = m = M and 1 = n = N; and performing, by a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. 13. The method of claim 12, wherein if load and shift happen together, (m-n), is added to C. , Description: FIELD OF THE INVENTION [0001] The present disclosure relates generally to Integrated Circuit (IC) devices having circuitry with programmable functions and programmable interconnections, and more particularly, the present disclosure pertains to devices, systems, and methods for width conversion of data streams. BACKGROUND [0002] The background description includes information that may be useful in understanding present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art. [0003] In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history. This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has state (memory) while combinational logic does not. As conventionally known, Shift Register (SR) is a type of sequential logic circuit that can be used for storage or transfer of data in the form of binary numbers. This sequential device loads data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name Shift Register. A SR basically consists of several single bit “D-Type Data Storage elements”, one for each data bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that output from one data storage element becomes input of the next storage element and so on. [0004] In digital circuits, a SR is a cascade of flip flops, sharing same clock, in which output of each flip-flop is connected to 'data' input of next flip-flop in the chain, resulting in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data present at its input and 'shifting out' the last bit in the array, at each transition of the clock input. Data bits may be fed in or out of a SR serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration. The number of individual data storage elements required to make up a single SR device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight individual data storage elements. SRs are used for data storage or for movement of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. Individual data storage elements that make up a single SR are all driven by a common clock signal making them synchronous devices. [0005] Directional movement of data through a SR can be either to the left (left shifting) to the right (right shifting) left-in but right-out (rotation) or both left and right shifting within the same register, thereby making it bidirectional. FIG. 1A illustrates an exemplary working 100 of shift register as available in the prior-art. The effect of data movement from left to right through a SR can be presented graphically in FIG. 1A. Also, the directional movement of the data through a shift register can be either to the left (left shifting) to the right (right shifting) left-in but right-out (rotation) or both left and right shifting within the same register thereby making it bidirectional. However, because data must be retrieved one bit at time, it also takes N clocks to retrieve N bits of data stored in an N-bit SISO shift register. The 4-bit shift register requires 4 clocks to retrieve the 4 bits stored in it. Thus, the conventional SRs need to be made configurable and re-configurable such that they are more precise in data storage and transfer of the data and meet the requirement of real time dynamic nature of operations. [0006] Conventionally known, programmable logic device (PLD) is an electronic component used to build reconfigurable digital circuits. PLD is any IC that has programmable functions and programmable interconnections. PLD commonly includes one or more data paths, or collections of digital signals routed through the system during processing. Size of a collection, called the “data width” or “data path width” herein, depends on a number of factors. One factor in determining data path width is significance of signals (i.e., information that the signals represent, and the format of the signals). Another factor is the required speed of operation of the design. Yet another factor relates to size constraints introduced by the design. Other factors may also possibly affect data path width. In some cases, it may be desirable to modify the width of a data path at some point in the design, changing the extent to which data is propagated in parallel. This may be necessary, for example, because of different operating speeds in different portions of the design, or different constraints on the data width in different portions of the design. It may also be beneficial for this data width modification to be programmable and to be done dynamically. It would therefore be desirable to have a PLD capable of implementing a variable-width data path. [0007] There is therefore a need in the art for programmable data width conversion that efficiently reduces the number of flops, and also reduces latency that is associated with reduced number of flops. Further, there is also a need to provide an improved system, device, and method that includes storage capable of ensuring that all combinations of bits fit in the storage without any left over. Furthermore, there is also a need to provide an improved programmable data width converter capable of achieving aforementioned needs arriving with the growth and development of the technology. [0008] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply. [0009] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. [0010] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise. [0011] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention. [0012] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims. SUMMARY [0013] The present disclosure relates generally to integrated circuit (IC) devices having circuitry with programmable functions and programmable interconnections, and more particularly, the present disclosure pertains to devices, systems, and methods for width conversion of data streams. [0014] It may be appreciated that, for understanding of the subject matter, a load register having a fixed data width is referred to/denoted as “M” hereinafter, a load register having a variable data width is referred to/denoted as “m” hereinafter, a read register having a new fixed data width is referred to/denoted as “N” hereinafter, a read register having a new variable data width is referred to/denoted as “n” hereinafter, and the number of sample bits is referred to as “k” hereinafter. [0015] The present disclosure provides a new, cost-effective, technically advanced and improved programmable data width converter (pDWC) that serves as a storage device for data streams. In an embodiment, the proposed pDWC ensures that all combinations of {m, n} bits fit in the storage so as to allow a user to always write-in n (m × k)-bit words, and read-out m (n × k)-bit words. The proposed pDWC enables writing-in of n (m × k)-bit words and reading-out of m (n × k)-bit words in at least (k × (M + N)) flops with the least possible latency. Thus, the proposed pDWC not only efficiently reduces the number of flops, but also reduces latency associated with such reduced number of flops. Further, the proposed pDWC includes storage capable of ensuring that all combinations of {m, n} bits fit in the storage without any left over. [0016] An aspect of the present disclosure relates to a programmable data width converter (pDWC) that includes a control Finite State Machine (FSM), and a loadable programmable shift register (pSR) with programmable load location (complete register (pSR with programmable load location) being hereinafter referred to as pSRL). The control Finite State Machine (FSM) receives input values of m and n, and controls any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n. The loadable programmable shift register with programmable load location (pSRL) is operatively coupled with the control FSM, and is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. [0017] In an aspect, the pDWC is configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1 = m = M and 1 = n = N (M and N being any positive integers). [0018] In an aspect, the pSRL can be loaded based on value of the LL, and by setting L=1, and wherein the pSRL can be shifted by setting S=1 in a manner such that data is loaded in m bits and read out in n bits. [0019] In an aspect, the pSRL is at least M+N bits wide. In another aspect, the p is equal to n. In an aspect, the pSRL is any of a right shift register or a left shift register. In another aspect, the LL defines where data D is loaded. [0020] In an aspect, the pSR can be configured to receive a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal) = 1. [0021] In an aspect, the load register width is M bits, and wherein m bits of said load register are used. [0022] In an aspect, the control FSM loads at least n bits into the pSRL that has width W where W (M+N), and wherein if m > n, only one load is required, else if m < n, multiple load cycles are required with S=0. In another aspect, the control FSM keeps a count C of bits that are currently in the pSRL, wherein each load increments the C by m such that when C = n has been loaded into the pSRL, the control FSM initiates a shift that shifts out n bits and decrements C by n. In yet another aspect, when a load and shift happen together, (m-n) is added to C, and wherein whenever a free space exists in the pSRL as defined by (W-C) = (m-n), the control FSM performs a load cycle, and wherein when L=S=1, loading happens while shifts are going on. [0023] In an aspect, the pDWC is a k-bit pDWC with the control FSM being operatively coupled with either a large pSRL allowing m and n to be integral multiples of k, or being operatively coupled to control k single-bit pSRLs in parallel. [0024] In an aspect, the pDWC requires a minimum or exactly equal to k × (M+N) number of flops. In another aspect, the pDWC has a width that is a greater than or exactly equal to k × (M+N) [0025] In an aspect, the pSR with programmable load location (pSRL) comprises a bit-re-mapper function that receives L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and based on n (n+1):1 multiplexers and pi’, outputs a load vector, wherein pi’ = (LL-1) when ((L = 1, S = 0) and (LL i)), else if (S = 1), pi’ = p + i, else pi’ = i. [0026] In an aspect, the pSRL receives the L (Load Control Signal), the S (Shift Control Signal), the LL (Load Location Control Signal), and the p (programmable shift value) from any or combination of a control Finite State Machine (FSM), a programmable logic device (PLD), or a software application. [0027] In an aspect, if L=1 and S =0, i = Di-LL if LL i min (n, (LL+m)), else i = di. In another aspect, if L=0 and S =1, i = di+p if i < (n-p), else i = 0. In yet another aspect, when L=1 and S =1, i = di+p if i n, only one load is required, else if m < n, multiple load cycles are required with S=0. In another aspect, the control FSM keeps a count C of bits that are currently in the pSRL, wherein each load increments the C by m such that when C = n has been loaded into the pSRL, the control FSM initiates a shift that shifts out n bits and decrements C by n. In yet another aspect, when a load and shift happen together, (m-n) is added to C, and wherein whenever a free space exists in the pSRL as defined by (W-C) = (m-n), the control FSM performs a load cycle, and wherein when L=S=1, loading happens while shifts are going on. [0069] In an aspect, the pDWC is a k-bit pDWC with the control FSM being operatively coupled with either a large pSRL allowing m and n to be integral multiples of k, or being operatively coupled to control k single-bit pSRLs in parallel. [0070] In an aspect, the pDWC requires a maximum of k × (M+N) number of flops. [0071] In an aspect, the pSR with programmable load location (pSRL) comprises a bit-remapper function that receives L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and based on n (n+1):1 multiplexers and pi’, outputs a load vector, wherein pi’ = (LL-1) when ((L = 1, S = 0) and (LL i)), else if (S = 1), pi’ = p + i, else pi’ = i. [0072] In an aspect, the pSRL receives the L (Load Control Signal), the S (Shift Control Signal), the LL (Load Location Control Signal), and the p (programmable shift value) from any or combination of a control Finite State Machine (FSM), a programmable logic device (PLD), or a software application. [0073] In an aspect, if L=1 and S=0, i = Di-LL if LL i min (n, (LL+m)), else i = di. In another aspect, if L=0 and S =1, i = di+p if i < (n-p), else i = 0. In yet another aspect, when L=1 and S =1, i = di+p if i 1, then loading happens to the left of bit 1 and d1 stays uninvolved. This is a total of (n + 1) values. • Similarly, bit 2 could get its own value, one of (n – 2) bits to its left or only bits 1 and 2 of the load register (D1 or D2). It would get D1 if LL = 2, and it would get D2 if LL = 1. This is a total of (n + 1) values. • Continuing, bit 3 could get its own value, one of (n – 3) bits to its left or bits 1, 2 or 3 of the load register (D1, D2 or D3). It would get D1 if LL = 3, D2 if LL = 2 and D3 if LL = 1. Once again, this is a total of (n + 1) values. • Generically, bit r gets its own value, one of (n – r) bits to its left or one of r bits {1, 2, 3 … r} of the load register – D1, D2, D3 … Dr. It gets D1 if (LL = r), D2 if LL = (r – 1), D3 if LL = (r – 2) and so on. This is a total of (n + 1) values. Thus, in general bit r gets the value of bit D(r – LL + 1) if LL = r. If LL > r, then bit r either may either get a shifted value or hold its previous value. [0093] From above results it may be noted that, at most n (n + 1):1 multiplexers are needed for the implementation. The multiplexer size starts reducing from the (n – m + 1)th bit onwards because there are fewer bits on the left to choose from while shifting. The nth bit can only get its own value or one of m values from the load register, since it does not have bits on its left. [0094] FIG. 5B illustrates an exemplary implementation of the proposed loadable programmable shift register with programmable load location (pSRL), in accordance with an embodiment of the present disclosure. In an embodiment, FIG. 5B illustrates the proposed loadable programmable shift register with an additional input that defines where data is loaded (pSRL). [0095] It is to be appreciated that for the exemplary implementation purpose, D1, D2, D3 … etc. are connected in the reverse order of d2, d3, d4… etc, which enables a simple way of realizing the expression (r – LL + 1), since bit r will get the value of bit D(r – LL + 1) from the load register while loading. [0096] In an exemplary embodiment, in an implementation, the proposed pSRL focuses on the way pi’ is computed, wherein using the implementation as illustrated in FIG. 5C, for pi’ generation for the pSRL: p1’ is realized by: if ((L = 1, S = 0) and (LL = 1)) p1’ = (LL – 1) else if (S = 1) p1’ = p + 1 else p1’ = 1 if (L = 1, S = 0) and (LL = 3): LL p1’ selects 1 0 D3 2 1 D2 3 2 D1 else if (S = 1) p p1’ selects 1 4 d4 2 5 d5 3 6 d6 … … … else X 3 d3 p2’ is realized by if ((L = 1, S = 0) and (LL = 2)) p2’ = (LL – 1) else if (S = 1) p2’ = p + 2 else p2’ = 2 if (L = 1, S = 0) and (LL = 2): LL p2’ selects 1 0 D2 2 1 D1 else if (S = 1) p p2’ selects 1 3 d3 2 4 d4 3 5 d5 … … … else X 2 d2 p3’ is realized by: if ((L = 1, S = 0) and (LL = 3)) p3’ = (LL – 1) else if (S = 1) p3’ = p + 3 else p3’ = 3 if (L = 1, S = 0) and (LL = 3): LL p3’ selects 1 0 D3 2 1 D2 3 2 D1 else if (S = 1) p p3’ selects 1 4 d4 2 5 d5 3 6 d6 … … … else X 3 d3 pi’ is realized by: if ((L = 1, S = 0) and (LL = i)) pi’ = (LL – 1) else if (S = 1) pi’ = p + i else pi’ = i if (L = 1, S = 0) and (LL = p): LL pi’ selects 1 0 Dp 2 1 Dp-1 3 2 Dp-2 … … … p p–1 D1 else if (S = 1) p pi’ selects 1 1+p dp+1 2 2+p dp+2 3 3+p dp+3 … … … else X p dp [0097] Thus, it may be noted form the above that, the n (n + 1):1 multiplexers and pi’ together defines the bit re-mapper function d, which is a complete solution for a pSRL. [0098] FIG. 5C illustrates an exemplary conceptual block diagram of the proposed loadable programmable shift register with programmable load location (pSRL) as illustrated in FIGs. 5A-B with a bit-remapper function (d) 594, in accordance with an embodiment of the present disclosure. The proposed loadable programmable shift register includes with an additional input that defines where data is loaded (pSRL). Considering the above analysis representations and analysis, FIG. 5C illustrates the block diagram of pSRL. As shown in FIG. 5C, the bit-mapper function d (also interchangeably referred to as bit-mapper d 594) receives a data (Din) from a load register having a data width (M) 592 along with at least one of control inputs 582 that control at least one of load location (LL) of data 584, loading (L) of data 584, shifting (S) of data 588, and a programmable shift value (p) 590. Based on which the data 596 is loaded in a register (not shown) to ultimately convert data received from the load register having a fixed data width (M) or variable data width (m) to the data 598 having a new fixed data width (N) or a new variable data width (n) based on the received output. It may be noted from the above that, FIG. 5C provides a generalized programmable shift register with programmable load location which serves as a storage. [0099] In an exemplary embodiment, the proposed loadable programmable shift register with programmable load location (pSRL) 580 is provided. The pSRL being configured to receive a programmable input LL 584 that defines where data D is to be loaded from the Load Register when L (Load Control Signal) = 1. [00100] In an exemplary embodiment, the pSR with programmable load location (pSRL) includes a bit-remapper d 594 function that receives L (Load Control Signal) 586, S (Shift Control Signal) 588, LL (Load Location Control Signal) 584, and p (programmable shift value 590, and based on n (n+1):1 multiplexers and pi’, outputs a load vector, wherein pi’ = (LL-1) when ((L = 1, S = 0) and (LL = i)), else if (S = 1), pi’ = p + i, else pi’ = i. [00101] In an exemplary embodiment, the pSRL receives the L (Load Control Signal), the S (Shift Control Signal), the LL (Load Location Control Signal), and the p (programmable shift value) from a control Finite State Machine (FSM). [00102] In an exemplary embodiment, if L=1 and S=0, i = Di-LL if LL i min (n, (LL+m)), else i = di. In another aspect, if L=0 and S=1, i = di+p if i < (n-p), else i = 0. In yet another aspect, if L=1 and S =1, i = di+p if i 8. In cycle 0, the FSM loads one 7-bit word into the pSRL. This is loaded at LL = 1. In cycle 1, the FSM initiates a load with L = 1 and also initiates a shift with S = 1. The FSM computes that (W – C) = 8, and (m – n) = 2 which is lesser, so it initiates a load. The FSM computes that C = 7, which is greater than n, which is 5. In cycle 2, after one shift and one load, C increases to 9, and the free space decreases by 2 to 6, but this is still greater than (m – n), which is 2, so the FSM performs a load. Since the bit count C = 9 is greater than the number of bits to be shifted out n = 5, the FSM also performs a shift. This state allows for concurrent load and shift again.… (Cycles 3 and 4 are similar) In cycle 5, C increases to 15. The free space decreases to 0, which is less than (m – n), which is 2, so the FSM cannot perform a load. Since the bit count C = 15 is greater than the number of bits to be shifted out n = 5, the FSM does perform a shift. In cycle 6, (W – C) = 5, which is more than (m – n), which is 2; so L = 1. There are enough bits to shift: (C > n), so S = 1. In cycle 7, (W – C) = 3, which is more than (m – n), which is 2; so L = 1. There are enough bits to shift: (C > n), so S = 1. In cycle 8, (W – C) reduces to 1; which prevents a load. There are enough bits for a shift so the FSM does initiate a shift. This is the second cycle in which there is a shift but no load. In cycle 9, the state of data in the pSRL is the same as it was in cycle 2 and after this, things repeat in this 7-cycle loop. In 7 cycles, there are exactly 5 loads of 7 bits and 7 shifts of 5 bits for a transfer of 35 bits. FIG. 8A illustrates that in 7 cycles, there are 5 loads (of 7 bits each) and 7 shifts (of 5 bits each). The dark colored boxes show how 8 bits are actually loaded and how the eighth bit of the previous load is discarded when a new 7-bit word is loaded. Example 2: pDWC for m = 5, n = 7 Let’s assume that M = 8 and N = 7 Thus, the pSRL is configured with a width of 15. (W = 15) Load register width = 8; d width = 15. Naturally, some bits of the load register will be discarded when LL > 10. In cycle 0 and cycle 1, the FSM loads two 5-bit words into the pSRL. The first one is loaded at LL = 1, and the second at LL = 1 + m = 6. Two 5-bit words are needed since n = 7. In cycle 2, the FSM initiates shifts with S = 1. The FSM computes that C = 10 in this cycle since in cycle 1, C = 5, L = 1 and S = 0. Since C > n, a shift is initiated. However, since (W – C) = 5, and this is greater than (m – n) = –2, a load is simultaneously initiated as well. In cycle 3, after a simultaneous load and shift, C = 10 + 5 – 7 = 8, and the free space is 15 – 8 = 7. This is greater than (m – n), which is –2, so the FSM performs a load. Since the bit count C = 8 is greater than the number of bits to be shifted out n = 5, the FSM also performs a shift. Note: Since (m – n) = –2, there never will be a condition when (W – C) is less than this; therefore on every clock, the FSM will perform a load. In cycle 4, after a concurrent shift and load, the bit count C increases by (m – n) = -2 to become 6. At this point (W – C) = 9, which is still greater than (m – n) which is -2; so the FSM does a load. However, since C < n, (6 < 7), the FSM does not initiate a shift. Continuing, in cycle 5, C increases to 11, (W – C) = 4 and (m – n) = -2, so L = 1. Also C > n, so S = 1. Thus, cycle 5 also has concurrent load and shift.… (Cycles 6 and 7 are similar). This continues until cycle 8, which also has a load but no shift. The state of data in the pSRL is the same in cycle 9 as it was in cycle 2. After this, things repeat in this 7-cycle loop. In 7 cycles, there are exactly 7 loads of 5 bits and 5 shifts of 7 bits for a transfer of 35 bits. FIG. 8B illustrates there are 7 loads (of 5 bits each) and 5 shifts (of 7 bits each). FIG. 8B shows how 8 bits are actually loaded and how the leftmost three bits of the previous load are discarded when a new 5-bit word is loaded. [00118] FIG. 9 illustrates an exemplary block diagram of a multi-bit programmable data width converter (pDWC). In an embodiment, a multi-bit pDWC is required when, instead of single bits, operation of a pDWC is in bit multiples, for instance, when one wants to write m bytes at a time and read out n bytes at a time, wherein, in the implementation of FIG. 9, k = 8. [00119] In exemplary implementation, a proposed system can incorporate a pDWC with byte (8-bit) operation, which multi-bit operation is often required in protocol framers and de-framers. JESD204B Transport Layer Framer/De-Framer can be an example for the requirements of multi-bit pDWC. JESD204B needs pDWC operation in terms of “samples” that could be upto 32 bits. In an example, when one application requires M = N = 64 samples, each sample can be defined to be 32 bits. In another example, the number of sample bits can be referred to as ‘k’. [00120] In an exemplary embodiment, it is possible to implement a k-bit pDWC by simply using a large pSRL and allowing m and n to only be an integral multiple of the word size k. But another solution can be to operate k single-bit pSRLs in parallel with a single control FSM controlling all pSRLs in lock step as illustrated in FIG. 9. This needs no more than (k × (M + N)) flops to implement. As illustrated in FIG. 9, the input is m words in and n words out of pDWC wherein the word size is k bits. [00121] FIG. 10 illustrates an exemplary method performed by the proposed programmable data width converter (pDWC), in accordance with an embodiment of the present invention. In an embodiment, FIG. 10 illustrates a method for programmably converting width of m k-bit word input into n k-bit word output by a programmable data width converter (pDWC). [00122] At step 1002, a control Finite State Machine (FSM) receives input values of m and n. [00123] At step 1004, any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) is controlled by the FSM based on the received values of m and n. [00124] At step 1006, width of ‘m’ k-bit word input to ‘n’ k-bit word output, and wherein 1 = m = M and 1 = n = N is programmably converted by the pDWC. [00125] At step 1008, loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM are performed by a loadable programmable shift register with programmable load location (pSRL). In an embodiment, the loadable programmable shift register with programmable load location (pSRL) is operatively coupled with the control FSM. [00126] Although the proposed system has been elaborated as above to include all the main modules, it is completely possible that actual implementations may include only a part of the proposed modules or a combination of those or a division of those into sub-modules in various combinations across multiple devices that can be operatively coupled with each other, including in the cloud. Further the modules can be configured in any sequence to achieve objectives elaborated. Also, it can be appreciated that proposed system can be configured in a computing device or across a plurality of computing devices operatively connected with each other, wherein the computing devices can be any of a computer, a laptop, a smartphone, an Internet enabled mobile device and the like. All such modifications and embodiments are completely within the scope of the present disclosure. [00127] As used herein, and unless the context dictates otherwise, the term “coupled to” is intended to include both direct coupling (in which two elements that are coupled to each other or in contact each other) and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms “coupled to” and “coupled with” are used synonymously. Within the context of this document terms “coupled to” and “coupled with” are also used euphemistically to mean “communicatively coupled with” over a network, where two or more devices are able to exchange data with each other over the network, possibly via one or more intermediary device. [00128] Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. [00129] While some embodiments of the present disclosure have been illustrated and described, those are completely exemplary in nature. The disclosure is not limited to the embodiments as elaborated herein only and it would be apparent to those skilled in the art that numerous modifications besides those already described are possible without departing from the inventive concepts herein. All such modifications, changes, variations, substitutions, and equivalents are completely within the scope of the present disclosure. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. TECHNICAL ADVANTAGES OF pDWC: [00130] The present disclosure provides a pDWC that allows reading of an n-bit output word as soon as it becomes available, which achieves the lowest theoretically possible latency. [00131] The present disclosure provides a pDWC that is implementable in (M + N) bits of storage, (M + N) (N + 1):1 multiplexers and some gates to generate pi’ in addition to a few flops and gates to implement the control FSM. [00132] The present disclosure provides a pDWC that enables achievement of high performance due to highly optimized structural implementation and can operate at high speed. [00133] The present disclosure provides a pDWC that is scalable in nature such that the pDWC scales linearly, making large values of W (size of pDWC) possible. [00134] The present disclosure provides a FSM, size of which does not increase significantly even if M, N, and k become very large, and therefore size of FSM stays a very small part of the overall size.