The present invention relates to a programmable logic control circuit of an electrical installation, in particular a nuclear installation, the programmable logic circuit comprising a functional unit comprising:
- a plurality of types of functional blocks, two distinct functional blocks being adapted to perform at least one separate function,
- at least one own processing module for receiving at least a block sequence (s) function (s) to be executed, and

- at least an internal memory configured to store at least said sequence.

Furthermore, the present invention also relates to a control device for an electrical installation, in particular a nuclear installation, the control device comprising at least such a programmable logic circuit.

In addition, the present invention also relates to a method for controlling an electrical system, implemented, at least in part by the control device of said electric installation.

It is known from EP 2988420 A1 a power plant control system based on an electronic board with two programmable logic devices (FPGAs English Field Programmable Gate Array).

A first FPGA acts as a master and comprises a set of functional units comprising as many functional blocks of the same type, e.g., "AND" type, the number of instances of this type of block for a given application controller control a nuclear facility. The second FPGA is connected point to point to the inputs and output of the first FPGA and acts as a physical connection matrix of the functional blocks of the first FPGA.

At each change of the command and control application in question or if the command control application changes, reprogramming VHDL hardware description language (English very high speed integrated circuit (VHSIC) hardware description language (DLJ ) or Verilog and requalification of the second FPGA connecting the functional blocks to each other is required.

Indeed in the context of control command nuclear installation, each FPGA design must be described very carefully by using complex processes of development and verification.

Such reprogramming stage language hardware description, Verilog or VHDL for example, requires the operator knowledge of this language, and requalification requires time and verification efforts.

In order to overcome these drawbacks a solution is described in EP 3107212 A1 and based on the FPGA implementation also comprising a set of functional blocks executed in parallel in successive cycles to obtain the result of a given application control command of a nuclear installation. According to this solution the FPGA circuit comprises at least as many functional blocks of the same type as the number of instances of that block type. In addition, in this document, a data conveyor permits the transit of binary and analog values ​​between the functional blocks each having a specific architecture to extract them respectively of the conveyor and to transmit to the conveyor their input and output data .

However, this solution requires a number of functional blocks of the same large type and defined empirically from experience in control system design control of nuclear facility. Furthermore, parallel execution of the functional blocks during several successive cycles required to obtain the result associated with an application, requires the implementation of a synchronization, including delay means (s), so as to ensure determinism of information transmitted between each functional block and between each cycle.

The object of the invention is therefore to provide an alternative solution for monitoring control of nuclear installation based on programmable logic implementation for which, in case of command control application changes, reprogramming in VHDL or requalification of the processing module is avoided, while reducing the number of logical resources used and while responding simply to deterministic safety demonstration requirements for a safety device, such as a control device a nuclear facility.

To this end, the invention relates to a programmable logic circuit of the aforementioned type, wherein the programmable logic circuit comprises a single functional block of each type, the same functional block being adapted to be called multiple times, and a module execution configured to run in series or block (s) function (s) called according to said sequence.

The programmable logic device of the invention then significantly reduces the number of logical resources and therefore the size and power consumption of programmable logic circuit while ensuring the determinism of the command and control application with serial execution functional blocks called according to their sequence (ie order) of execution during a single cycle (a cycle corresponding to a time during which the input data of the programmable logic circuit are fixed in memory and will be reassessed at next cycle). In other words, according to the present invention, one cycle, corresponding to the execution of the series of function blocks listed in the sequence, is required to obtain the result of

According to other advantageous aspects of the invention, the programmable logic circuit includes one or more of the following characteristics, taken individually or in all technically possible combinations:

- the programmable logic circuit of FPGA;

- the runtime is a state machine;

the functional unit further comprises a plurality of computing units parallelizable floating point;

- at least one processing module is adapted to receive an application program corresponding to a group of configuration of computer files including said sequence and at least one other computer file belonging to the group comprising:

- a memory configuration file corresponding to a table associating at least one input / output signal of the programmable logic circuit in an address memory,

- a value file (s) parameter (s) block (s) function (s) own (s) to perform at least one function using a parameter,

- a file that lists, for each functional block, or the address (es) of the allocated memory (s) to one or more inlet (s) of this functional block,

- a file that lists, for each functional block, or the address (es) of the allocated memory (s) to or output (s) of the functional block;

- the parameter values ​​are ordered (s) within their file based on said block sequence (s) function (s) to be performed;

- the memory comprises at least two data storage areas respectively dedicated to binary data to analog data;

- each storage space comprises at least three dedicated sub-areas:

- at least a sub-area dedicated to data inputs of the programmable logic circuit,

- at least a sub-area dedicated to data outputs of the programmable logic circuit,

- at least a sub-area dedicated to temporary data obtained during execution of said sequence;

- the sub-areas dedicated to input or sub-areas dedicated to the output data are latch registers (s) synchronous (s).

The invention also relates to a control device as defined above.

According to other advantageous aspects of the invention, the control device includes one or more of the following characteristics, taken individually or in all technically possible combinations:

- the control device comprises a plurality of programmable logic circuits of the aforementioned type;

- the control device further comprises:

- at least a supply module,

- auxiliary modules among one or more modules dedicated to the acquisition of different input data, one or more modules dedicated to the publication of separate output data, and one or more maintenance and diagnostic modules, and

- a communication bus configured to connect the one or more circuit (s) logic (s) Programmable (s) for auxiliary modules;

- the communication bus comprises four low voltage differential transmission links (M-LVDS) respectively dedicated to the input data and output data of each programmable logic circuit for each direction of transmission;

- the control device comprises an optical fiber communication network configured to connect the plurality of programmable logic circuits.

- control device wherein a programmable logic master circuit, among the plurality of programmable logic circuits, is adapted to be connected to a timer and is configured to synchronize other programmable logic circuits of the plurality of programmable logic circuits through the network optical fiber communication;

- control device wherein the master programmable logic circuit is further configured to synchronize the auxiliary modules through the communication bus;

- control device wherein the plurality of programmable logic circuits is accommodated in a same housing.

- control device wherein the programmable logic circuits (the plurality of programmable logic circuits are separated in at least two separate housing.

The invention also relates to a method for controlling an electrical system, implemented, at least in part by the control device for an electrical installation comprising a programmable logic circuit comprising a functional unit comprising:

- a plurality of types of functional blocks, two distinct functional blocks being adapted to perform at least one separate function,

- at least one own processing module for receiving at least a block sequence (s) function (s) to be executed,

at least one memory configured to store at least said sequence,

the programmable logic circuit comprising a single functional block of each type, the same functional block being adapted to be called multiple times, and comprising an execution module configured to execute in series or block (s) function (s) called ( s) in said sequence,

the method comprising at least:

- receiving at least a block sequence (s) function (s) to be executed,

- executing a series of or block (s) function (s) called (s) in said sequence.

According to other advantageous aspects of the invention, the control method includes one or more of the following characteristics, taken individually or in all technically possible combinations:

- implementation of the method is distributed on several separate bodies namely an application program generator of a maintenance center, and the aforementioned type control device comprising at least one maintenance and diagnostic module and at least one circuit programmable logic of the aforementioned type;

- the method further comprising:

the programming of the functional blocks or circuit (s) logic (s) Programmable (s),

the development of a library file describing the characteristics of functions that can be implemented by each functional block as programmed, and storing said library file in a memory of an application program generator;

developing functional diagrams representing a command control application of the electrical installation using a graphical editor connected to the application program generator,

data conversion block diagrams by the application program generator into at least one sequence of functional blocks to be executed, each functional block of the sequence by implementing the functions in accordance with those previously programmed and listed in the library file,

the connection of the application program generator to the control device of an electrical installation by a maintenance and diagnostic module,

loading at least the sequence of functional blocks to be executed in the control device.

- the library file comprises, for each scheduled function block:

son type,

the description of at least one function that is specific to implement its identifier corresponding to a predetermined hardware description language code,

its number and / or kind of entries,

its number and / or kind of outlet,

its number and / or kind of parameter (s) that is suitable for use. These features and advantages of the invention will become apparent from reading the description which follows, given by way of example, and with reference to the accompanying drawings, wherein:

- Figure 1 is a schematic representation of a programmable logic circuit according to the invention;

- Figure 2 is a view illustrating an example of control application command to be executed;

- Figure 3 is a schematic representation of the connection of the programmable logic circuit according to the invention to a maintenance and diagnostic module;

- Figure 4 is a schematic representation of a control device according to the invention comprising, according to one embodiment, the programmable logic circuit of Figure 1;

- Figures 5 and 6 show two variants of control devices comprising a plurality of programmable logic circuits shown in FIG 1.

In Figure 1, the programmable logic circuit 10 is a processing module (PM English Processing Module). Specifically, the programmable logic circuit 10 is in the form of an electronic structure such as a programmable gate array, or FPGA (English Field-Programmable Gate Array).

Such FPGA 10 comprises a module 12 for control of the input signals, a functional unit 14 (OPU English Operating Unit), and a module 16 of control output signals.

The functional unit 14 includes a plurality of 18 W types of functional blocks FB 1; ... FB ,, FB N distinct with an integer N and / ' the type of functional block index between one and N.

Two distinct types of function blocks are specific to perform at least one separate function. By "function" means individual functions to be implemented in an FPGA.

According to the present invention, the functional unit comprises a single functional block of each type.

Each functional block is otherwise qualified once and for all when designing the programmable logic circuit according to the present invention is subsequently only called to be executed at a command control application without any retraining is necessary in case of change / changing command control application.

Each block instance can also provide, if necessary, an internal storage space of a module dedicated 20 22 execution of the functional unit 14, for storing persistent values ​​of an execution cycle the other.

All the specific functions to be implemented in an FPGA according to the present invention are thus implemented (ie programmed according to a preliminary step) once and for all in VHDL. Their characteristics are listed by example and stored in a library file 100 stored in a memory, not shown, an automatic generator 1 10 of configuration data of a maintenance station 76 (shown in Figure 3) spaced and separate from the programmable logic circuit 10 according to the present invention.

In other words, the file library 100 describes characteristics of functions that can be implemented by each functional block as programmed.

Such a library file 100 includes, for example for each functional block:

- son type,

- description of at least one function that is able to implement,

- its identifier corresponding to a predetermined arbitrary code

- the number and / or kind of entries,

- the number and / or type of outputs

- the number and / or type of parameters it is clean to use.

Such a library file 100 is previously prepared and used by an automatic generator 1 10 of the maintenance center configuration data 76 to automatically translate a set of block diagrams 120 in the application program 34.

2 illustrates a block diagram 120 of an exemplary monitoring and control application to be executed. One such application is the limit temperature detection in four separate points of a nuclear reactor.

One such application is generated by an operator from a graphics editor connected to the automatic generator 1 10 of application program 34 without requiring special knowledge of Verilog or VHDL hardware description language.

The automatic generator 1 10 of application program 34 is adapted to convert the data of such a block diagram 120 by the generator 1 10 of application program 34 in at least a sequence 46 of functional blocks to be executed, each functional block in the sequence involving implement the functions consistent with those previously programmed and recorded in the library file 100.

Four types 24, 26, 28, 30 of separate functional blocks are required for the implementation control of control such application, namely four types LIN, THR, and VOTE AND which are graphically connected by directed links representing causal relationships between functional blocks.

More specifically, the operator graphically defines the number of monitoring the application of control input signals that is E1, E2, E3, and E4 which correspond, for example at different measuring points of a nuclear reactor.

According to this control application control, the electric signals Ei in (i = 1 to 4) are then each suitable for being converted by means of a LIN function block type in a physical datum, here a temperature.

Then, the temperature obtained at the output of functional block 24 LIN type is compared to a threshold temperature by means of a functional block 26 for THR type having this temperature threshold parameter namely, for example 100 ° C.

The command control application referred then comprises a voting function implemented by function block VOTE 28 applied to the four signals associated with each entry point. The voting function is for example a 2/4 vote function adapted to confirm or deny (ie binary result) comparing the temperature threshold, from the time at least two out of four comparisons the same result.

Finally, the command and control target application is adapted to take into account, by means of a functional block 30 AND, activation of a push button 32 (adapted to be manually actuated by an operator) Result inhibitor. In other words, the functional block 30 receives two AND logic inputs corresponding respectively to the output of function block 32 and the pushbutton 28 VOTE signals and outputs the result 33 binary function block VOTE if the pushbutton 32 n ' has not been operated, and the result 33 binary otherwise contrary.

Thus, for this example of command and control application, the library file 100 used by the automatic generator 1 10 is for example in the form of the following table:

Code Type Description function Input Output Settings arbitrai

re you

FB

LIN 0x01 linear 1 Conversion 1 none

an analog analog electrical signal in a given

physique

THR 0x02 comparison to a binary 1 1 1 Analog:

analogue threshold threshold value

VOTE 0x03 voting Function 2/4 4 1 binary bit no

0x04 AND Logic Function 2 1 bit binary no

"AND" between two

input

In connection with Figure 1, the FB ^ FB is e.g. LIN type and 0x01 code it is allocated on the FPGA, the functional block FB i = 5 is THR type and 0x02 code is allocated, the FB i = 12 is to VOTE type and code 0x03 is allocated, and the function block FB i = 18 is aND type and code 0x04 is allocated.

From the diagram shown in Figure 2, and the library file January 00 described above, a set of configuration data files forming an application program 34 is automatically generated.

Such an application program 34 includes:

a configuration file 36 from the memory 38 of the functional unit 14 corresponding to a table associating at least one input / output signal of the programmable logic circuit 1 a 0 address in its memory,

- a 40 value file (s) parameter (s) block (s) function (s) own (s) to perform at least one function using a parameter,

- a file listing 42 for each functional block, or the address (es) of the allocated memory (s) to one or more inlet (s) of this functional block,

- a file listing 44 for each functional block, or the address (es) of the allocated memory (s) to or output (s) of this functional block,

- a sequence 46 of block (s) function (s) to run

The memory 38 of the functional unit 14 comprises at least two spaces 48 and 50 respectively dedicated data storage to binary data (Boolean encoded on two separate bits) and analog data (coded floating-point numbers for example thirty-two bits). In a variant not shown, the memory 38 of the functional unit 14 further includes a data storage space dedicated to the values ​​of parameters of the file 40.

The space 48 of binary data storage is itself hierarchized into at least three sub-spaces, namely: a first subspace 52 dedicated to binary data inputs of the programmable logic circuit 1 0, a second subspace 54 dedicated to temporary binary data obtained by running the sequence 46, a third sub-area 56 dedicated to binary data outputs of the programmable logic circuit.

Similarly, the space 50 analog data storage itself is hierarchized into at least three sub-spaces, namely: a first subspace 58 dedicated to the analog input data of the programmable logic circuit 10, a second sub -space 60 dedicated to temporary analog data obtained during

execution of the sequence 46, a third sub-area 58 dedicated to analog data outputs of the programmable logic circuit.

The configuration file 36 from the memory 38 is configured to be read by the execution unit 22 of the functional unit 14 during a single execution cycle of the command and control application (corresponding for example to that shown in Figure 2).

During execution of the sequence 46, the execution module 22 reads the configuration file 36 which are stored in the memory 38 the values ​​of the inputs and outputs of the application as a whole.

In other words, the configuration file 36 is a table for allocating, in the different sub-spaces (ie registers) memory, memory addresses to the inputs and outputs of the programmable logic circuit 10.

The five input values ​​are, in the example command control application shown in Figure 2, four analog values ​​ina_E1, _ina_E2, ina_E3 and ina_E4 corresponding to electrical signals representative of temperature measurements respectively at points E1 to E4 and a representative inb_P1 binary value of the activation / deactivation of the push button 32.

The output value outb_ACT is issued after execution of the functional blocks in the sequence 46 of functional blocks.

Thus, for this example of control application control illustrated in Figure 2, the configuration file 36 is, for example, in the form of the following table:

According to the present invention, the sequence 46 of block (s) function (s) to be executed is a file that lists, from the causality of the diagram, the order of instantiation of the function blocks to be executed in series by the module execution 22 of the functional unit 14 to perform the desired command control application.

The sequence 46 is a computer file, for example, shown as the following ordered table:

In other words, according to the present invention a single functional block FB (the code is indicated in the library file described above) is executed at a time, according to the successive instances of the series of functional blocks shown in the computer file sequence 46 below -above.

Such a serial execution guarantees the determinism of execution of the command and control application since the output of each functional blocks of data are stored and / or fed back as input to the next functional block As instances.

According to the prior art to realize the application control command shown in FIG 2, it is necessary that the FPGA includes four functional blocks LIN type, four functional blocks type THR, a VOTE function block type and a block functional type AND totaling about ten separate functional blocks.

Rather, the present invention only one functional block of each type is required and "called" as many times as required by the control application command to execute. Thus, in relation to the application example of Figure 2, the number of functional blocks needed to run such an application is reduced from ten to four, allowing a reduction in the size of the FPGA (ie optimization of the compactness ) and / or the ability to incorporate callable function blocks for other monitoring and control applications.

In other words, the impression material (eg VHDL footprint) of the programmable logic circuit according to the invention is unique and permanent, a qualified functional block being adapted to be reused with a control application command to another. According to the invention, only the application program 34 is separate from a command control application to another, the same functional block being called for example in the first instance to a first command control application and ultimately to a second application of control command different from the first.

The 40 value computer file (s) parameter (s) functional block (s) comprises in turn the parameter values ​​required when executing the sequence 46, these parameter values ​​being ordered by taking into account the sequence 46 execution of the functional blocks.

The computer file 40 parameter values ​​is shown for example in the form of ordered following table:

In other words, for the example command control application shown in Figure 2, the same functional block FB i = 5 THR type is instantiated four times with the same parameter value that is a temperature of 100 ° vs.

According to other examples of command and control applications, different parameter values are adapted to be associated with the various instances of the function block FB i = 5 THR kind. Thus, without changing the hardware footprint (eg VHDL footprint), and accordingly without requalification of the programmable circuit, the present invention allows a change of parameter of the same function block during the life of a control system , or from one application to another. The evolution of operating the programmable circuit is facilitated.

Moreover, as indicated previously the application program 34 also includes two computer files listing 42 and 44 respectively for each function block on the one hand or the addresses of the memory 38 allocated (s) to one or more input operands of this functional block, and secondly the email address of the allocated memory (s) to one or more output of this function block operands.

In connection with the implementation shown in Figure 2, these two computer files 42 and 44 are, for example, respectively as follows:

Address (es) Name Used in address (es) Name of the input value memory Used entry: memory output value

0x0001 ina_E1 LIN output:

0x0800 wa_a1 THR 0x0800 wa_a1 LIN

0x0005 ina_E2 LIN 0x0804 wb_b1 THR

0x0805 wa_a2 THR 0x0805 wa_a2 LIN

0x0009 ina_E3 LIN 0x0809 wb_b2 THR

0x080A wa_a3 THR 0x080A wa_a3 LIN

0x0013 ina_E4 LIN 0x080 E wb_b3 THR

0x080F wa_a4 THR 0x080 F wa_a4 LIN

0x0804 wb_b1 VOTER 0x0813 wb_b4 THR

0x0809 wb_b2 VOTER 0x0814 wb_c VOTER

0x080E wb_b3 VOTER 0xF800 outb_ACT AND

0x0813 wb_b4 VOTER

0x0000 lnb_P1 AND

0x0814 wb_c AND

The execution module 22 then operates as a state machine and distributes and / or automatically stores each function block instance values ​​of input and output to the memory addresses listed in the files 42 and 44 of the application program 34.

A pointer allows the execution module 22 to know for each function block instance the starting location of the addresses of the input and output values ​​to read in the files 42 and 44. At the end of execution each function block instance, it updates the pointer to the number of read input values ​​and the number of output values ​​generated, allowing the execution module 22 of the addresses to read the file 42 44 and for the following block instance.

In other words, the computer files of the application program 34 have a synergistic effect so that the execution module 22 is configured to take into account all parallel to implement a serial execution without any link is physically created between the various functional blocks.

Thus, in connection with an example of control application control illustrated in Figure 2, the execution module 22 is configured to read the sequence 46 and determine the first functional block to execute.

The first block is the functional block FB type LIN, and the execution unit 22 is then configured to distribute it as input, according to the computer file 42 associated with the input data of each functional block, the analog value of ina_E1 which is stored at the address 0x0001 of the subspace 58 dedicated to analog data memory input 38.

The FB LIN type ^ is then executed and the analog value of wa_a1 outputted is stored at the address 0x0800 of the memory sub-space 60 dedicated to temporary analog data according to the computer file 44 associated with the output data of each function block.

Then, the execution module 22 is configured to read the sequence 46 and determine the second function block to execute. This second block is the functional block FB i = 5 THR type and code 0x02 is allocated to it on the FPGA card. The execution module 22 is then configured to distribute it into the value of wa_a1 which is stored at the address 0x0800 and the parameter value 100.0 is the next value on the stack analog parameter values.

The FB 5 THR type is then executed and the binary value of wb_b1 outputted is written and stored by the execution module 22 to 0x0804 address subspace 54 dedicated to temporary binary data.

Then, according to the sequence 46, the third functional block is to execute again the function block FB type LIN. At this second instance of the same function block FB type ^ LIN the execution module 22 is then configured to distribute it into the analog value of ina_E2 which is stored at the address 0x0005 of the subspace 58 dedicated to data analog memory input 38.

The FB LIN type ^ is then executed for the second time and the analog value of wa_a2 outputted is stored at the address 0x0805 of the memory sub-space 60 dedicated to temporary analog data, and so on up to that the whole sequence 46 is completely executed (ie until the stop code 0x00 is read by the execution module 22).

Thus, according to the present invention a single function block is executed at a time at a given time.

In the example shown in Figure 1, the functional unit 14 further includes a plurality 64 of M processing units in floating point (FPU standing for "floating point units") parallelizable, with M an integer.

Such processing units are for example adapted to implement square root calculations or logarithm and are parallelized for implementation of complex calculations required during the execution of a functional block such as determining the ratio between the thermal flux of appearance of the boiling crisis and the actual heat flow in the heart of a reactor called report critical heat flux / RFTC (English DBNR Departure from nucleate boiling ratio). Such pool of computing units floating point is shared for all functional blocks of the functional unit 14 and accelerates the computing capacity of a function block when the latter is configured to calculate a complex analog.

The functional unit 14 also includes a clean output input interface 66 to receive and transmit respectively the ina_E1 input data ina_E2, ina_E3, ina_E4 and inb_P1 output and outb_ACT listed in the configuration file 36, and associated with the command and control application as a whole.

The interface 66 is adapted to receive the application program 34 via an internal configuration bus (ICB English Internai Configuration Bus) connected to the module 12 for control of the input signals and to transmit data through the same data bus control and diagnostic module 16 of control output signals.

The module 12 for control of the input signals as the module 16 of control output signals are external to the functional unit 14 and are adapted to communicate with devices and / or external circuitry to the programmable logic circuit 10.

The signal control module input 12 and output signals from the control module 16 are themselves each a state machine comprising one or more memory spaces dedicated respectively to unrepresented analog and binary data.

These dedicated memory spaces, some of which are dedicated to the control of input and output data exchanged with a communication network and adapted to receive / transmit data transmitted / transmitted asynchronously with respect to the operating cycle of the programmable logic circuit 10 . to do this, these memory spaces dedicated to data networks specifically are latch registers (s) synchronous (s) (ie dual port English flip-flop) so as to store network data received / transmitted cycle during current while the network data received / transmitted in the previous cycle is used by the functional unit 14 during the current cycle. The programmable logic circuit 10 has thus a number of optical fiber connectors allowing to

The modules 12 and 16 are particularly configured to provide communication with a 68 maintenance and diagnostic module (SMD English Service Maintenance Diagnosis Module) shown in Figure 3.

Such maintenance and diagnostic module 68 serves in particular to load, on the programmable logic circuit 10, the application program 34 associated with the application to run or changes in functional block parameters (eg a temperature threshold changing 100 ° C to 120 ° C), to periodically initiate maintenance tests on the programmable logic circuit 10, or to transfer the programmable logic circuit 10 according to the invention the maintenance and diagnostic module 68 of data processing. This exchange of data between the programmable logic circuit 10 and the maintenance and diagnostic module 68 are secured by means of a connection such as a bus 70 connected to the rear face (the

The maintenance and diagnostic module 68 also comprises a programmable logic circuit 72, for example, FPGA and a microprocessor 74, and is adapted to communicate in a secure fashion with a maintenance station 76 comprising, for example, the automatic generator 1 10, by means of a link 78 such as Ethernet and a switch 80 adapted to communicate with other electrical installation control devices, a control device comprising at least one programmable logic circuit 10 according to the invention as described above.

The maintenance center 76 is, for example, remote nuclear power plant in which the programmable logic circuit 10 is implemented. Within this central maintenance 76, a maintenance operator carries out using a graphical editor (requiring no prior knowledge of VHDL or Verilog) the monitoring and control application to be implemented within the system nuclear power in the form of block diagrams 120 as shown for example in Figure 2. as indicated above, the block diagrams 120 are then converted into the application program 34, by the automatic generator 1 10 which uses the library file 100 to ensure that the application program 34 s'

Three variants of architectures of such a controller 81 are respectively shown in Figures 4 to 6.

In Figure 4, the controller 81 is "mono-" programmable logic circuit 10. In other words, the controller 81 includes a housing 82 (the rack English) forming the housing, for example of size 61 ) (U is the unit of height of a rack), wherein a single programmable logic circuit 10 is integrated. The housing 82 is adapted to further comprise a supply module 84, and auxiliary modules, namely one or more modules 86 dedicated to the acquisition of different input data, and 88 or modules dedicated to the publication separate data output, and one or more maintenance modules and diagnostic 68 previously described. Furthermore, the programmable logic circuit 10 includes connectors (e.g. seven connectors not shown) for,

A connection of the automatic generator 1 10 of the application program 34 to the control device 81 is adapted to be established via the one or more maintenance modules and diagnostic 68, which is in particular configured to load the sequence 46 of functional blocks to be executed in device control 81 once such connection is established.

Within the housing 82, the programmable logic circuit 10 is the master and controls communication with the auxiliary modules 86, 88, and 68 through a bus 70 using, for example non-limiting low voltage differential transmission links (M-LVDS English-Multipoint Low Voltage Differential Signaling), operating for example at 50MHz, and respectively dedicated to binary and analog input data and the binary and analog data output of the programmable logic circuit 10. Advantageously, each data type ( input or output) has an independent transmission path for binary data and analog data. In the cases so that makes four differential low-voltage transmission links.

Many unrepresented embodiments may be implemented without departing from the scope of the invention. For example 86 modules dedicated to the acquisition of the input data, and 88 modules dedicated to the publication of the output data may be accommodated on a single electronic card of the type "GPIO" (English-General purpose input output ) otherwise known.

The power supply module 84 supplies a stabilized power supply to the other modules of the housing 82 and is also configured to implement a voltage conversion, for example 24 volts DC to 5 volts for feeding each module housing 82.

Figures 5 and 6 show two variants of control devices 81 comprising a plurality of programmable logic circuits 10 shown in FIG 1.

Such architecture "multi" programmable logic devices 10 can increase the number of controller per network interface, duplicate control control operations in at least two programmable logic circuits 10 for security screening purposes imposing redundancy rules, or optimize the inter-module routing within a housing 82.

In such an architecture "multi" programmable logic circuits 10, the plurality of programmable logic circuitry 10 is synchronized, the synchronization is achieved through a master logic circuit 10a among the programmable logic circuitry 10, connected to a clock.

The programmable master 10a logic circuit is especially adapted to transmit, via the signal control module 12 shown in FIG 1, a start synchronization pulse and / or the end of the cycle (a cycle having for example a duration of 2 ms) and a status request to module 86 dedicated to separate input data, the 88 modules dedicated to distinct output data, or to other programmable logic circuitry 10 to synchronize and refresh each cycle the data input / output of the next cycle (new iteration of the command and control application). Therefore, contrary to trade via communication networks, these data exchange within a plurality of programmable logic circuits are made on a synchronous mode.

Thus, all programmable logic circuits 10 of the plurality are configured to operate simultaneously within the same cycle.

Two non-limiting variations of such architecture "multi" programmable logic circuits 10, are shown in Figures 5 and 6 for illustration.

In Figure 5, three programmable logic circuit comprising a programmable logic circuit master 10a and the other two programmable logic circuits 10, are housed in the same housing 82, programmable logic circuits 10 and 10a, being adapted to communicate with each other and auxiliary modules 86, 88, 68 of the housing 82 synchronously. In the embodiment shown by Figure 5 the programmable logic circuits 10a and 10 communicate with one another synchronously with optical fiber 92, the connectors being specifically dedicated to this logical inter-system programmable communication architecture within a "multi "-Circuits. Furthermore, the programmable logic circuit 10a master communicates synchronously with the auxiliary modules 86, 88, 68 of the housing 82 via the bus 70.

In Figure 6, a control device architecture 81 "multi" programmable logic circuit 10a and 10, and "multi" housing 90A, 90B, 90C is shown. According to this multi-system architecture, multi-housing, each housing 90A, 90B, 90C corresponds to an arrangement described in Figure 4 (Single-Circuit) or Figure 5 (Multi-Circuit).

Each unit may comprise further auxiliary modules 86, 88, 68.

Preferably, a housing 90A is "master" and includes the master programmable logic circuit 10a for all programmable logic circuits 10 of the 81 multi-circuit control device and multi-housing, and providing synchronization of auxiliary modules 86 , 88, 68 of the housing through the bus 70A.

Programmable logic circuits 10 of the controller 81 are adapted to communicate with a housing to each other and within the same synchronously housing optical fiber 92.

Each housing 90B, 90C "slave" of the master housing 90A includes among its programmable logic circuits 10 a programmable logic circuit sychonisationl Ob to synchronize the auxiliary modules 86, 88, 68 of the housing through the bus 70B, 70C Property

In the embodiments of Figures 5 and 6, and without this being a limitation of the scope of the invention, a single maintenance and diagnostic module 68 is implemented by controller 81 irrespective of the number of circuit (s) logic (s) programmable (s) 10 or the number of housing (s) it comprises.

In the embodiments of Figures 5 and 6, and without this being a limitation of the scope of the invention, only the master programmable logic circuit 10a and the programmable logic circuit 10b are connected to auxiliary synchronization modules 86, 88 , 68 of their respective housings 90A, 90B, 90C through their respective buses 70A, 70B, 70C. Other programmable logic circuits 10 of a housing are connected to the auxiliary modules 86, 88, 68 from their housing by the intermediary, respectively, of the programmable logic circuit 10a or 10b master timing of the programmable logic circuit, and the fiber grating optics 92. in this configuration, a bus 70A, 70B, 70C advantageously comprises four low voltage differential transmission links (M-LVDS of English-Multipoint Low Voltage Differential Signaling), operating for example at 50MHz. in each direction of transmission.

In another embodiment not shown, the buses 70A, 70B, 70C may be sized to enable each programmable logic circuit 10 to be

connected to the auxiliary modules 86, 88, 68 of the housing through the bus 70A, 70B, 70C.

CLAIMS
1. programmable logic circuit (10) for controlling an electric installation, in particular a nuclear installation, the programmable logic circuit comprising a functional unit (14) comprising:

- a plurality of types of function blocks (FB 1, FB ,, FB N ), two distinct functional blocks being adapted to perform at least one separate function,

- at least one own processing module for receiving at least one block (46) block (s) function (s) to be executed,

- at least one memory (38) internally configured to store at least said sequence (46)

characterized in that the programmable logic circuit comprises a single functional block of each type, the same functional block being adapted to be called multiple times, and an execution module (22) configured to execute in series or block (s) function (s) called (s) in said sequence (46).

2. The programmable logic circuit (10) according to claim 1, wherein the programmable logic circuit (10) is of FPGA.

3. The programmable logic circuit (10) according to claim 1 or 2, wherein the execution unit (22) is a state machine.

4. The programmable logic circuit (10) according to any preceding claim, wherein the functional unit (14) further comprises a plurality (64) computing units floating point (FPU) parallelizable.

5. The programmable logic circuit (PM) according to any preceding claim, wherein at least one processing module is adapted to receive an application program (34) corresponding to a group of configuration of computer files including said sequence and at least another computer file belonging to the group comprising:

- a configuration file (36) of the memory (38) corresponding to a table associating at least one input / output signal of the programmable logic circuit (MP) an address in its memory (38),

- a file (40) value (s) parameter (s) block (s) function (s) own (s) to perform at least one function using a parameter,

- a file (42) listing, for each functional block, or the address (es) of the allocated memory (s) to one or more inlet (s) of this functional block,

- a file (44) listing, for each functional block, or the address (es) of the allocated memory (s) to or output (s) of this functional block.

6. The programmable logic circuit (PM) according to claim 5, wherein the parameter values ​​are ordered (s) within their file (40) according to said block sequence (s) function (s) to execute.

7. The programmable logic circuit (PM) according to any preceding claim, wherein the memory (38) comprises at least two spaces (48, 50) data storage dedicated respectively to binary data and analog data.

8. The programmable logic circuit (PM) according to claim 7, wherein each space (48, 50) for storing comprises at least three dedicated sub-areas:

- at least one sub-space (52,58) dedicated to the input data of the programmable logic circuit (10),

- at least one sub-space (56,62) dedicated to data outputs of the programmable logic circuit (10),

- at least one sub-space (54,60) dedicated to temporary data obtained during execution of said sequence (46).

9. A programmable logic circuit (PM) according to claim 8, wherein the sub-spaces (52, 58) dedicated to the input data or the dedicated sub-spaces (56, 62) to the output data latch registers are (s) synchronous (s).

10. A control device for an electrical installation, in particular a nuclear installation, characterized in that the control device comprises at least one programmable logic circuit (10) according to any one of the preceding claims 1 to 9.

January 1. A control apparatus of an electrical installation according to claim 10, wherein the control device comprises a plurality of programmable logic circuits (10) according to any one of the preceding claims 1 to 9.

12. A control apparatus of an electrical installation according to claims 10 or 1 1 further comprising:

- at least one power module (84),

- auxiliary modules among one or more modules (86) dedicated to the acquisition of different input data, one or more modules (88) dedicated to the publication of separate output data, and one or more maintenance modules and diagnosis (68), and

- a communication bus (70) configured to connect the one or more circuit (s) logic (s) Programmable (s) (10) to the auxiliary module (86, 88, 68).

13. A control apparatus of an electrical installation according to claim

12 wherein the communication bus (70) comprises four low voltage differential transmission links (M-LVDS) respectively dedicated to the input data and output data of each programmable logic circuit (10) in each transmission direction.

14. A control apparatus of an electrical installation according to any one of claims 1 1 to 13, comprising an optical fiber communications network (92) configured to connect the plurality of programmable logic circuits (10).

15. A control apparatus of an electrical installation according to any one of claims 1 1 to 14, wherein a master programmable logic circuit (10a) of the plurality of programmable logic circuits (10) is adapted to be connected to a clock and is configured to synchronize other programmable logic circuits of the plurality of programmable logic circuits (10) through the optical fiber communication network (92).

16. A control apparatus of an electrical installation according to claim 15, wherein the master programmable logic circuit (10a) is further configured to synchronize the auxiliary modules through the communication bus (70).

17. A control apparatus of an electrical installation according to any one of claims 1 1 to 16, wherein the plurality of programmable logic circuits (10, 10a, 10b) is accommodated in a same housing (82).

18. A control apparatus of an electrical installation according to any one of claims 1 1 to 17, wherein the programmable logic circuits (10, 10a, 10b) of the plurality of programmable logic circuits are separated in at least two separate housing (90 A , 90 B, 90 c ).