PROGRAMMABLE LOGIC DEVICES PROVIDING REDUCED POWER
CONSUMPTION
BACKGROUND OF THE INVENTION
1. Field of Invention:
This invention relates to Programmable Logic Devices providing reduced power consumption for a given system performance.
2. Description of the Prior art:
Programmable Logic Devices (PLDs) are semi-custom devices containing a fixed set of logic structures which may be interconnected in several different ways to achieve a desired logic function. PLDs generally include an array of Programmable Logic Blocks (PLBs). A PLB may also be called a Configurable Logic Block (CLB) or a Configurable Logic Element (CLE) or Programmable Function Unit (PFU). Each PLB is a programmable logic circuit comprising one or more input lines, one or more output lines, one or more latches and one or more Look-Up Tables (LUTs) alongwith sequential logic elements. Each LUT can be programmed to perform various functions including general combinatorial or control logic, or to operate as a Read Only Memory (ROM), Random Access Memory (RAM) or as a data path between input and output lines. In this manner, the LUT determines whether the PLB performs general logic, or operates in a special mode such as an adder, a subtracter, a counter, a register or a memory cell.
As the size and speed of PLDs increase, the power consumption also increases. The device architecture directly affects the power efficiency which can be expected in any design. PLDs generally use low power technologies such as CMOS technology. However in high density PLDs the power consumption issue becomes a limiting factor inspite of the low-power technology used. This results in the limitation that all the resources (logic blocks / routing etc) of the device cannot be used at the maximum speed owing to excessive temperature rise. The power consumption of the device also directly affects reliability and cost. Almost all power consumption in PLDs is dynamic power, the result of charging and discharging of internal and external capacitance. One of the main ingredients of dynamic power consumption in PLDs is clock distribution power. High speed switching in clock distribution results in considerably higher power consumption. Thus, it is safe to operate a PLD device at lower speed with a low cost package without any heat sink, however at high speed the

reliability of the device can be sustained only by using expensive packages sometimes together with a heat sink.
Sequential logic elements and data storage circuit elements including memory cells incorporate edge-triggered flip-flops as the basic building block. These flip-flops, being edge-triggered, operate on only a specific edge of the clock signal. The remaining edge of the clock signal does not produce any circuit action. However, the unused edge does contribute to an equal amount of wasteful power dissipation. It is therefore desirable to have a mechanism that enables useful operation on the unused clock edges.
SUMMARY OF THE INVENTION
The object of this invention is to provide a Programmable Logic Device with reduced power consumption at a given system performance.
To achieve this object the invention provides a Programmable logic Device (PLD) comprising Programmable Logic Blocks incorporating circuit arrangements of single edge flip-flops that are configurable for functioning as dual-edge triggered flip-flops operating on both edges of the clock signal so as to perform functions at an increased rate for a given clock frequency. In dual-edge triggered mode one of the flip-flops receives the clock directly while the other flip-flop receives the clock after inversion. The final output being obtained by multiplexing the outputs from the two flip-flops with the clock selecting the active output. The circuit arrangement is used as a memory element in a PLD and can be programmed to function as either a normal or a dual-edge flip-flop.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and advantages of the invention will become more apparent in reference to the following description and the accompanying drawings, wherein:
Fig-1 shows a block diagram of conventional Programmable Logic Block. Fig-2 shows the internal circuit of a conventional rising edge D flip-flop Fig-3 shows the internal state of a conventional rising edge D flip flop at CLK=0. Fig-4 shows the internal state of a conventional rising edge D flip flop at CLK=1.

Fig-5 shows the dual-edge-triggered D flip-flop system of the present invention.
Fig-6 shows the internal operation of the dual-edge-triggered flip-flop system for single edge
configuration mode.
Fig-7 shows the internal state of the dual-edge-triggered D flip-flop system at CLK=0 for
dual edge configuration mode
Fig-8 shows the internal state of the dual-edge-triggered D flip-flop system at CLK=1 for
Dual edge configuration mode.
Fig-9 shows timing diagrams for single edge and dual edge trigger D flip flop operations. FiglO shows the block diagram of a PLD logic block using the dual edge trigger D flip flop system according to the invention.
DETAILED DESCRIPTION
As shown in Fig.-l, a PLB 30 consists of LUTs 31, and one or more registering elements 32. Each registering element is typically a D flip-flop.
Figure 2 shows the internal structure of a D flip-flop 32. D flip-flop 32 comprises data latches 10, 11 connected in series through transistor switches 12, 13, 14, and 15 as shown. The input at Din 7 is connected sequentially to the output Q 8 on triggering the circuit at the rising edge of a clock cycle.
Figure 3 shows the internal states of a rising edge trigger D flip-flop when the clock control signal CLKF 75 is at logical "0". Switches 12 and 15 are ON while switches 13 and 14 are OFF. As a result Din 7 is passed to latchl 10, but is not latched into it and is also not passed to Iatch2 11. Switch 15 is ON in this mode, hence latch 11 provides the D flip-flop output Q 8.
Figure 4 shows the internal states when the clock CLKF 75 switches to "1". Switches 12 and 15 are now OFF while switches 13 and 14 are ON. In this case latch 10 is active and the information latched in latch 10 is passed through switch 13 to Iatch2 11. The data is not latched in latch 11 since switch 15 is open and the output of the flip-flop Q 8 is provided with the data that was latched into latch 10 in the previous clock transition.

Figure-5 shows a dual edge triggered flip-flop system 132. The system is provided two data inputs Dinl 107 and Din2 127 and a clock input CLKH 175 for generating two outputs Ql 108 and Q2 208. D flip-flops DFF2 105 and DFF1 106 are positive (rising) edge type of flip-flops. Flip-flop DFF1 106 has a multiplexer 152 at its clock input to select a direct clock input or inverted clock input based on configuration bit CB3 153. This selection can be used to configure the DFF1 106 as a positive edge trigger flip flop when direct clock input is selected or a negative edge flip flop when an inverted clock is selected. Similarly, flip-flop DFF2 105 has a clock input multiplexer 151 to make the flip flop positive edge trigger or negative edge trigger on the basis of configuration bit CB4 150. Input Dinl 107 is a dedicated input for flip flop DFF2 105 and an optional input for flip flop DFF1 106 whereas input Din2 127 is an optional input for flip flop DFF1 106. Multiplexer 120 selects one of the inputs 107 or 127 for flip flop DFF1 106 according to the value of configuration data CB1 119. In this example input 107 is selected when configuration bit 119 is "0", otherwise Din2 127 is selected. A second multiplexer 104 selects one of the flip-flop outputs 109 or 110 according to the value on select line 204, for final output 108. A third multiplexer 122 is used to provide the select line signal 204 for multiplexer 104 according to configuration data CB2 121. Clock signal 175 is used as a select line 204 if configuration data CB2 121 is set to "0" and select line 204 is set to "1" if configuration data CB2 121 is set to "1". Clock signal 175 is common for both flip flops DFF2 105 and DFF1 106.
Fig-6 describes the operation of the dual edge flip-flop system 132 when configured for single-edge mode. In this mode, multiplexers 151 and 152 select the normal clock inputs for flip-flops. DFF1 106 & DFF2 105. At the same time, configuration data 119 is set to "1" and multiplexer 120 selects data source Din2 127 as the data input for flip flop DFF1 106. Further, configuration data CB2 121 makes select line 204 "1" using multiplexer 122. This selects the DFF2 flip-flop output QP 110 as multiplexer 104 output Ql 108. DFF1 flip-flop output QN 109 is also available at Q2 208 output. At the positive edge of clock 175, flip flop DFF2 105 registers the data Dinl 107 for output Ql 108 whereas flip flop DFF1 106 is used to register data Din2 127 at the positive edge of clock 175 for output Q2 208. Accordingly, in this mode this system provides a normal operation with both flip-flops registering their respective data inputs at the positive edge of clock 175.
Fig 7 illustrates the dual-edge triggered mode of the present invention for the negative clock edge. CB1 119 is now configured as "0", so that, input Dinl 107 becomes a common input

for both flip flops DFF1 106 and DFF2 105. Configuration bit CB4 150 is configured to select the normal clock 175 for DFF2 105 and hence DFF2 105 operates as a positive edge triggered flip flop. Configuration bit CB3 153 is configured to select the inverted clock 175 for DFF1 106 and hence DFF1 106 operates as a negative edge triggered flip flop. In this configuration, DFF1 106 registers the data Dinl 107 at the negative edge of the clock 175 while DFF2 105 registers the data Dinl 107 at the positive edge of the clock 175.
Multiplexer 120 selects Dinl 107 as the data input for flip flop 106 and sets the valid output at QN 109. Multiplexer 122 compensates for the clock to output delay of flip flop 106 and sets select line 204 to "0" in response to clock signal 175. Accordingly, select line 204 selects output QN 109 for final output Ql 108.
At the positive edge of the clock 175 as shown in fig 8, flip flop 105 registers the data Dinl
107 and sets the valid output at QP 110. Multiplexer 122 compensates for the clock to output
delay of flip flop 105 and set select line 204 to "1" according to clock signal 175. The select
line 204 selects the output QP 110 for final output Ql 108. This enables a single data line to
be used to register the data at both the edges of the clock signal. At the positive edge of the
clock cycle DFF2 105 acts as a receiver for data input Din 107 and as a driver for output Q
108 while at the negative edge of the clock cycle, DFF1 106 becomes the receiver for data
input Din 107 and a driver for output Q 108. In this manner, the combination behaves like a
dual edge trigger D flip-flop 132.
Figure 9 shows the timing for different clock cycles and for the active flip-flop during a particular clock cycle. The timing diagram shows the operation for both the dual edge operation as well as the simple single positive edge triggered D operation. Before t = tl, when CLKH = "0", the value of DFF2 105 can not be reflected by data input Din 107 but at t = tl when CLKH changes from "0" to "1", the last data input Din 107 Dl (at t = tl) is registered into DFF2 105. This latched data is transmitted to output Q 108 after t = tl when CLKH = 1 (using 1st input of multiplexer 104). This is similar to the operation of a simple single positive edge triggered D-flip flop. At CLKH = 1, the value of DFF 1 106 can not be changed by changing data input Din 107 but at t = t2, when CLKH changes from "1" to "0", the last data input Din 107 D2 (at t = t2) is registered into DFF1 106 and this latched data is transmitted to output Q 108 after t=t2 when CLKH=0(using 0th input of multiplexer 104). This operation is similar to that of a negative edge trigger D type flip-flop. Therefore, the

present invention operates as a dual edge trigger D flip flop system that can access the data both at the rising (positive) edge and falling (negative) edge of a clock cycle. This renders the present invention capable of handling double the data rates as compared to a conventional positive (rising) edge triggered flip flop. In the case of conventional single rising edge D flip flop 32 there is an extra switching 200 that consumes extra power in the clock system. The extra power consumption can be avoided by using the dual edge triggered D Flip flop facility 132 while maintaining the efficiency of the system.
Figure 10 shows a PLB 130 according to the present invention. The PLB consists of LUTs 131 and the dual edge trigger D flip-flop system 132.
It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the above invention.
Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.

We claim:
1. A Programmable Logic Device providing reduction in the power consumption for
sequential logic and data storage functions, comprising at least one circuit arrangement
configurable to function as a dual-edge-triggered flip-flop operating on a selected one
or both edges of the circuit clock.
2. A Programmable Logic Device as claimed in claim 1, wherein the circuit arrangement
comprises two flip-flops, one of which is capable of being configured as rising edge
triggered while the other is configured as falling edge triggered with one of the flip-
flops latching data each time the clock changes state while the other remains inactive,
the outputs from two flip-flops being selectively enabled as the dual-edge-triggered
output by the clock signal.
3. A Programmable Logic Device as claimed in claim 1, wherein the dual-edge triggered
flip flop comprises two single edge-triggered flip flops triggered by two clock sources
that are configurable as complimentary clocks for dual edge-triggered operation or as
clocks with the same polarity for single-edge-triggered operation.
4. A Programmable Gate Array (PGA) providing reduction in power consumption for
sequential logic and data storage functions, comprising at least one circuit arrangement
configurable to function as a dual-edge-triggered flip-flop operating on a selected one
or both edges of the circuit clock.
5. A Programmable Gate Array as claimed in claim 4, wherein the circuit arrangement
comprises two flip-flops, one of which is capable of being configured as rising edge
triggered while the other is configured as falling edge triggered with one of the flip-
flops latching data each time the clock changes state while the other remains inactive,
the outputs from two flip-flops being selectively enabled as the dual-edge-triggered
output by the clock signal
6. A method of enabling reduction in power consumption for sequential logic and data
storage functions in a Programmable Logic Device, comprising the step of providing at

least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.
7. A Programmable Logic Device providing reduction in the power consumption for
sequential logic and data storage functions substantially as herein described with
reference to and as illustrated in figures 5 to 10 of the accompanying drawings.
8. A Programmable Gate Array (PGA) providing reduction in power consumption for
sequential logic and data storage functions substantially as herein described with
reference to and as illustrated in figures 5 to 10 of the accompanying drawings.